WO2009051191A1 - ドントケアビット抽出方法及びドントケアビット抽出プログラム - Google Patents

ドントケアビット抽出方法及びドントケアビット抽出プログラム Download PDF

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Publication number
WO2009051191A1
WO2009051191A1 PCT/JP2008/068775 JP2008068775W WO2009051191A1 WO 2009051191 A1 WO2009051191 A1 WO 2009051191A1 JP 2008068775 W JP2008068775 W JP 2008068775W WO 2009051191 A1 WO2009051191 A1 WO 2009051191A1
Authority
WO
WIPO (PCT)
Prior art keywords
don
care bit
bit extraction
care
input vector
Prior art date
Application number
PCT/JP2008/068775
Other languages
English (en)
French (fr)
Inventor
Kohei Miyase
Xiaoqing Wen
Seiji Kajihara
Original Assignee
Kyushu Institute Of Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyushu Institute Of Technology filed Critical Kyushu Institute Of Technology
Priority to KR1020107005777A priority Critical patent/KR101451461B1/ko
Priority to JP2009538142A priority patent/JP5221554B2/ja
Priority to CN200880112187.7A priority patent/CN101828122B/zh
Publication of WO2009051191A1 publication Critical patent/WO2009051191A1/ja
Priority to US12/761,643 priority patent/US8589751B2/en

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318307—Generation of test inputs, e.g. test vectors, patterns or sequences computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318594—Timing aspects

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

組合せ回路の入力線に順次印加する第１、第２の入力ベクトルによって活性化された組合せ回路内のパスを保証して第１、第２の入力ベクトルからドントケアビットを抽出することが可能なドントケアビット抽出方法及びドントケアビット抽出プログラムを提供する。 ０及び１の論理値ビットの組合せから構成されて、スキャン設計された順序回路内の又は単独の組合せ回路１０の入力線に順次印加される第１、第２の入力ベクトルＶ１、Ｖ２から、第１、第２のドントケアビットＸ１、Ｘ２を抽出するドントケアビット抽出方法であって、第１、第２の入力ベクトルＶ１、Ｖ２の印加によって活性化された組合せ回路１０内のパスＰｉの一部又は全部の活性化を保証して第１、第２の入力ベクトルＶ１、Ｖ２から第１、第２のドントケアビットＸ１、Ｘ２を抽出する抽出工程を有する。
PCT/JP2008/068775 2007-10-19 2008-10-16 ドントケアビット抽出方法及びドントケアビット抽出プログラム WO2009051191A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020107005777A KR101451461B1 (ko) 2007-10-19 2008-10-16 돈 케어 비트 추출 방법 및 돈 케어 비트 추출 프로그램을 기록한 컴퓨터로 판독 가능한 기록매체
JP2009538142A JP5221554B2 (ja) 2007-10-19 2008-10-16 ドントケアビット抽出方法及びドントケアビット抽出プログラム
CN200880112187.7A CN101828122B (zh) 2007-10-19 2008-10-16 无关位提取方法
US12/761,643 US8589751B2 (en) 2007-10-19 2010-04-16 Don't-care-bit identification method and don't-care-bit identification program

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-272496 2007-10-19
JP2007272496 2007-10-19

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/761,643 Continuation-In-Part US8589751B2 (en) 2007-10-19 2010-04-16 Don't-care-bit identification method and don't-care-bit identification program

Publications (1)

Publication Number Publication Date
WO2009051191A1 true WO2009051191A1 (ja) 2009-04-23

Family

ID=40567453

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/068775 WO2009051191A1 (ja) 2007-10-19 2008-10-16 ドントケアビット抽出方法及びドントケアビット抽出プログラム

Country Status (5)

Country Link
US (1) US8589751B2 (ja)
JP (1) JP5221554B2 (ja)
KR (1) KR101451461B1 (ja)
CN (1) CN101828122B (ja)
WO (1) WO2009051191A1 (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101828122B (zh) * 2007-10-19 2012-12-26 株式会社Lptex 无关位提取方法

Citations (3)

* Cited by examiner, † Cited by third party
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JP2641954B2 (ja) * 1990-02-07 1997-08-20 富士通株式会社 テストパターンの発生装置
JPH10134093A (ja) * 1996-10-28 1998-05-22 Matsushita Electric Ind Co Ltd 集積回路の性能推定装置及びその性能推定方法
JP3090929B2 (ja) * 1989-04-28 2000-09-25 富士通株式会社 ディレイ故障検査方式

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JP3231174B2 (ja) * 1993-10-18 2001-11-19 新日本製鐵株式会社 絞り性の良好な熱延高強度鋼板およびその製造方法
US5726996A (en) * 1995-09-18 1998-03-10 Nec Usa, Inc. Process for dynamic composition and test cycles reduction
US6018813A (en) * 1997-04-21 2000-01-25 Nec Usa, Inc. Identification and test generation for primitive faults
JP3137056B2 (ja) * 1997-11-19 2001-02-19 日本電気株式会社 故障伝搬経路抽出システム及びその方法並びにその制御プログラムを記録した記録媒体
US6223314B1 (en) * 1997-12-31 2001-04-24 Karim Arabi Method of dynamic on-chip digital integrated circuit testing
CN100421081C (zh) * 2001-06-01 2008-09-24 Nxp股份有限公司 数字系统及其错误检测方法
EP1475644A1 (en) * 2003-04-29 2004-11-10 Koninklijke Philips Electronics N.V. Data compression
CN100395557C (zh) * 2005-03-04 2008-06-18 清华大学 采用加权扫描选通信号的基于扫描的自测试结构的自测试方法
US8117513B2 (en) * 2005-03-30 2012-02-14 Lptex Corporation Test method and test program of semiconductor logic circuit device
US7444556B2 (en) * 2005-05-13 2008-10-28 Freescale Semiconductor, Inc. System and method of interleaving transmitted data
WO2007013306A1 (ja) * 2005-07-26 2007-02-01 Kyushu Institute Of Technology 半導体論理回路装置のテストベクトル生成方法及びテストベクトル生成プログラム
JP5017603B2 (ja) * 2005-11-30 2012-09-05 国立大学法人九州工業大学 変換装置、変換方法、変換方法をコンピュータに実行させることが可能なプログラム、及び、このプログラムを記録した記録媒体
JP5066684B2 (ja) * 2006-03-28 2012-11-07 国立大学法人九州工業大学 生成装置、生成方法、生成方法をコンピュータに実行させることが可能なプログラム、及び、このプログラムを記録した記録媒体
WO2008001818A1 (fr) * 2006-06-30 2008-01-03 Japan Science And Technology Agency dispositif de conversion, procédé de conversion, programme et support d'enregistrement
CN101828122B (zh) * 2007-10-19 2012-12-26 株式会社Lptex 无关位提取方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3090929B2 (ja) * 1989-04-28 2000-09-25 富士通株式会社 ディレイ故障検査方式
JP2641954B2 (ja) * 1990-02-07 1997-08-20 富士通株式会社 テストパターンの発生装置
JPH10134093A (ja) * 1996-10-28 1998-05-22 Matsushita Electric Ind Co Ltd 集積回路の性能推定装置及びその性能推定方法

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
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"VLSI Test Symposium, 19th IEEE Proceedings on. VTS 2001", 29 April 2001, article SANKARALINGAM, R. ET AL.: "Reducing power dissipation during test using scan chain disable", pages: 319 - 324 *

Also Published As

Publication number Publication date
US20100218063A1 (en) 2010-08-26
US8589751B2 (en) 2013-11-19
KR20100081295A (ko) 2010-07-14
CN101828122B (zh) 2012-12-26
JP5221554B2 (ja) 2013-06-26
KR101451461B1 (ko) 2014-10-15
JPWO2009051191A1 (ja) 2011-03-03
CN101828122A (zh) 2010-09-08

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