WO2009049546A1 - Circuit de contrôleur de disque dur à semi-conducteurs et disque dur à semi-conducteurs - Google Patents

Circuit de contrôleur de disque dur à semi-conducteurs et disque dur à semi-conducteurs Download PDF

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Publication number
WO2009049546A1
WO2009049546A1 PCT/CN2008/072654 CN2008072654W WO2009049546A1 WO 2009049546 A1 WO2009049546 A1 WO 2009049546A1 CN 2008072654 W CN2008072654 W CN 2008072654W WO 2009049546 A1 WO2009049546 A1 WO 2009049546A1
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WO
WIPO (PCT)
Prior art keywords
unit
data
pcie interface
interface
buffer
Prior art date
Application number
PCT/CN2008/072654
Other languages
English (en)
Chinese (zh)
Inventor
Xiaoping Zhang
Original Assignee
Huawei Technologies Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Publication of WO2009049546A1 publication Critical patent/WO2009049546A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0661—Format or protocol conversion arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G06F3/0607—Improving or facilitating administration, e.g. storage management by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Definitions

  • the present invention relates to the field of storage technologies, and in particular to a solid state hard disk controller circuit and a solid state hard disk based on the above controller circuit. Background technique
  • I0PS input/output per second
  • Flash-based solid-state drives (SSD id Sta Te Disk, SSD for short) came into being. Compared to traditional magnetic media hard disks with seek time of ms, flash-based SSDs have no seek time, only The data delay time is generally a us-level delay, so the SSD greatly improves the I0PS.
  • the interface of the existing SSD generally uses an Integrated Integrated Power (IDE) or Serial Advanced Technology Attachment (SATA) interface.
  • IDE Integrated Integrated Power
  • SATA Serial Advanced Technology Attachment
  • the inventors have found that at least the following problems exist in the prior art: Because the IDE uses a parallel bus interface, the bus frequency is low, so the bandwidth can only reach 200 MB at most, and can no longer be upgraded, so the SSD based on the IDE interface is slow. Slow will be eliminated; compared to IDE, SATA uses a serial data transmission, the bandwidth has been improved, theoretically up to 300MB, but its bandwidth can not be improved. Summary of the invention
  • An aspect of the present invention is to provide a solid state hard disk controller circuit that is connected to the controller The solid state drive of the circuit gets higher bandwidth.
  • Another aspect of the present invention provides a solid state hard disk that is connected to a device having a PCIE (PCI Expres s, PCIE) interface through the above controller circuit to obtain higher bandwidth.
  • PCIE PCI Expres s, PCIE
  • an embodiment of a solid state hard disk controller circuit includes: a PCIE interface conversion unit connected to a device having a PCIE interface through a PCIE interface, and configured to complete a PCIE interface data packet.
  • a flash controller interface unit for connecting to a flash memory to write data to or read data from the flash memory;
  • a buffer unit connected to the PCIE interface conversion unit and the flash controller interface unit, for And buffering the command and data sent by the PCIE interface conversion unit to the flash controller interface unit, buffering the command and data transmitted by the flash controller interface unit, and transmitting the command and data to the PCIE interface conversion unit.
  • the solid state hard disk controller circuit realizes connection with a server, a desktop computer, a notebook or other computer device having a PCIE interface through a PC IE interface conversion unit, through a buffer unit and a flash controller interface unit
  • the connection with the flash memory constitutes a solid state hard disk, and the PCIE interface can provide high bandwidth, so that the solid state hard disk connected to the solid state hard disk controller circuit can obtain higher bandwidth; the solid state hard disk can be directly accessed as a host PCIE device, and can Direct memory access (Di rect Memory Acces s, hereinafter referred to as DMA) operation, DMA operation saves CPU overhead.
  • DMA Direct memory access
  • an embodiment of a solid state hard disk of the present invention includes a PCIE interface connection unit, a controller circuit, and a flash memory, which are sequentially connected, wherein the controller circuit includes: a PCIE interface conversion unit, through PCIE
  • the interface connection unit is connected to the device having the PCIE interface for completing the parsing of the PCIE interface data packet; the flash controller interface unit is connected to the flash memory to write data to or read data from the flash memory.
  • a buffer unit connected to the PCIE interface conversion unit and the flash controller interface unit, configured to buffer the command and data transmitted by the PCIE interface conversion unit, and send the command to the flash controller interface And transmitting, by the unit, the commands and data transmitted by the flash controller interface unit to the PCIE interface conversion unit.
  • the PCIE interface can provide high bandwidth
  • the SSD connected to the SSD controller circuit can obtain higher bandwidth; the SSD can be directly accessed as the host's PCIE device, and can perform DMA operations, saving CPU overhead.
  • FIG. 1 is a schematic structural diagram of an embodiment of a solid state hard disk controller circuit according to the present invention.
  • Figure 2 is a schematic view showing the structure of Figure 1 further refined
  • FIG. 3 is a schematic structural diagram of an embodiment of a solid state drive according to the present invention. detailed description
  • FIG. 1 is a schematic structural diagram of an embodiment of a solid state hard disk controller circuit according to the present invention.
  • the SSD controller circuit includes a PCIE interface conversion unit 310, a buffer unit 320, and a flash controller interface unit 330, which are respectively connected in sequence.
  • the PCIE interface conversion unit 310 is connected to a device having a PCIE interface through a PCIE interface, and is used for parsing PCIE data packets.
  • the SSD is connected to the PCIE interface of the server, desktop, notebook or other computer device through the PCIE interface conversion unit 310.
  • the PCIE interface conversion unit 310 is used for serial-to-parallel conversion, unpacking/packaging processing, in addition to being connected to a device having a PCIE interface.
  • the PCIE interface conversion unit 310 needs to serially convert the data packets from the PCIE interface, and after 10b/8b decoding, passes through the physical layer, the data link layer, and the transport layer.
  • the PCIE interface conversion unit 310 will buffer the commands in the buffer unit 320 And the data is packaged layer by layer through the transport layer, the data link layer, and the physical layer. After 8b/ 10b encoding, and serial conversion, it is sent to the host through the PCIE interface.
  • the flash controller interface unit 330 is connected to the flash memory and will be connected from the buffer of the buffer unit 320.
  • the received data is written to the flash memory, or the data read from the flash memory is sent to the buffer of the buffer unit 320.
  • the buffer unit 320 is connected to the PCIE interface conversion unit 310 and the flash controller interface unit 330, and is configured to buffer the commands and data transmitted by the PCIE interface conversion unit 310, and then send the commands to the flash controller interface unit 330.
  • the commands and data transmitted by the controller interface unit 330 are buffered and sent to the PCIE interface conversion unit 310.
  • Fig. 2 is a schematic view showing the structure of Fig. 1 further refined.
  • the PCIE interface conversion unit 310 includes a serial-to-parallel conversion and decoding module 311, a packet parsing processing module 312, a packet encapsulation processing module 313, and a parallel-to-serial conversion and encoding module 314.
  • the serial to parallel conversion and decoding module 311 is configured to perform serial to parallel conversion on the data received by the PCIE interface, and then perform 10b/8b decoding processing; the packet parsing processing module 312, and the serial to parallel conversion and decoding module The 311 is connected, and is used for performing physical layer, data link layer, and processing layer layer-by-layer unpacking processing on the data packet transmitted by the serial-to-parallel conversion and decoding module 311, and then sending the command and data to the receiving buffer of the buffer unit 320.
  • the packet encapsulation processing module 313 is configured to perform layer-by-layer packing processing on the processing layer, the data link layer, and the physical layer of the command and data transmitted from the transmission buffer of the buffer unit 320; the parallel-to-serial conversion and encoding module 314
  • the packet encapsulation processing module 313 is connected to the 8b/10b code for the command and data transmitted by the packet encapsulation processing module 313, and then converted to the PCIE interface after parallel to serial conversion.
  • the buffer unit 320 includes: a receiving buffer module 321 and a transmission buffer module 322.
  • the receiving buffer module 321 is configured to receive commands and data sent by the PCIE interface conversion unit 310, and buffer the commands and data, and send the commands to the flash controller interface unit 330 in a first-in-first-out order;
  • the module 322 is configured to receive commands and data sent by the flash controller interface unit 330, and buffer the commands and data, and send the commands to the PCIE interface conversion unit 310 in a first-in first-out order.
  • the SSD controller circuit implements a connection with a server, a desktop computer, a notebook, or other computer device having a PCIE interface through the PCIE interface conversion unit 310; through the buffer unit 320 and the flash controller interface unit 330 and the flash memory.
  • the connection constitutes a solid state drive. Due to PCIE connection
  • the port can provide higher bandwidth, lLane can reach 250MB, 4Lane can reach 1000MB, so that the solid state drive connected to the SSD controller circuit can obtain higher bandwidth; the SSD can be directly accessed as the host PCIE device.
  • the reading delay of the conventional magnetic media hard disk is at the ms level, and the reading of the flash memory The delay is at the us level, so the flash-based solid state hard disk has a large difference in random read/write performance compared to the conventional magnetic media hard disk, and the advantage is obvious, so that the solid state hard disk connected to the solid state hard disk controller circuit can obtain higher I0PS.
  • the flash controller interface unit may include one or more controller interface connection modules, and each controller interface connection module may be connected to one or more pieces of flash memory.
  • each controller interface connection module may be connected to one or more pieces of flash memory.
  • the solid state hard disk includes a PCIE interface connection unit 500b, a controller circuit 100b, and a plurality of flash memories 400b connected in sequence.
  • the controller circuit 100b includes a PCIE interface conversion unit 310, a buffer unit 320, and a flash controller interface unit 330 that are sequentially connected.
  • the PCIE interface conversion unit 310 is connected to a device having a PCIE interface through the PCIE interface connection unit 500b.
  • the buffer unit 320 is connected to the PCIE interface conversion unit 310 and the flash controller interface unit 330, and is configured to buffer the commands and data transmitted by the PCIE interface conversion unit 310, and then send the commands to the flash controller interface unit 330.
  • the commands and data transmitted by the controller interface unit 330 are buffered and sent to the PCIE interface conversion unit 310.
  • the flash controller interface unit 330 is connected to the flash memory 400b to read data from or write data to the flash memory 400b.
  • the flash controller interface unit 330 includes one or more controller interface connection modules 331, each controller interface connection module 331 being coupled to one or more flash memories 40 Ob.
  • the flash memory 400b may be a Not-AND Ga te (NAND) type flash memory, or a Not-OR Ga te (NOR) type flash memory or other types of flash memory.
  • the selection of the flash controller interface unit 330 depends on the type of the flash memory. If the flash memory 400b is a NAND type flash memory, the flash controller interface unit supporting the NAND type flash memory is selected; if the flash memory 400b is the NOR type flash memory, the selection supports the NOR type flash memory. Flash controller interface unit.
  • the PCIE interface can provide high bandwidth, so that the solid state hard disk connected to the SSD controller circuit can obtain higher bandwidth; the SSD can be directly accessed as the host PCIE device, and can perform DMA operation, saving The overhead of the CPU; at the same time, because the access latency of the flash memory is superior to that of the conventional magnetic media hard disk, the read latency of the conventional magnetic media hard disk is at the ms level, and the read latency of the flash memory is at the us level, so based on Flash SSDs can achieve higher IOPs than traditional magnetic media drives.
  • a solid state hard disk based on a PC IE interface can implement a plurality of flash controller interface units, each flash controller interface unit includes at least one controller interface connection module, and each controller interface connection module can be connected to at least one flash memory to be flexible
  • the data concurrency between multiple controller interface connection modules and the multiple flash memories connected to each controller connection module can effectively improve the bandwidth of the SSD.
  • the controller circuit and the flash memory in the above embodiments may be an integrated structure or a discrete structure.
  • Each module in the controller circuit can be designed by using a Field Programmable Gate Array (FPGA) technology, or can be implemented by combining PCIE to PCI-X bridge and FPGA circuit, or using a processor. Parsing the PCIE interface data packet, and then combining the peripheral circuit to implement the solid state hard disk, or ⁇ 1 or more methods to form an ASIC (Appl ica t ion Spec if ic Intergra ted Ci rcui t, custom integrated circuit).
  • FPGA Field Programmable Gate Array

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

La présente invention concerne un circuit de contrôleur de disque dur à semi-conducteurs qui comporte une unité de conversion d'interface d'interconnexion de composants périphériques express, une unité tampon et une unité d'interface de contrôleur de mémoire flash connectées à tour de rôle. L'unité de conversion d'interface d'interconnexion de composants périphériques express est connectée à un dispositif équipé d'une interface d'interconnexion de composants périphériques express par l'intermédiaire d'une interface d'interconnexion de composants périphériques express pour terminer la résolution du bloc de données. L'unité tampon est connectée à l'unité de conversion d'interface d'interconnexion de composants périphériques express et à l'unité d'interface de contrôleur de mémoire flash. L'unité tampon met en mémoire tampon la commande et les données transmises par l'unité de conversion d'interface PCI Express et les envoie à l'unité d'interface de contrôleur de mémoire flash. L'unité tampon met en mémoire tampon la commande et les données transmises par l'unité d'interface de contrôleur de mémoire flash et les envoie à l'unité de conversion d'interface d'interconnexion de composants périphériques express. L'unité d'interface de contrôleur de mémoire flash est connectée à une mémoire flash pour écrire des données dans la mémoire flash et pour lire les données hors de la mémoire flash. La présente invention concerne également un disque à semi-conducteurs qui comporte l'unité de connexion à l'interface d'interconnexion de composants périphériques express, un circuit de contrôleur et une mémoire flash connectés à tour de rôle.
PCT/CN2008/072654 2007-10-19 2008-10-10 Circuit de contrôleur de disque dur à semi-conducteurs et disque dur à semi-conducteurs WO2009049546A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CNB2007101761118A CN100511122C (zh) 2007-10-19 2007-10-19 固态硬盘控制器电路及固态硬盘
CN200710176111.8 2007-10-19

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WO2009049546A1 true WO2009049546A1 (fr) 2009-04-23

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Cited By (5)

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US8635407B2 (en) 2011-09-30 2014-01-21 International Business Machines Corporation Direct memory address for solid-state drives
US9348518B2 (en) 2014-07-02 2016-05-24 International Business Machines Corporation Buffered automated flash controller connected directly to processor memory bus
US9542284B2 (en) 2014-08-06 2017-01-10 International Business Machines Corporation Buffered automated flash controller connected directly to processor memory bus
CN109427402A (zh) * 2017-08-23 2019-03-05 西安莫贝克半导体科技有限公司 固态硬盘
CN117423366A (zh) * 2023-12-14 2024-01-19 武汉麓谷科技有限公司 一种用于ssd固态硬盘的上电回路

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CN101442548B (zh) * 2008-12-17 2012-09-05 成都市华为赛门铁克科技有限公司 一种固态硬盘的操作方法和固态硬盘
CN101650639B (zh) * 2009-09-11 2012-01-04 成都市华为赛门铁克科技有限公司 一种存储装置及计算机系统
CN102129881A (zh) * 2010-01-15 2011-07-20 多利吉科技股份有限公司 适用于外设互联速捷接口的固态储存磁盘装置及系统
CN102073459B (zh) * 2010-11-02 2013-04-17 记忆科技(深圳)有限公司 基于固态硬盘的计算机系统及固态硬盘
CN102096560A (zh) * 2011-01-27 2011-06-15 浪潮电子信息产业股份有限公司 一种基于pci-e接口的多路固态硬盘加速方法
CN102693096B (zh) * 2012-05-17 2014-03-26 山西达鑫核科技有限公司 基于位的串行传输云存储方法及装置
CN102929813B (zh) * 2012-10-19 2016-06-01 浪潮电子信息产业股份有限公司 一种pci-e接口固态硬盘控制器的设计方法
CN104951237B (zh) * 2014-03-24 2018-04-27 北京强度环境研究所 基于sata接口固态硬盘的高速存储装置
CN105573929A (zh) * 2014-10-14 2016-05-11 中兴通讯股份有限公司 一种固态硬盘的控制器模块
CN105677239A (zh) * 2015-12-30 2016-06-15 中航网信(北京)科技有限公司 数据存储方法、装置和服务器
CN109165177A (zh) * 2018-09-21 2019-01-08 郑州云海信息技术有限公司 一种pcie接口的通信方法及相关装置
CN115033509B (zh) * 2022-06-30 2024-06-07 上海领存信息技术有限公司 一种磁盘阵列管理装置、磁盘阵列系统及服务器

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US8635407B2 (en) 2011-09-30 2014-01-21 International Business Machines Corporation Direct memory address for solid-state drives
US8683131B2 (en) 2011-09-30 2014-03-25 International Business Machines Corporation Direct memory address for solid-state drives
US9348518B2 (en) 2014-07-02 2016-05-24 International Business Machines Corporation Buffered automated flash controller connected directly to processor memory bus
US9852798B2 (en) 2014-07-02 2017-12-26 International Business Machines Corporation Buffered automated flash controller connected directly to processor memory bus
US10573392B2 (en) 2014-07-02 2020-02-25 International Business Machines Corporation Buffered automated flash controller connected directly to processor memory bus
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CN109427402A (zh) * 2017-08-23 2019-03-05 西安莫贝克半导体科技有限公司 固态硬盘
CN117423366A (zh) * 2023-12-14 2024-01-19 武汉麓谷科技有限公司 一种用于ssd固态硬盘的上电回路
CN117423366B (zh) * 2023-12-14 2024-03-15 武汉麓谷科技有限公司 一种用于ssd固态硬盘的上电回路

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CN100511122C (zh) 2009-07-08
CN101140502A (zh) 2008-03-12

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