WO2009048265A1 - Method of selectively etching semiconductor region, separation method of semiconductor layer and separation method of semiconductor device from substrate - Google Patents

Method of selectively etching semiconductor region, separation method of semiconductor layer and separation method of semiconductor device from substrate Download PDF

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Publication number
WO2009048265A1
WO2009048265A1 PCT/KR2008/005913 KR2008005913W WO2009048265A1 WO 2009048265 A1 WO2009048265 A1 WO 2009048265A1 KR 2008005913 W KR2008005913 W KR 2008005913W WO 2009048265 A1 WO2009048265 A1 WO 2009048265A1
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WIPO (PCT)
Prior art keywords
semiconductor
substrate
semiconductor region
gan
layer
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PCT/KR2008/005913
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French (fr)
Inventor
Sang Wan Ryu
Joon Mo Park
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Industry Foundation Of Chonnam National University
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Priority claimed from KR1020070103186A external-priority patent/KR100889978B1/en
Priority claimed from KR20080097552A external-priority patent/KR101001773B1/en
Application filed by Industry Foundation Of Chonnam National University filed Critical Industry Foundation Of Chonnam National University
Publication of WO2009048265A1 publication Critical patent/WO2009048265A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3063—Electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
    • H01L21/7813—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate leaving a reusable substrate, e.g. epitaxial lift off
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate

Definitions

  • the invention is related to method of selectively etching semiconductor region, separation method of semiconductor layer and separation method of semiconductor device from substrate, using the changes of etch rates depending on doping concentration, doping species of the semiconductor of in electrolytic etching the semiconductor layer.
  • the present invention has been made in view of the above problems, and an object of the invention is to provide a separation method of semiconductor layer and separation method of semiconductor device from substrate with high efficiency, easy manufacturing process, and low cost.
  • a method of selectively etching semiconductor region comprising: preparing an n-GaN- based first semiconductor region and GaN-based second semiconductor region of different doping type with first semiconductor region, on substrate, performing electrolytic etching using the first semiconductor region and second semiconductor region as an anode, and an electrolyte solution as a cathode, wherein etch rate of the first semiconductor region is higher than that of the first semiconductor region.
  • GaN-based semiconductor means that material consists of only Ga, or N, or includes at least one among III species such as In, Al or V species such as P, As, or Sb.
  • the electrolyte solution may include oxalic acid or KOH.
  • the second semiconductor region is undoped or P-doped region.
  • method of separating semiconductor structure from substrate comprising; preparing an semiconductor structure including n-GaN-based semiconductor layer, on a first substrate, attaching the semiconductor structure to a second substrate, and performing electrolytic etching using the semiconductor structure as an anode, and an electrolyte solution as a cathode, and separating the first substrate from the second substrate by the electrolytic etching of the n-GaN- based semiconductor layer.
  • method of Separating Semiconductor Structure from Substrate comprising! preparing an n-GaN-based first semiconductor layer and GaN-based second semiconductor layer of different doping type with first semiconductor region, and semiconductor device part, on a first substrate, attaching the semiconductor device part to a second substrate, and performing electrolytic etching using the first substrate and the second substrate as an anode, and an electrolyte solution as a cathode, wherein the first substrate is separated with the second substrate by removing the first semiconductor layer using the difference of each rate, each rate of first semiconductor layer being higher than that of the second semiconductor layer.
  • the second semiconductor layer may be included in optical device such as LED, or LD.
  • the second semiconductor layer may be portion of the semiconductor device part or inserted in the semiconductor device part as dummy layer.
  • the first substrate is semiconductor substrate and the second substrate is metal substrate.
  • a method of selectively etching semiconductor region comprising; preparing an n ⁇ GaN- based first semiconductor region and n-GaN-based second semiconductor region, on substrate, performing electrolytic etching using the first the semiconductor region as an anode, and an electrolyte solution as a cathode, wherein the etch rate of electrolytic etching is controlled by differently control doping concentrations of first semiconductor region and the second semiconductor region of different doping type with first semiconductor region, on substrate.
  • a method of selectively etching semiconductor region comprising; preparing an n-GaN- based first semiconductor region and n-GaN-based second semiconductor region, on substrate, preparing an etching accelerating layer in the second semiconductor region, and performing electrolytic etching using the first the semiconductor region as an anode, and an electrolyte solution as a cathode.
  • a method of Separating Semiconductor Structure from Substrate comprising; preparing an semiconductor device part including n-GaN-based first semiconductor region and GaN-based second semiconductor region, on a first substrate, attaching the semiconductor device part to a second substrate, performing electrolytic etching using the first substrate and the second substrate as an anode, and an electrolyte solution as a cathode, wherein the etch rate of electrolytic etching is controlled by differently control doping concentrations of first semiconductor region and the second semiconductor region, thus the second semiconductor region is removed.
  • a method of Separating Semiconductor Structure from Substrate comprising; preparing an semiconductor device part including n-GaN-based first semiconductor region and GaN-based second semiconductor region, on a first substrate, attaching the semiconductor device part to a second substrate, performing electrolytic etching using the first substrate and the second substrate as an anode, and an electrolyte solution as a cathode, wherein in electrolytic etching, the second semiconductor region is removed by preparing an etching accelerating layer in the second semiconductor region.
  • semiconductor structure which is grown on substrate can be easily separated by a method of electrolytic etching using electrolyte solution. If the present invention is applied to LED fabricating, the optical device including easily grown GaN-based substance can be grown on low thermal conductive sapphire substrate and transferred to high thermal conductive metal substrate which makes it possible to easily emit heat and it is effective on fabricating high-power LED.
  • FIG. 1 is a cross-sectional view for explaining a selective etching method of a semiconductor region in accordance with an exemplary embodiment of the present invention.
  • FIGS. 2 and 3 are photographs showing separation of semiconductor layers according to an experiment of the present invention.
  • FIG. 4 shows a graph of etch rate versus voltage in accordance with an exemplary embodiment of the present invention.
  • FIGS. 5 and 6 are views showing a method of separating a semiconductor structure in accordance with an exemplary embodiment of the present invention from a substrate.
  • FIGS. 7 and 8 are views for explaining preparation of a semiconductor structure for a delamination process of FIGS. 5 and 6.
  • FIG. 9 is a cross-sectional view showing a selective etching method of a semiconductor region in accordance with another exemplary embodiment of the present invention.
  • FIG. 10 shows an etch rate of Sample A
  • FIG. 11 shows an etch rate of Sample B.
  • FIGS. 12 and 13 show shapes after the etching process in accordance with another exemplary embodiment of the present invention.
  • FIG. 14 is a cross-sectional view showing a selective etching method of a semiconductor region in accordance with another exemplary embodiment of the present invention.
  • FIG. 15 is a cross-sectional view for explaining a selective etching method of a semiconductor region in accordance with another exemplary embodiment of the present invention.
  • FIG. 16 is a cross-sectional view for explaining a method of separating semiconductor device from substrate in accordance with exemplary embodiment of the present invention.
  • FIG. 1 is a cross-sectional view for explaining a selective etching method of a semiconductor region in accordance with an exemplary embodiment of the present invention.
  • FIG. 1 Referring to FIG. 1, a structure in which an n-GaN-based first semiconductor layer 130 and undoped-GaN-based second semiconductor layers 120 and 140 are deposited on a substrate 110 is shown.
  • Electrolytic etching is performed using the first semiconductor layer 130 and p-GaN-based second semiconductor layers 120 and 140 as an anode and an electrolyte solution as a cathode.
  • the electrolyte solution may include oxalic acid or KOH.
  • the n-GaN-based first semiconductor layer 130 has an etching speed substantially larger than that of the undoped-GaN-based second semiconductor layers 120 and 140.
  • the inventors have confirmed that, when the etching is performed using the above-mentioned oxalic acid or KOH electrolyte solution, the n-GaN-based first semiconductor layer has an etching speed substantially larger than those of the other conductivity types, for example, the undoped-GaN-based and p-GaN-based semiconductor layers.
  • the GaN-based semiconductor layer is used for a manufacturing method, applications to various manufacturing processes are possible.
  • FIGS. 2 and 3 are photographs showing separation of semiconductor layers according to an experiment of the present invention.
  • FIG. 4 shows a graph of etch rate versus voltage in accordance with an exemplary embodiment of the present invention.
  • the graph shows an etch rate varied depending on voltage, in a state in which the electrolyte solution of oxalic acid (COOH) 2 , under conditions of a concentration of 0.3M and a temperature of 10°C is fixed. As a result, a region from 20V to 60V shows a particularly high etch rate.
  • COOH oxalic acid
  • FIG. 5 and 6 are views showing a method of separating a semiconductor structure in accordance with an exemplary embodiment of the present invention from a substrate.
  • a substrate on which an n-GaN-based first semiconductor layer 230, and GaN-based second semiconductor layers 220 and 240 and a semiconductor structure 300 having different conductivity from the first semiconductor layer 230 are sequentially deposited on a first substrate 210 is prepared.
  • the semiconductor structure 300 is attached to a second substrate 500 using a well known method such as a method using an adhesive layer for attachment , and so on.
  • a portion of the semiconductor structure 300 or the entire semiconductor structure 300 may be deposited.
  • the semiconductor layers may be moved and attached on the second semiconductor layer having good thermal conductivity to accomplish the purpose.
  • each layer of the semiconductor structure 300 is not exposed by the electrolytic etching (an example of which will be described in detail with reference to FIG. 8), and the n-GaN-based semiconductor layer 230 is exposed to the electrolyte solution, such that the n-GaN-based semiconductor layer 230 is etched to separate both substrates from each other.
  • the semiconductor structure 300 may be transited from the first substrate 210 and then attached to the second substrate 500.
  • n-GaN-based semiconductor layer 230 when the n-GaN-based semiconductor layer 230 can be etched to perform a function of a sacrificial layer to thereby separate the first substrate 210 from the second substrate 500, it will be understood as being within the technical spirit of the present invention. That is, provided that other materials having good etching rates are employed when the n-GaN-based semiconductor layer is etched through the electrolytic etching, the present invention may not employ a GaN-based semiconductor layer having a different conductivity type from the first semiconductor layer 230.
  • FIGS. 7 and 8 are views for explaining preparation of a semiconductor structure for a delamination process of FIGS. 5 and 6.
  • an electrolyte solution In order to perform an electrolytic etching, an electrolyte solution must be in contact with an n-GaN layer 330 disposed thereunder, and an n-GaN layer 350 disposed thereon as a portion of an LED structure may not be removed.
  • an undoped GaN layer 320, an n-GaN-based semiconductor layer 330, and an undoped GaN layer 340 are sequentially formed on a first substrate 310, and then an n-GaN layer 350, an active layer360, and a p ⁇ GaN layer are formed thereon.
  • a separation operation is performed through the electrolytic etching with reference to the n-GaN-based semiconductor layer 330, wherein a hole is formed such that the electrolyte solution cannot arrive at the other n-GaN-based layer and can arrive at only the n-GaN-based semiconductor layer 330.
  • a passivation layer 410 is formed on a side part of the hole such that the electrolyte solution is in contact with only the n- GaN-based semiconductor layer 330 through the hole.
  • the passivation layer 410 is formed of a material having a lower etch rate than the n-GaN-based semiconductor layer through the electrolytic etching.
  • the n-GaN-based semiconductor layer 330 can smoothly separate the substrates even when the n-GaN-based material is deposited on the semiconductor device.
  • n-GaN-based semiconductor layer 330 is exposed and selectively etched to form the hole.
  • FIG. 9 is a cross-sectional view showing a selective etching method of a semiconductor region in accordance with another exemplary embodiment of the present invention.
  • an n-GaN-based first semiconductor layer 520, an undoped-GaN-based semiconductor layer 530, an n-GaN-based second semiconductor layer 540, an active layer 550, and a p-GaN-based semiconductor layer 560 are deposited on a substrate 500. Electrolytic etching is performed using the layers-deposited substrate as an anode and an electrolyte solution as a cathode.
  • the electrolyte solution may include oxalic acid or KOH.
  • the substrate may be formed of various kinds of materials without limitation, a sapphire substrate may be preferable when the GaN-based material is used.
  • Udoped-GaN-based semiconductor layers 510 may be formed as a buffer layer on the substrate 500.
  • the active layer 550 is formed between the n-GaN-based second semiconductor layer 540 and the p-GaN- based semiconductor layer 560.
  • the n-GaN-based first semiconductor layer 530 and the n-GaN-based second semiconductor layer 540 may have different etch rates by differently adjusting doping concentrations. That is, when a semiconductor has a high doping concentration, its etch rate is also high.
  • electrolytic etching characteristics of the n-GaN-based semiconductor depend on doping concentration of the GaN layer.
  • electrolytic etching was performed by varying a voltage using a sample in which n-GaN having n-type
  • FIG. 10 shows an etch rate of Sample A
  • FIG. 11 shows an etch rate of Sample B.
  • the undoped-GaN-based semiconductor layer 530 is formed between the n-GaN-based first semiconductor layer 520 and the n-GaN- based second semiconductor layer 540.
  • the undoped-GaN-based semiconductor layer is not an essential element of the present invention, and a desired type of liftoff may be implemented without the layer.
  • a desired type of liftoff may be implemented without the layer.
  • the liftoff process may be performed by selectively removing a lower n-GaN having a high doping concentration from a structure in which the undoped-GaN (u-GaN) is inserted therebetween.
  • an upper n-GaN is etched in a manner that a nano structure is partially formed from an edge thereof. That is, in the most regions, the upper n-GaN exists as it is.
  • the lower n-GaN of the inserted u-GaN is etched to prevent generation of electrolytic etching of the upper n-GaN due to contact between the electrolyte solution moved into an empty space and the upper n-GaN.
  • n-GaN shows two different characteristics during the electrolytic etching process.
  • the electrolytic etching process is performed in a manner that fine holes of nano ⁇ size are formed in the n ⁇ GaN, and second, the n-GaN layer is completely removed.
  • FIGS. 12 and 13 show shapes after the etching process.
  • Symbol O means formation of the nano structure
  • Symbol 0 means complete removal.
  • ⁇ 6i> Therefore, using this phenomenon, when an epitaxial structure for an emission structure such as LED, etc., has several n-GaN layers, only one of the layers may be selectively removed through appropriate variation in doping quantity and voltage adjustment to perform liftoff. This phenomenon may be applied to a semiconductor manufacturing process in various ways.
  • FIG. 14 is a cross-sectional view showing a selective etching method of a semiconductor region in accordance with another exemplary embodiment of the present invention.
  • FIG. 14 is different from FIG. 9 in that an etching accelerating layer 620a is further formed to increase an etch rate of the n-GaN-based semiconductor layer.
  • the method may include forming the etching accelerating layer 620a in the middle of forming the GaN-based semiconductor layer.
  • the etching accelerating layer 620a is formed by exposing a surface of a semiconductor layer, which is to form the etching accelerating layer 620a, to the air in the middle of forming the GaN-based semiconductor layer.
  • This phenomenon may be supposed as a natural oxide layer of several to several tens of A formed in the process of exposing the semiconductor layer to the air or an impurity layer acts as an etching accelerating layer.
  • an oxide layer may be intentionally formed through an oxygen surface treatment in a high temperature chamber instead of exposure to the air, or an impurity layer such as Si, Ge, Sn, or the like, may be intentionally formed to function as the etching accelerating layer.
  • the oxide layer or the impurity layer may have a thickness of several to several tens of A.
  • the etching accelerating layer 620a is inserted into the semiconductor region, in which etching must be relatively rapidly performed, and etched, the inserted part is abruptly etched such that the semiconductor region including the etching accelerating layer 620a allows the etchant to be injected into a wide region through the etching accelerating layer 620a.
  • the semiconductor region is more rapidly etched than other semiconductor regions. Therefore, even when the semiconductor regions have different doping concentrations, a desired purpose can be accomplished by only inserting the etching accelerating layer.
  • FIG. 15 is a cross-sectional view for explaining a selective etching method of a semiconductor region in accordance with another exemplary embodiment of the present invention.
  • n-GaN-based first semiconductor layer 720 and an n-GaN-based second semiconductor layer 730 are deposited on a substrate 700 is shown and an undoped-GaN-based semiconductor layer 710 is placed below of n-GaN-based first semiconductor layer 720.
  • the n-GaN-based first semiconductor layer 720 has higher doping concentration than the n-GaN-based second semiconductor layer 730 and consequently it has high etch rate.
  • n-GaN-based first semiconductor layer 720 is quickly etched, a current path is largely extended when electrolytic etching is performed on n-GaN-based second semiconductor layer 730.
  • the current path of etching process is shown in a dotted line.
  • the n-GaN-based second semiconductor layer 730 has high electric resistance and electrolytic etching rate is largely decreased.
  • FIG. 16 is a cross-sectional view for explaining a method of separating semiconductor device from substrate in accordance with exemplary embodiment of the present invention.
  • n-GaN-based first semiconductor layer 520, an undoped GaN-based semiconductor layer 530, an n-GaN-based second semiconductor layer 540, an active layer 550 and a p-GaN-based semiconductor layer 560 are deposited on a first substrate 500 is shown.
  • the n-GaN-based second semiconductor 540, the active layer 550 and the p-GaN-based semiconductor layer 560 will finally compose a semiconductor device A. Therefore, they should be transferred to the second substrate 800 after lift-off process.
  • the semiconductor device A which is formed at the first substrate is attached to the second substrate 800. Then, electrolytic etching is performed using the first substrate 500 and the second substrate as an anode and an electrolyte solution as a cathode.
  • the n-GaN-based first semiconductor layer 520 and the n-GaN-based second semiconductor layer 540 may have different etching rates by differently adjusting doping concentrations.
  • the semiconductor device A is separated from substrate by removing the n-GaN- based first semiconductor layer 520.
  • the first substrate 500 may be a semiconductor substrate and the metal substrate can be used as a second substrate 800.
  • FIG. 15 and FIG.16 Furthermore, the method of separating semiconductor device from substrate was explained using FIG. 5, but it is also possible to adjust FIG. 15 and FIG.16. That is, like FIG. 9, using etching accelerating layer inside of the second semiconductor region, the second semiconductor's etching is more rapidly accelerated than the first semiconductor region. The second semiconductor region is removed by etching acceleration and it can be separated from substrate.
  • the etching accelerating layer can be formed by oxidation treatment, impurity treatment and exposing to the air in the middle of forming the second semiconductor region.

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Abstract

A method of selectively etching semiconductor region is provided. The method comprises preparing an n-GaN-based first semiconductor region and GaN-based second semiconductor region of different doping type with first semiconductor region, on substrate, and performing electrolytic etching using the first semiconductor region and second semiconductor region as an anode, and an electrolyte solution as a cathode, wherein etch rate of the first semiconductor region is higher than that of the first semiconductor region.

Description

[DESCRIPTION] [Invention Title]
METHOD OF SELECTIVELY ETCHING SEMICONDUCTOR REGION, SEPARATION METHOD OF SEMICONDUCTOR LAYER AND SEPARATION METHOD OF SEMICONDUCTOR DEVICE FROM SUBSTRATE
[Technical Field]
<i> The invention is related to method of selectively etching semiconductor region, separation method of semiconductor layer and separation method of semiconductor device from substrate, using the changes of etch rates depending on doping concentration, doping species of the semiconductor of in electrolytic etching the semiconductor layer.
[Background Art]
<2> With rising demand for high-efficiency and high-power operation of LED, the need for emitting heat quickly out the heat generating LED chip is increasing. The method for separating LED epi layer from sapphire substrate through lift-off process and attaching it to metal substrate shows the maximum efficiency of heat emission up to now. According to this, it has become possible to emit heat not through low thermal conductive sapphire substrate but through high thermal conductive metal substrate. This can be applied to fabricating high-power LED. The Korean registration gazette No. 495215 explains embodiment of these methods.
<3> However, a method of using laser beam which is usually used for liftoff process has many problems such as it costs high to process and takes a long process time for small laser exposure area. Furthermore, the stress which is caused by laser exposure has bad effect on reliability of semiconductor device. [Disclosure] [Technical Problem]
<4> The present invention has been made in view of the above problems, and an object of the invention is to provide a separation method of semiconductor layer and separation method of semiconductor device from substrate with high efficiency, easy manufacturing process, and low cost. [Technical Solution]
<5> According to an aspect of the present invention, a method of selectively etching semiconductor region, comprising: preparing an n-GaN- based first semiconductor region and GaN-based second semiconductor region of different doping type with first semiconductor region, on substrate, performing electrolytic etching using the first semiconductor region and second semiconductor region as an anode, and an electrolyte solution as a cathode, wherein etch rate of the first semiconductor region is higher than that of the first semiconductor region.
<6> "GaN"-based semiconductor means that material consists of only Ga, or N, or includes at least one among III species such as In, Al or V species such as P, As, or Sb.
<7> The electrolyte solution may include oxalic acid or KOH.
<8> Preferably, the second semiconductor region is undoped or P-doped region.
<9> According to another aspect of the present invention, method of separating semiconductor structure from substrate, comprising; preparing an semiconductor structure including n-GaN-based semiconductor layer, on a first substrate, attaching the semiconductor structure to a second substrate, and performing electrolytic etching using the semiconductor structure as an anode, and an electrolyte solution as a cathode, and separating the first substrate from the second substrate by the electrolytic etching of the n-GaN- based semiconductor layer.
<io> According to still another aspect of the present invention, method of Separating Semiconductor Structure from Substrate, comprising! preparing an n-GaN-based first semiconductor layer and GaN-based second semiconductor layer of different doping type with first semiconductor region, and semiconductor device part, on a first substrate, attaching the semiconductor device part to a second substrate, and performing electrolytic etching using the first substrate and the second substrate as an anode, and an electrolyte solution as a cathode, wherein the first substrate is separated with the second substrate by removing the first semiconductor layer using the difference of each rate, each rate of first semiconductor layer being higher than that of the second semiconductor layer.
<ii> The second semiconductor layer may be included in optical device such as LED, or LD. The second semiconductor layer may be portion of the semiconductor device part or inserted in the semiconductor device part as dummy layer.
<12> Preferably, the first substrate is semiconductor substrate and the second substrate is metal substrate.
<13> According to still another aspect of the present invention, a method of selectively etching semiconductor region, comprising; preparing an n~GaN- based first semiconductor region and n-GaN-based second semiconductor region, on substrate, performing electrolytic etching using the first the semiconductor region as an anode, and an electrolyte solution as a cathode, wherein the etch rate of electrolytic etching is controlled by differently control doping concentrations of first semiconductor region and the second semiconductor region of different doping type with first semiconductor region, on substrate.
<i4> According to still another aspect of the present invention, a method of selectively etching semiconductor region, comprising; preparing an n-GaN- based first semiconductor region and n-GaN-based second semiconductor region, on substrate, preparing an etching accelerating layer in the second semiconductor region, and performing electrolytic etching using the first the semiconductor region as an anode, and an electrolyte solution as a cathode.
<15> According to still another aspect of the present invention, a method of Separating Semiconductor Structure from Substrate, comprising; preparing an semiconductor device part including n-GaN-based first semiconductor region and GaN-based second semiconductor region, on a first substrate, attaching the semiconductor device part to a second substrate, performing electrolytic etching using the first substrate and the second substrate as an anode, and an electrolyte solution as a cathode, wherein the etch rate of electrolytic etching is controlled by differently control doping concentrations of first semiconductor region and the second semiconductor region, thus the second semiconductor region is removed.
<16> According to still another aspect of the present invention, a method of Separating Semiconductor Structure from Substrate, comprising; preparing an semiconductor device part including n-GaN-based first semiconductor region and GaN-based second semiconductor region, on a first substrate, attaching the semiconductor device part to a second substrate, performing electrolytic etching using the first substrate and the second substrate as an anode, and an electrolyte solution as a cathode, wherein in electrolytic etching, the second semiconductor region is removed by preparing an etching accelerating layer in the second semiconductor region. [Advantageous Effects]
<17> According to present invention, semiconductor structure which is grown on substrate can be easily separated by a method of electrolytic etching using electrolyte solution. If the present invention is applied to LED fabricating, the optical device including easily grown GaN-based substance can be grown on low thermal conductive sapphire substrate and transferred to high thermal conductive metal substrate which makes it possible to easily emit heat and it is effective on fabricating high-power LED. [Description of Drawings]
<18> FIG. 1 is a cross-sectional view for explaining a selective etching method of a semiconductor region in accordance with an exemplary embodiment of the present invention.
<19> FIGS. 2 and 3 are photographs showing separation of semiconductor layers according to an experiment of the present invention.
<20> FIG. 4 shows a graph of etch rate versus voltage in accordance with an exemplary embodiment of the present invention.
<2i> FIGS. 5 and 6 are views showing a method of separating a semiconductor structure in accordance with an exemplary embodiment of the present invention from a substrate. <22> FIGS. 7 and 8 are views for explaining preparation of a semiconductor structure for a delamination process of FIGS. 5 and 6. <23> FIG. 9 is a cross-sectional view showing a selective etching method of a semiconductor region in accordance with another exemplary embodiment of the present invention. <24> FIG. 10 shows an etch rate of Sample A, and FIG. 11 shows an etch rate of Sample B. <25> FIGS. 12 and 13 show shapes after the etching process in accordance with another exemplary embodiment of the present invention. <26> FIG. 14 is a cross-sectional view showing a selective etching method of a semiconductor region in accordance with another exemplary embodiment of the present invention. <27> FIG. 15 is a cross-sectional view for explaining a selective etching method of a semiconductor region in accordance with another exemplary embodiment of the present invention. <28> FIG. 16 is a cross-sectional view for explaining a method of separating semiconductor device from substrate in accordance with exemplary embodiment of the present invention.
[Mode for Invention] <29> Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the embodiments. In the drawings, like reference numerals refer to like elements. <30> FIG. 1 is a cross-sectional view for explaining a selective etching method of a semiconductor region in accordance with an exemplary embodiment of the present invention. <3i> Referring to FIG. 1, a structure in which an n-GaN-based first semiconductor layer 130 and undoped-GaN-based second semiconductor layers 120 and 140 are deposited on a substrate 110 is shown. Electrolytic etching is performed using the first semiconductor layer 130 and p-GaN-based second semiconductor layers 120 and 140 as an anode and an electrolyte solution as a cathode. The electrolyte solution may include oxalic acid or KOH.
<32> When the electrolytic etching is performed using the electrolyte solution, the n-GaN-based first semiconductor layer 130 has an etching speed substantially larger than that of the undoped-GaN-based second semiconductor layers 120 and 140.
<33> The inventors have confirmed that, when the etching is performed using the above-mentioned oxalic acid or KOH electrolyte solution, the n-GaN-based first semiconductor layer has an etching speed substantially larger than those of the other conductivity types, for example, the undoped-GaN-based and p-GaN-based semiconductor layers. When the GaN-based semiconductor layer is used for a manufacturing method, applications to various manufacturing processes are possible.
<34> FIGS. 2 and 3 are photographs showing separation of semiconductor layers according to an experiment of the present invention.
<35> This experiment shows results performed in an electrolyte solution of oxalic acid (COOH)2, under conditions of a concentration of 0.3M, a voltage of
40V, and a temperature of 10"C . <36> FIG. 4 shows a graph of etch rate versus voltage in accordance with an exemplary embodiment of the present invention. <37> The graph shows an etch rate varied depending on voltage, in a state in which the electrolyte solution of oxalic acid (COOH)2, under conditions of a concentration of 0.3M and a temperature of 10°C is fixed. As a result, a region from 20V to 60V shows a particularly high etch rate. <38> (Method of Separating Semiconductor Structure from Substrate) <39> Next, FIGS. 5 and 6 are views showing a method of separating a semiconductor structure in accordance with an exemplary embodiment of the present invention from a substrate. <40> Referring to FIG. 5, a substrate on which an n-GaN-based first semiconductor layer 230, and GaN-based second semiconductor layers 220 and 240 and a semiconductor structure 300 having different conductivity from the first semiconductor layer 230 are sequentially deposited on a first substrate 210 is prepared.
<4i> Then, the semiconductor structure 300 is attached to a second substrate 500 using a well known method such as a method using an adhesive layer for attachment , and so on.
<42> A portion of the semiconductor structure 300 or the entire semiconductor structure 300 may be deposited. Of course, in this embodiment, after growing the semiconductor layers on the first substrate 210 on which growth can be readily performed and heat transfer is disadvantageous, the semiconductor layers may be moved and attached on the second semiconductor layer having good thermal conductivity to accomplish the purpose.
<43> In FIG. 5, each layer of the semiconductor structure 300 is not exposed by the electrolytic etching (an example of which will be described in detail with reference to FIG. 8), and the n-GaN-based semiconductor layer 230 is exposed to the electrolyte solution, such that the n-GaN-based semiconductor layer 230 is etched to separate both substrates from each other. Eventually, the semiconductor structure 300 may be transited from the first substrate 210 and then attached to the second substrate 500.
<44> In this embodiment, when the n-GaN-based semiconductor layer 230 can be etched to perform a function of a sacrificial layer to thereby separate the first substrate 210 from the second substrate 500, it will be understood as being within the technical spirit of the present invention. That is, provided that other materials having good etching rates are employed when the n-GaN-based semiconductor layer is etched through the electrolytic etching, the present invention may not employ a GaN-based semiconductor layer having a different conductivity type from the first semiconductor layer 230.
<45> (Method of Separating Semiconductor Device from Substrate)
<46> FIGS. 7 and 8 are views for explaining preparation of a semiconductor structure for a delamination process of FIGS. 5 and 6. In order to perform an electrolytic etching, an electrolyte solution must be in contact with an n-GaN layer 330 disposed thereunder, and an n-GaN layer 350 disposed thereon as a portion of an LED structure may not be removed.
<47> Referring to FIG. 7, an undoped GaN layer 320, an n-GaN-based semiconductor layer 330, and an undoped GaN layer 340 are sequentially formed on a first substrate 310, and then an n-GaN layer 350, an active layer360, and a p~GaN layer are formed thereon.
<48> Next, a separation operation is performed through the electrolytic etching with reference to the n-GaN-based semiconductor layer 330, wherein a hole is formed such that the electrolyte solution cannot arrive at the other n-GaN-based layer and can arrive at only the n-GaN-based semiconductor layer 330.
<49> Referring to FIG. 8, a passivation layer 410 is formed on a side part of the hole such that the electrolyte solution is in contact with only the n- GaN-based semiconductor layer 330 through the hole. The passivation layer 410 is formed of a material having a lower etch rate than the n-GaN-based semiconductor layer through the electrolytic etching.
<50> When the passivation layer 410 is formed on the side part of the hole, the n-GaN-based semiconductor layer 330 can smoothly separate the substrates even when the n-GaN-based material is deposited on the semiconductor device.
<5i> In this case, before attaching the semiconductor device to the second substrate, at least a portion of the n-GaN-based semiconductor layer 330 is exposed and selectively etched to form the hole.
<52> Hereinafter, another exemplary embodiment in accordance with the present invention will be described.
<53> FIG. 9 is a cross-sectional view showing a selective etching method of a semiconductor region in accordance with another exemplary embodiment of the present invention.
<54> Referring to FIG. 9, an n-GaN-based first semiconductor layer 520, an undoped-GaN-based semiconductor layer 530, an n-GaN-based second semiconductor layer 540, an active layer 550, and a p-GaN-based semiconductor layer 560 are deposited on a substrate 500. Electrolytic etching is performed using the layers-deposited substrate as an anode and an electrolyte solution as a cathode. The electrolyte solution may include oxalic acid or KOH.
<55> While the substrate may be formed of various kinds of materials without limitation, a sapphire substrate may be preferable when the GaN-based material is used. Udoped-GaN-based semiconductor layers 510 may be formed as a buffer layer on the substrate 500. In addition, the active layer 550 is formed between the n-GaN-based second semiconductor layer 540 and the p-GaN- based semiconductor layer 560.
<56> According to the present invention, the n-GaN-based first semiconductor layer 530 and the n-GaN-based second semiconductor layer 540 may have different etch rates by differently adjusting doping concentrations. That is, when a semiconductor has a high doping concentration, its etch rate is also high.
<57> The inventors have found that electrolytic etching characteristics of the n-GaN-based semiconductor depend on doping concentration of the GaN layer. In order to verify this assumption, electrolytic etching was performed by varying a voltage using a sample in which n-GaN having n-type
1P, -1^ 1ft N—"3 doping concentrations of 1.0x10 cm (Sample A) and 7.7x10 cm (Sample B) was disposed between undoped GaN and grown. Therefore, it is possible to measure an electrolytic etch rate of the n-GaN along side surfaces thereof. FIG. 10 shows an etch rate of Sample A, and FIG. 11 shows an etch rate of Sample B.
<58> Referring to FIG. 9, the undoped-GaN-based semiconductor layer 530 is formed between the n-GaN-based first semiconductor layer 520 and the n-GaN- based second semiconductor layer 540.
<59> Meanwhile, the undoped-GaN-based semiconductor layer is not an essential element of the present invention, and a desired type of liftoff may be implemented without the layer. However, in order to more effectively use a relative difference in etch rate of the two layers having different doping concentrations, it will be more effective to insert the undoped-GaN layer therebetween. The liftoff process may be performed by selectively removing a lower n-GaN having a high doping concentration from a structure in which the undoped-GaN (u-GaN) is inserted therebetween. Due to the difference in doping concentration, while the lower n-GaN is completely removed, an upper n-GaN is etched in a manner that a nano structure is partially formed from an edge thereof. That is, in the most regions, the upper n-GaN exists as it is. The lower n-GaN of the inserted u-GaN is etched to prevent generation of electrolytic etching of the upper n-GaN due to contact between the electrolyte solution moved into an empty space and the upper n-GaN.
<60> Referring to FIGS. 10 and 11, it will be appreciated that Sample B having high doping concentration has substantially a higher etch rate. The n-GaN shows two different characteristics during the electrolytic etching process. First, the electrolytic etching process is performed in a manner that fine holes of nano~size are formed in the n~GaN, and second, the n-GaN layer is completely removed. FIGS. 12 and 13 show shapes after the etching process. As a result of measurement, it will be appreciated that a nano structure is formed from Sample A at every voltages, and the n-GaN layer is completely removed from Sample B at a section of 50 ~ 60V, but a nano structure is formed from other sections. In FIGS. 10 and 11, Symbol O means formation of the nano structure, and Symbol 0 means complete removal.
<6i> Therefore, using this phenomenon, when an epitaxial structure for an emission structure such as LED, etc., has several n-GaN layers, only one of the layers may be selectively removed through appropriate variation in doping quantity and voltage adjustment to perform liftoff. This phenomenon may be applied to a semiconductor manufacturing process in various ways.
<62> FIG. 14 is a cross-sectional view showing a selective etching method of a semiconductor region in accordance with another exemplary embodiment of the present invention.
<63> For the convenience of description, difference from FIG. 9 will be described. FIG. 14 is different from FIG. 9 in that an etching accelerating layer 620a is further formed to increase an etch rate of the n-GaN-based semiconductor layer. <64> The method may include forming the etching accelerating layer 620a in the middle of forming the GaN-based semiconductor layer.
<65> While a specific method of forming the etching accelerating layer 620a may be performed in various ways without limitation, it is of course convenient to use a simple process. The inventors have found a phenomenon that the etching accelerating layer 620a is formed by exposing a surface of a semiconductor layer, which is to form the etching accelerating layer 620a, to the air in the middle of forming the GaN-based semiconductor layer. This phenomenon may be supposed as a natural oxide layer of several to several tens of A formed in the process of exposing the semiconductor layer to the air or an impurity layer acts as an etching accelerating layer.
<66> Therefore, an oxide layer may be intentionally formed through an oxygen surface treatment in a high temperature chamber instead of exposure to the air, or an impurity layer such as Si, Ge, Sn, or the like, may be intentionally formed to function as the etching accelerating layer. The oxide layer or the impurity layer may have a thickness of several to several tens of A.
<67> Meanwhile, when the etching accelerating layer 620a is inserted into the semiconductor region, in which etching must be relatively rapidly performed, and etched, the inserted part is abruptly etched such that the semiconductor region including the etching accelerating layer 620a allows the etchant to be injected into a wide region through the etching accelerating layer 620a. As a result, the semiconductor region is more rapidly etched than other semiconductor regions. Therefore, even when the semiconductor regions have different doping concentrations, a desired purpose can be accomplished by only inserting the etching accelerating layer.
<68> FIG. 15 is a cross-sectional view for explaining a selective etching method of a semiconductor region in accordance with another exemplary embodiment of the present invention.
<69> Referring to FIG. 15, a structure in which an n-GaN-based first semiconductor layer 720 and an n-GaN-based second semiconductor layer 730 are deposited on a substrate 700 is shown and an undoped-GaN-based semiconductor layer 710 is placed below of n-GaN-based first semiconductor layer 720. The n-GaN-based first semiconductor layer 720 has higher doping concentration than the n-GaN-based second semiconductor layer 730 and consequently it has high etch rate.
<70> Referring to FIG. 15, if an n-GaN-based first semiconductor layer 720 is quickly etched, a current path is largely extended when electrolytic etching is performed on n-GaN-based second semiconductor layer 730. The current path of etching process is shown in a dotted line. As a result of that, the n-GaN-based second semiconductor layer 730 has high electric resistance and electrolytic etching rate is largely decreased. Like FIG. 1, it becomes possible to remove first semiconductor layer 720 without inserting an undoped GaN between both of the two n-GaN semiconductor layers.
<7i> Using above-mentioned method of selectively etching semiconductor region, a method of separating semiconductor device from substrate will be described.
<72> FIG. 16 is a cross-sectional view for explaining a method of separating semiconductor device from substrate in accordance with exemplary embodiment of the present invention.
<73> A structure in which an n-GaN-based first semiconductor layer 520, an undoped GaN-based semiconductor layer 530, an n-GaN-based second semiconductor layer 540, an active layer 550 and a p-GaN-based semiconductor layer 560 are deposited on a first substrate 500 is shown. Among the deposited layers, the n-GaN-based second semiconductor 540, the active layer 550 and the p-GaN-based semiconductor layer 560 will finally compose a semiconductor device A. Therefore, they should be transferred to the second substrate 800 after lift-off process.
<74> Next, the semiconductor device A which is formed at the first substrate is attached to the second substrate 800. Then, electrolytic etching is performed using the first substrate 500 and the second substrate as an anode and an electrolyte solution as a cathode. The n-GaN-based first semiconductor layer 520 and the n-GaN-based second semiconductor layer 540 may have different etching rates by differently adjusting doping concentrations. The semiconductor device A is separated from substrate by removing the n-GaN- based first semiconductor layer 520.
<75> The first substrate 500 may be a semiconductor substrate and the metal substrate can be used as a second substrate 800.
<76> Furthermore, the method of separating semiconductor device from substrate was explained using FIG. 5, but it is also possible to adjust FIG. 15 and FIG.16. That is, like FIG. 9, using etching accelerating layer inside of the second semiconductor region, the second semiconductor's etching is more rapidly accelerated than the first semiconductor region. The second semiconductor region is removed by etching acceleration and it can be separated from substrate. The etching accelerating layer can be formed by oxidation treatment, impurity treatment and exposing to the air in the middle of forming the second semiconductor region.

Claims

[CLAIMS] [Claim 1]
A method of selectively etching semiconductor region, comprising : Preparing an n-GaN-based first semiconductor region and GaN-based second semiconductor region of different doping type with first semiconductor region, on substrate,
Performing electrolytic etching using the first semiconductor region and second semiconductor region as an anode, and an electrolyte solution as a cathode,
Wherein etch rate of the first semiconductor region is higher than that of the first semiconductor region. [Claim 2]
The method according to claim 1, wherein the electrolyte solution include s oxalic acid or KOH. [Claim 3]
The method according to claim 1, wherein the second semiconductor region is undoped or P-doped region. [Claim 4]
Method of Separating Semiconductor Structure from Substrate, comprising;
Preparing an semiconductor structure including n-GaN-based semiconductor layer, on a first substrate,
Attaching the semiconductor structure to a second substrate, Performing electrolytic etching using the semiconductor structure as an anode, and an electrolyte solution as a cathode,
Separating the first substrate from the second substrate by the electrolytic etching of the n-GaN-based semiconductor layer, [Claim 5]
The method according to claim 4, wherein the electrolyte solution include s oxalic acid or KOH. [Claim 6] Method of Separating Semiconductor Structure from Substrate, comprising;
Preparing an n-GaN-based first semiconductor layer and GaN-based second semiconductor layer of different doping type with first semiconductor region, and semiconductor device part, on a first substrate, attaching the semiconductor device part to a second substrate, performing electrolytic etching using the first substrate and the second substrate as an anode, and an electrolyte solution as a cathode, wherein the first substrate is separated with the second substrate by removing the first semiconductor layer using the difference of each rate, each rate of first semiconductor layer being higher than that of the second semiconductor layer. [Claim 7]
The method according to claim 6, wherein the electrolyte solution include s oxalic acid or KOH. [Claim 8]
The method according to claim 6, wherein the second semiconductor region is undoped or P-doped region. [Claim 9]
The method according to claim 6, wherein the second semiconductor region is undoped or P-doped region. [Claim 10]
The method according to claim 6, further comprising the step of selectively etching at least portion of the semiconductor device part and the second semiconductor region, before attaching the semiconductor device part to a second substrate. [Claim 11]
The method according to claim 10, further comprising the step of forming protection layer, after selectively etching. [Claim 12]
The method according to claim 6, wherein the first substrate is semiconductor substrate and the second substrate is metal substrate. [Claim 13]
The method according to claim 6, wherein the second semiconductor layer is placed on and below the first semiconductor layer. [Claim 14]
A method of selectively etching semiconductor region, comprising;
Preparing an n-GaN-based first semiconductor region and n-GaN-based second semiconductor region, on substrate,
Performing electrolytic etching using the first the semiconductor region as an anode, and an electrolyte solution as a cathode, and
Wherein the etch rate of electrolytic etching is controlled by differently control doping concentrations of first semiconductor region and the second semiconductor region of different doping type with first semiconductor region, on substrate. [Claim 15]
A method of selectively etching semiconductor region, comprising;
Preparing an n-GaN-based first semiconductor region and n-GaN-based second semiconductor region, on substrate, preparing an etching accelerating layer in the second semiconductor region,
Performing electrolytic etching using the first the semiconductor region as an anode, and an electrolyte solution as a cathode. [Claim 16]
The method according to claim 15, wherein the etching accelerating layer is formed by exposing the second semiconductor layer to oxidation process, impurity treatment, or exposure of the air in the middle of forming the semiconductor region. [Claim 17]
The method according to claim 15, wherein the electrolyte solution include s oxalic acid or KOH. [Claim 18] The method according to claim 14 to 16, wherein an undoped GaN based semiconductor layer is formed between the first semiconductor region and the second semiconductor region. [Claim 19]
The method according to claim 14 to 16, wherein an undoped GaN based semiconductor layer is in contact with the first semiconductor region. [Claim 20]
Method of Separating Semiconductor Structure from Substrate, comprising;
Preparing an semiconductor device part including n-GaN-based first semiconductor region and GaN-based second semiconductor region, on a first substrate,
Attaching the semiconductor device part to a second substrate,
Performing electrolytic etching using the first substrate and the second substrate as an anode, and an electrolyte solution as a cathode,
Wherein the etch rate of electrolytic etching is controlled by differently control doping concentrations of first semiconductor region and the second semiconductor region, thus the second semiconductor region is removed. [Claim 21]
Method of Separating Semiconductor Structure from Substrate, comprising;
Preparing an semiconductor device part including n-GaN-based first semiconductor region and GaN-based second semiconductor region, on a first substrate,
Attaching the semiconductor device part to a second substrate,
Performing electrolytic etching using the first substrate and the second substrate as an anode, and an electrolyte solution as a cathode,
Wherein in electrolytic etching, the second semiconductor region is removed by preparing an etching accelerating layer in the second semiconductor region. [Claim 22]
The method according to claim 21, wherein the etching accelerating layer is formed by exposing the second semiconductor layer to oxidation process, impurity treatment, or exposure of the air in the middle of forming the semiconductor region. [Claim 23]
The method according to claim 20 to 22, wherein the electrolyte solution include s oxalic acid or KOH. [Claim 24]
The method according to claim 20 to 22, wherein an undoped GaN based semiconductor layer is formed between the first semiconductor region and the second semiconductor region. [Claim 25]
The method according to claim 20 to 22, wherein an undoped GaN based semiconductor layer is in contact with the first semiconductor region. [Claim 26]
The method according to claim 20 to 22, wherein the electrolyte solution include s oxalic acid or KOH. [Claim 27]
The method according to claim 20 to 22, wherein the second semiconductor layer is a portion of the semiconductor device part or dummy part. [Claim 28]
The method according to claim 20 to 22, wherein the first substrate is semiconductor substrate and the second substrate is metal substrate.
PCT/KR2008/005913 2007-10-12 2008-10-09 Method of selectively etching semiconductor region, separation method of semiconductor layer and separation method of semiconductor device from substrate WO2009048265A1 (en)

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JP2013518447A (en) * 2010-01-27 2013-05-20 イェイル ユニヴァーシティ Conductivity-based selective etching for GaN devices and applications thereof
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CN104094421A (en) * 2012-02-06 2014-10-08 首尔伟傲世有限公司 Method for separating semiconductor devices using nanoporous structure
US9583353B2 (en) 2012-06-28 2017-02-28 Yale University Lateral electrochemical etching of III-nitride materials for microfabrication
WO2014200827A1 (en) * 2013-06-13 2014-12-18 Yan Ye Methods and apparatuses for delaminating process pieces
US9624597B2 (en) 2013-06-13 2017-04-18 Yan Ye Methods and apparatuses for delaminating process pieces
US11095096B2 (en) 2014-04-16 2021-08-17 Yale University Method for a GaN vertical microcavity surface emitting laser (VCSEL)
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US10554017B2 (en) 2015-05-19 2020-02-04 Yale University Method and device concerning III-nitride edge emitting laser diode of high confinement factor with lattice matched cladding layer

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