WO2009044635A1 - データ処理装置および方法 - Google Patents

データ処理装置および方法 Download PDF

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Publication number
WO2009044635A1
WO2009044635A1 PCT/JP2008/066763 JP2008066763W WO2009044635A1 WO 2009044635 A1 WO2009044635 A1 WO 2009044635A1 JP 2008066763 W JP2008066763 W JP 2008066763W WO 2009044635 A1 WO2009044635 A1 WO 2009044635A1
Authority
WO
WIPO (PCT)
Prior art keywords
data processing
processing device
state transition
object code
hierarchy
Prior art date
Application number
PCT/JP2008/066763
Other languages
English (en)
French (fr)
Inventor
Takeshi Inuo
Kengo Nishino
Nobuki Kajihara
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Priority to US12/681,402 priority Critical patent/US20100223596A1/en
Priority to JP2009536012A priority patent/JP5240200B2/ja
Publication of WO2009044635A1 publication Critical patent/WO2009044635A1/ja

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/45—Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
    • G06F8/456—Parallelism detection

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Executing Special Programs (AREA)
  • Multi Processors (AREA)

Abstract

　事前にデータ登録されている並列演算装置の制約条件に基づいて、入力されたオブジェクトコードの単一階層の状態遷移グラフ構造からループ構造を抽出し、ループ構造を含むような状態遷移を別階層の状態遷移となるように状態遷移グラフを変換し、これを新たなオブジェクトコードとして出力する。
PCT/JP2008/066763 2007-10-03 2008-09-17 データ処理装置および方法 WO2009044635A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/681,402 US20100223596A1 (en) 2007-10-03 2008-09-17 Data processing device and method
JP2009536012A JP5240200B2 (ja) 2007-10-03 2008-09-17 データ処理装置および方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-259889 2007-10-03
JP2007259889 2007-10-03

Publications (1)

Publication Number Publication Date
WO2009044635A1 true WO2009044635A1 (ja) 2009-04-09

Family

ID=40526063

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/066763 WO2009044635A1 (ja) 2007-10-03 2008-09-17 データ処理装置および方法

Country Status (3)

Country Link
US (1) US20100223596A1 (ja)
JP (1) JP5240200B2 (ja)
WO (1) WO2009044635A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010055706A1 (ja) * 2008-11-14 2010-05-20 日本電気株式会社 データ処理装置、データ処理方法及びプログラム

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5131188B2 (ja) * 2006-04-05 2013-01-30 日本電気株式会社 データ処理装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001068993A (ja) * 1999-08-25 2001-03-16 Fuji Xerox Co Ltd 情報処理システム
JP2003099409A (ja) * 2001-09-26 2003-04-04 Nec Corp データ処理装置および方法、コンピュータプログラム、情報記憶媒体、並列演算装置、データ処理システム
JP2006018515A (ja) * 2004-06-30 2006-01-19 Fujitsu Ltd 演算装置及び演算装置の制御方法
WO2007029421A1 (ja) * 2005-09-05 2007-03-15 Nec Corporation 情報処理装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4943912A (en) * 1987-10-13 1990-07-24 Hitachi, Ltd. Parallel processor system having control processor and array control apparatus for selectively activating different processors
US5941983A (en) * 1997-06-24 1999-08-24 Hewlett-Packard Company Out-of-order execution using encoded dependencies between instructions in queues to determine stall values that control issurance of instructions from the queues
JP3327818B2 (ja) * 1997-08-29 2002-09-24 松下電器産業株式会社 プログラム変換装置及び記録媒体
JP3528922B2 (ja) * 2001-08-31 2004-05-24 日本電気株式会社 アレイ型プロセッサ、データ処理システム
US8104030B2 (en) * 2005-12-21 2012-01-24 International Business Machines Corporation Mechanism to restrict parallelization of loops
JP5131188B2 (ja) * 2006-04-05 2013-01-30 日本電気株式会社 データ処理装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001068993A (ja) * 1999-08-25 2001-03-16 Fuji Xerox Co Ltd 情報処理システム
JP2003099409A (ja) * 2001-09-26 2003-04-04 Nec Corp データ処理装置および方法、コンピュータプログラム、情報記憶媒体、並列演算装置、データ処理システム
JP2006018515A (ja) * 2004-06-30 2006-01-19 Fujitsu Ltd 演算装置及び演算装置の制御方法
WO2007029421A1 (ja) * 2005-09-05 2007-03-15 Nec Corporation 情報処理装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010055706A1 (ja) * 2008-11-14 2010-05-20 日本電気株式会社 データ処理装置、データ処理方法及びプログラム

Also Published As

Publication number Publication date
JPWO2009044635A1 (ja) 2011-02-03
US20100223596A1 (en) 2010-09-02
JP5240200B2 (ja) 2013-07-17

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