WO2009040694A1 - Circuit électrique pour empêcher des attaques sur des circuits intégrés - Google Patents

Circuit électrique pour empêcher des attaques sur des circuits intégrés Download PDF

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Publication number
WO2009040694A1
WO2009040694A1 PCT/IB2008/053454 IB2008053454W WO2009040694A1 WO 2009040694 A1 WO2009040694 A1 WO 2009040694A1 IB 2008053454 W IB2008053454 W IB 2008053454W WO 2009040694 A1 WO2009040694 A1 WO 2009040694A1
Authority
WO
WIPO (PCT)
Prior art keywords
capacitor
diode
electric circuit
attacks
integrated circuits
Prior art date
Application number
PCT/IB2008/053454
Other languages
English (en)
Inventor
Sönke OSTERTUN
Joachim Christoph Hans Garbe
Original Assignee
Nxp B.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp B.V. filed Critical Nxp B.V.
Publication of WO2009040694A1 publication Critical patent/WO2009040694A1/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G06K19/07309—Means for preventing undesired reading or writing from or onto record carriers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4078—Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells

Definitions

  • the invention relates to an electric circuit particularly for preventing security relevant integrated circuits from attacks according to the preamble of claim 1.
  • Integrated circuits are known in the prior art especially as integrated circuits of so called smart cards or chip cards as smart card chips containing security relevant or confidential information.
  • Such confidential information may be a secret encryption key or data to identify the user or owner of the smart card or the like.
  • Such integrated circuits are within the scope of illegal attacks from third parties not authorized to get such information legally in order to get possession of such secret information to start illegal actions based on the availability of such secret information.
  • integrated circuits are used for smart cards for identification or to allow access to certain protected facilities or to allow money transactions.
  • integrated circuits are treated by certain illegal actions out of specifications of the integrated circuit like high voltage, high temperature, different clock rate, flash light or something else in order to disturb the functionality of such integrated circuits to get access to the secret information.
  • the basic idea of such treatment is to disturb the usual functionality of the integrated circuit to create an uncontrolled operational status of the circuit to allow uncontrolled access to the secret data.
  • Known smart cards contain sensor devices to detect the above described attacks like temperature sensors, voltage sensors, frequency sensors or light sensors.
  • a sensor detects an unusual status of the integrated circuit which may be triggered by an attack a reset of the integrated circuit will be initiated in order to stop the unusual and uncontrolled status of the integrated circuit. Such a reset starts the boot sequence of the integrated circuit to restart the functionality of the circuit.
  • WO 2007/049181 Al discloses such a circuit allowing to store one bit of information for a certain period of time.
  • a disadvantage of the prior art is, that the bit cannot be cleared intentionally once it is programmed.
  • Object of the invention is to create the possibility of an intentional clearing of a latch like in WO 2007/049181 Al without loosing significant hold time of the information.
  • the objects of the invention are solved using an electric circuit especially for preventing security relevant integrated circuits from attacks containing a memory cell consisting of a diode and a capacitor, wherein the capacitor is connectable firstly with the first diode and secondly with a predetermined potential and a second diode is connectable to mass potential and to the first diode and/or to the capacitor.
  • the diode is realized as a pnp-transistor allowing a clearing of a programmed memory cell.
  • the circuit is manufactured in CMOS-technology.
  • Fig. 1 shows a schematic diagram of an electronic device
  • Fig. 2 shows a schematic diagram of an electronic device
  • Fig. 3 shows a schematic diagram of an inventive device
  • Fig. 4 shows a schematic diagram of an inventive device. DESCRIPTION OF EMBODIMENTS
  • Figure 1 shows a schematic diagram of an electronic device 1 to prevent an integrated circuit 2 from applied attacks.
  • the device 1 contains a capacitor 12 and a diode 10 with low leakage rate.
  • the capacitor 12 can be charged very quickly via the diode 10, where the charging process can be interpreted as programming of the circuit.
  • the capacitor 12 loses its charge very slowly only during a discharging process.
  • a memory cell of the integrated circuit 2 the cell is produced using a standard CMOS process including a p-substrate.
  • a p+/nwell transition zone then produces the diode 10. If the capacitor 12 is connected to ground according to figure 1 this leads to a p-/nwell diode 11 additionally to the p+/nwell diode 10. This additional diode 11 contributes to the discharging of the capacitor 12 of the integrated circuit 2.
  • Reference sign 14 designates the memory port and 13 the program input of the circuit 2.
  • the capacitor 22 is connected to a fixed voltage level of the supply port 25 having a supply voltage level being positive compared to the ground level.
  • the diode 21 no longer contributes to the discharging of the capacitor 22 keeping the holding time of the capacitor 22 on an extended level, that means the holding time is very long compared to the holding time of the embodiment according to figure 1.
  • Reference sign 24 designates the memory port and 23 the program input of the circuit.
  • the two diodes 20, 21 are defining a bipolar pnp-transistor 30 according to figures 3 and 4.
  • This transistor 30 has a low current amplification but can be used as a device for discharging a capacitor 31. Therefore the positive voltage source 34 connected to the capacitor 31 has to be switchable such that the voltage supplied may be changed.
  • FIG. 3 shows a further embodiment of the invention.
  • the programming of the capacitor 31 will be realised by switching the voltage source to the voltage source of the chip of the circuit and the basis 32 of the transistor will be switched to the voltage potential of 0 V. Accordingly the capacitor 31 or the connection port or memory port 33 will be charged negatively via the collector-basis diode of the transistor 30.
  • connection port 33 will follow that change capacitively.
  • the transistor will not supply a current if the capacitor is discharged.
  • the transistor opens and supplies a respective current.
  • the capacitor 31 In order to discharge the capacitor 31 , the capacitor 31 will be disconnected from port 34 and therefore from the voltage supply source and the capacitor will be connected to ground or mass potential instead. In case of a programmed cell the connection port 33 will follow capacitively to a negative potential. As soon as the pnp-transistor opens the connection port 33 will be discharged to mass potential and the capacitor 31 loses its charge. To open the pnp-transistor the basis 32 has to be at negative potential too. Since the capacity of capacitor 31 is small, a small collector current is needed to discharge the capacitor and therefore the potential of the basis 32 have to be only slightly below mass potential. This may be realised via an additionally provided coupling capacitor at the basis 32. The basis 32 will be connected to mass potential and the coupling capacitor will be charged to supply voltage level. After the capacitor has been charged the basis will be disconnected from mass potential and a negative edge of the coupling capacitor will lower the potential of the basis below mass potential and the capacitor 31 will be discharged and memory content will be deleted.
  • the embodiment of figure 3 reveals the advantage that the holding time of the memory cell is almost unchanged compared to the holding time of the memory cell of figure 2. Additionally the holding time of the memory cell has been increased compared to the holding time of the memory cell according to figure 1 since there is preferably only one diode implemented creating a leakage current. In case of a bipolar transistor the needed chip surface is almost the same compared to the needed chip surface in case of a diode since a parasitic bipolar transistor is besides his low current amplification still sufficient.
  • a p-doped substrate 40 is used containing a n-doped area as basis 41.
  • the basis 41 contains a n-doped connection port 42 and a p-doped collector 43 realising the pnp- transistor in the design of figure 3 in CMOS-technology.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention porte sur un circuit électrique, notamment pour empêcher des attaques de circuits intégrés touchant à la sécurité (2), contenant une cellule mémoire constituée d'une diode (10, 11, 20, 21) et d'un condensateur (12, 22, 31), le condensateur (12, 22) étant apte à être connecté tout d'abord à la première diode (10, 20) et ensuite à un potentiel prédéterminé (25) et une seconde diode (11, 21) pouvant être connectée à un potentiel de masse et à la première diode (10, 20) et/ou au condensateur (12, 22).
PCT/IB2008/053454 2007-09-25 2008-08-27 Circuit électrique pour empêcher des attaques sur des circuits intégrés WO2009040694A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP07117156 2007-09-25
EP07117156.5 2007-09-25

Publications (1)

Publication Number Publication Date
WO2009040694A1 true WO2009040694A1 (fr) 2009-04-02

Family

ID=40261029

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2008/053454 WO2009040694A1 (fr) 2007-09-25 2008-08-27 Circuit électrique pour empêcher des attaques sur des circuits intégrés

Country Status (1)

Country Link
WO (1) WO2009040694A1 (fr)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4791611A (en) * 1985-09-11 1988-12-13 University Of Waterloo VLSI dynamic memory
US20030058710A1 (en) * 2001-09-25 2003-03-27 Kurt Hoffmann Semiconductor memory device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4791611A (en) * 1985-09-11 1988-12-13 University Of Waterloo VLSI dynamic memory
US20030058710A1 (en) * 2001-09-25 2003-03-27 Kurt Hoffmann Semiconductor memory device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
TIETZE, SCHENK: "Halbleiter-Schaltungstechnik", 1 January 1974, SPRINGER, BERLIN, XP002512511 *

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