WO2009038961A3 - Nonvolatile memory and method for compensating during programming for perturbing charges of neighboring cells - Google Patents

Nonvolatile memory and method for compensating during programming for perturbing charges of neighboring cells Download PDF

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Publication number
WO2009038961A3
WO2009038961A3 PCT/US2008/075034 US2008075034W WO2009038961A3 WO 2009038961 A3 WO2009038961 A3 WO 2009038961A3 US 2008075034 W US2008075034 W US 2008075034W WO 2009038961 A3 WO2009038961 A3 WO 2009038961A3
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WO
WIPO (PCT)
Prior art keywords
programming
neighboring cells
verify level
memory cell
adjacent
Prior art date
Application number
PCT/US2008/075034
Other languages
French (fr)
Other versions
WO2009038961A2 (en
Inventor
Yan Li
Original Assignee
Sandisk Corp
Yan Li
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sandisk Corp, Yan Li filed Critical Sandisk Corp
Priority to EP08831318.4A priority Critical patent/EP2191475B1/en
Priority to CN200880116492.3A priority patent/CN101861624B/en
Priority to JP2010524922A priority patent/JP2010539630A/en
Publication of WO2009038961A2 publication Critical patent/WO2009038961A2/en
Publication of WO2009038961A3 publication Critical patent/WO2009038961A3/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)

Abstract

Shifts in the apparent charge stored on a charge storing element of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent charge storing elements. To compensate for this coupling, the programming process for a given memory cell can take into account the target programmed state of one or more adjacent memory cell. The amount of programming is verified after each programming pulse and the standard verify level for the programming cell is dependent on the target state. The verify level is further offset lower dependent on the amount of perturbation from neighboring cells, determinable by their target states. The verify level is preferably virtually offset by biasing adjacent word lines instead of actually offsetting the standard verify level. For soft-programming erased cells, neighboring cells on both adjacent word lines are taken into account.
PCT/US2008/075034 2007-09-17 2008-09-02 Nonvolatile memory and method for compensating during programming for perturbing charges of neighboring cells WO2009038961A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP08831318.4A EP2191475B1 (en) 2007-09-17 2008-09-02 Nonvolatile memory and method for compensating during programming for perturbing charges of neighboring cells
CN200880116492.3A CN101861624B (en) 2007-09-17 2008-09-02 Nonvolatile memory and method for compensating during programming for perturbing charges of neighboring cells
JP2010524922A JP2010539630A (en) 2007-09-17 2008-09-02 Nonvolatile memory and method for compensating for perturbed charge of adjacent cells during programming

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/856,625 US7894269B2 (en) 2006-07-20 2007-09-17 Nonvolatile memory and method for compensating during programming for perturbing charges of neighboring cells
US11/856,625 2007-09-17

Publications (2)

Publication Number Publication Date
WO2009038961A2 WO2009038961A2 (en) 2009-03-26
WO2009038961A3 true WO2009038961A3 (en) 2009-06-25

Family

ID=40001371

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/075034 WO2009038961A2 (en) 2007-09-17 2008-09-02 Nonvolatile memory and method for compensating during programming for perturbing charges of neighboring cells

Country Status (7)

Country Link
US (2) US7894269B2 (en)
EP (1) EP2191475B1 (en)
JP (1) JP2010539630A (en)
KR (1) KR20100080896A (en)
CN (1) CN101861624B (en)
TW (1) TW200929230A (en)
WO (1) WO2009038961A2 (en)

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