CN106782656B - Method for improving data retention of flash memory - Google Patents
Method for improving data retention of flash memory Download PDFInfo
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- CN106782656B CN106782656B CN201611111224.5A CN201611111224A CN106782656B CN 106782656 B CN106782656 B CN 106782656B CN 201611111224 A CN201611111224 A CN 201611111224A CN 106782656 B CN106782656 B CN 106782656B
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- flash memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
- G11C16/3409—Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
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Abstract
The invention relates to the technical field of semiconductor manufacturing, in particular to a method for improving data retention of a flash memory, which is characterized in that the read operation and the corresponding programming operation of once improved voltage are added after the flash memory enters a standby state, so that the threshold voltage of a 0 unit with lower threshold voltage is kept above the preset voltage, the threshold voltage of the 0 unit with lower threshold voltage is ensured to be improved in time, and the 0 unit is effectively prevented from being reversed due to charge loss, thereby effectively improving the data retention capability of the flash memory and prolonging the service life of a product; and the added reading operation and the corresponding programming operation are automatically completed after the chip enters a standby mode, so that the use time of a user is not influenced.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a method for improving data retention of a flash memory.
Background
The NOR flash memory cell is a MOS transistor with a Floating Gate (FG) structure, and operates on the principle that the threshold voltage of the memory cell is changed by injecting or releasing charges into or from the FG to achieve the purpose of storing or releasing data. The erase (floating gate) process pulls charge out of the FG by tunneling effect by applying reverse voltage on the control gate (control gate) and Well (Well), and Program (Program) "0" injects charge into the FG by Channel (CHE) effect by applying voltage on the control gate and bit Line (Bite Line, BL).
Currently, the data retention of NOR-type flash memory cells themselves is affected by the following aspects: in a first aspect, increasing P/E (program/erase) cycles (cycles) may cause tunnel oxide trap (tunnel OX trap) charges to be generated, which affect the threshold voltage of a cell (cell) and may be unstable, and may cause the threshold voltage to drift when a trap charge (de-trap) occurs; on the second hand, as time goes on, the charge in the FG leaks (leak) through the tunnel oxide (tunnel OX), ONO, gate sidewall spacer (poly sidewall) and so on, causing the threshold voltage to shift and finally inverting the "0" cell. In a third aspect, tunneling oxide layer may cause TDDB (time dependent dielectric breakdown) or dielectric degradation under voltage and electric field, resulting in cell (Bit) error.
In addition to the data retention of the memory Cell itself, Flash is used as a storage array, and the memory Cell is constantly affected by external conditions such as word line interference (WL disturb), bit line interference (BL disturb), Well disturb (Well disturb) and the like in the use process.
The charge in the floating gate of the 0 memory cell in FLASH is reduced due to the increase of the memory cells in FLASH along with the time, and the threshold voltage is gradually reduced. For NOR flash memory, checking methods such as ECC are rarely adopted, so that the reliability of the product is reduced; as shown in fig. 1 (where the ordinate represents the value of bits and the abscissa represents the threshold voltage), 1 is a 1 cell whose threshold voltage is lower than the normal read voltage, 3 is a 0 cell whose threshold voltage is higher than the normal read voltage, and 2 is the normal read voltage, once the threshold voltage of 0bit is lower than the normal read voltage 2, 0 of the bit will be wrongly read as 1, and a is a 0 cell whose threshold voltage is lower than the normal read voltage.
Therefore, how to find an effective method to strengthen and manage the memory cell of 0 in the memory array to ensure the integrity of the user data becomes a direction of research for those skilled in the art.
Disclosure of Invention
Aiming at the existing problems, the invention discloses a method for improving the data retention of a flash memory, which comprises the following steps:
reading data in the flash memory by adopting a normal reading voltage after the flash memory enters a standby (standby) mode;
judging whether a 0 unit exists in the flash memory, if not, then exiting;
reading data in the flash memory by adopting a preset voltage, wherein the preset voltage is greater than the normal reading voltage;
judging whether a 0 unit with the threshold voltage smaller than the preset voltage exists in the flash memory or not, and if not, then exiting;
and programming the 0 unit of which the threshold voltage is less than the preset voltage so that the threshold voltage of the 0 unit is greater than the preset voltage.
In the method for improving data retention of the flash memory, the 0 unit is a memory unit of which the threshold voltage is greater than the read voltage in the flash memory.
In the method for improving data retention of the flash memory, the preset voltage is smaller than the program verification voltage.
In the method for improving data retention of the flash memory, the value range of the programming verification voltage is 7-9 v.
In the method for improving data retention of the flash memory, the value range of the normal reading voltage is 5-6 v.
In the method for improving data retention of the flash memory, the value range of the preset voltage is 6-7 v.
In the method for improving data retention of the flash memory, the flash memory is a NOR flash memory.
The method for improving data retention of a flash memory, wherein the NOR-type flash memory comprises:
a substrate;
a tunneling oxide layer disposed on the substrate;
the floating gate is arranged on the tunneling oxide layer;
and the barrier layer is arranged on the floating gate.
In the method for improving data retention of the flash memory, the blocking layer is an ONO blocking layer.
In the method for improving data retention of the flash memory, the NOR-type flash memory further includes a sidewall disposed on the sidewall of the floating gate.
The invention has the following advantages or beneficial effects:
the invention discloses a method for improving data retention of a flash memory, which is characterized in that a reading operation and a corresponding programming operation for increasing voltage are added once after the flash memory enters a standby state, so that the threshold voltage of a 0 unit with lower threshold voltage is kept above a preset voltage, the threshold voltage of the 0 unit with lower threshold voltage is ensured to be improved in time, and the 0 unit is effectively prevented from being reversed due to charge loss, so that the data retention capability of the flash memory is effectively improved, and the service life of a product is prolonged; and the added reading operation and the corresponding programming operation are automatically completed after the chip enters a standby mode, so that the use time of a user is not influenced.
Drawings
The invention and its features, aspects and advantages will become more apparent from reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Like reference symbols in the various drawings indicate like elements. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.
FIG. 1 is a diagram illustrating threshold voltage distributions of memory cells according to the background of the invention;
FIG. 2 is a flow chart of a method for improving data retention of a NOR flash memory according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating an embodiment of a method for improving data retention of a NOR flash memory according to the present invention;
FIG. 4 is a diagram illustrating threshold voltage distributions of memory cells according to an embodiment of the present invention.
Detailed Description
The invention will be further described with reference to the following drawings and specific examples, which are not intended to limit the invention thereto.
As shown in fig. 2, the present embodiment relates to a method for improving data retention of a flash memory, preferably, the flash memory is a NOR-type flash memory; specifically, the method comprises the following steps:
in step S1, after the flash memory enters the standby mode, the data in the flash memory is read using the normal read voltage.
In a preferred embodiment of the present invention, the normal read voltage ranges from 5v to 6v (e.g., 5v, 5.3v, 5.5v, or 6v, etc.), and of course, the normal read voltage is different for different flash memories, and therefore, the normal read voltage can be set by a person skilled in the art according to specific situations.
Step S2, determining whether there is 0 cell in the flash memory, if there is no 0 cell in the flash memory, then exiting, if there is 0 cell in the flash memory, then go to step S3.
In a preferred embodiment of the present invention, the 0 cell is a memory cell in the flash memory, wherein the threshold voltage of the memory cell is greater than the normal read voltage.
Step S3, reading data in the flash memory with a preset voltage, wherein the preset voltage is greater than the normal reading voltage.
In a preferred embodiment of the present invention, the predetermined voltage is smaller than a program verify (program verify) voltage.
In a preferred embodiment of the present invention, the preset voltage ranges from 6 to 7v (e.g., 6v, 6.3v, 6.5v, or 7v), and the like, and can be specifically set by a person skilled in the art according to the normal read voltage, the program verify voltage, and the like.
In a preferred embodiment of the present invention, the value range of the program verification voltage is 7-9 v (7v, 7.3v, 8v or 9 v).
Step S4, determining whether there is a 0 cell with a threshold voltage less than a preset voltage in the flash memory, and if there is no 0 cell with a threshold voltage less than a preset voltage in the flash memory, then exiting; if there is a 0 cell with a threshold voltage less than the predetermined voltage in the flash memory, step S5 is performed.
In step S5, a 0 cell having a threshold voltage less than a predetermined voltage is programmed (typically, a soft programming operation) such that the threshold voltage of the 0 cell is greater than the predetermined voltage.
In a preferred embodiment of the present invention, the NOR type flash memory includes:
a substrate;
a tunneling oxide layer disposed on the substrate;
the floating gate is arranged on the tunneling oxide layer;
and the barrier layer is arranged on the floating gate.
In a preferred embodiment of the present invention, the blocking layer is an ONO blocking layer.
In a preferred embodiment of the present invention, the NOR flash memory further includes a sidewall disposed on a sidewall of the floating gate.
The invention is further described below with reference to a specific implementation flowchart of a method for improving data retention of a flash memory:
as shown in fig. 3, the flash memory is first brought into a standby state; reading data in a storage array in the flash memory by adopting normal reading voltage; then judging whether a 0 unit (namely a storage unit with the threshold voltage larger than the normal reading voltage) exists in the flash memory, if the 0 unit does not exist in the flash memory, finishing the reading operation, if the 0 unit exists in the flash memory, reading data in a storage array in the flash memory by adopting a preset voltage which is larger than the normal reading voltage and smaller than the programming verification voltage, then continuously judging whether the 0 unit with the threshold voltage smaller than the preset voltage exists in the flash memory, and if the 0 unit with the threshold voltage smaller than the preset voltage does not exist in the flash memory, finishing the reading operation; if the flash memory has a 0 unit less than the preset voltage, performing programming operation on the 0 unit less than the preset voltage to enable the threshold voltage of the 0 unit to be greater than the preset voltage; as shown in fig. 4, wherein the abscissa represents the threshold voltage, the ordinate represents the bits value, 11 represents the 1 cell in which the threshold voltage is greater than the normal read voltage, 12 represents the normal read voltage, 13 represents the preset voltage, 14 represents the 0 cell, and B represents the 0 cell in which the threshold voltage is less than the preset voltage.
In summary, the method for improving data retention of the flash memory disclosed by the invention is characterized in that a preset voltage is set to perform read operation on the flash memory, the preset voltage is higher than a normal read voltage and lower than a programming verification voltage, and soft programming operation is performed on a 0 unit with a lower threshold voltage, so that the threshold voltage is kept above the preset voltage, thereby effectively preventing the 0 unit from being reversed due to charge loss, further effectively improving the data retention capability of the NOR flash memory and prolonging the service life of a product.
Those skilled in the art will appreciate that variations may be implemented by those skilled in the art in combination with the prior art and the above-described embodiments, and will not be described herein in detail. Such variations do not affect the essence of the present invention and are not described herein.
The above description is of the preferred embodiment of the invention. It is to be understood that the invention is not limited to the particular embodiments described above, in that devices and structures not described in detail are understood to be implemented in a manner common in the art; those skilled in the art can make many possible variations and modifications to the disclosed embodiments, or modify equivalent embodiments to equivalent variations, without departing from the spirit of the invention, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (9)
1. A method for improving data retention of a flash memory is characterized by comprising the following steps:
after the flash memory enters a standby mode, reading data in the flash memory by adopting a normal reading voltage;
judging whether a 0 unit exists in the flash memory, if not, then exiting;
reading data in the flash memory by adopting a preset voltage, wherein the preset voltage is greater than the normal reading voltage and less than a programming verification voltage;
judging whether a 0 unit with the threshold voltage smaller than the preset voltage exists in the flash memory or not, and if not, then exiting;
and programming the 0 unit of which the threshold voltage is less than the preset voltage so that the threshold voltage of the 0 unit is greater than the preset voltage.
2. The method of improving data retention of a flash memory of claim 1, wherein the 0 cell is a memory cell in the flash memory having a threshold voltage greater than the normal read voltage.
3. The method for improving data retention of a flash memory according to claim 1, wherein the program verify voltage has a value ranging from 7v to 9 v.
4. The method for improving data retention of a flash memory according to claim 1, wherein the normal read voltage has a value in a range of 5 to 6 v.
5. The method for improving data retention of a flash memory according to claim 1, wherein the preset voltage ranges from 6v to 7 v.
6. The method of improving data retention of a flash memory of claim 1, wherein the flash memory is a NOR type flash memory.
7. The method of improving data retention of a flash memory of claim 6, wherein the NOR-type flash memory comprises:
a substrate;
a tunneling oxide layer disposed on the substrate;
the floating gate is arranged on the tunneling oxide layer;
and the barrier layer is arranged on the floating gate.
8. The method of claim 7, wherein the barrier layer is an ONO barrier layer.
9. The method of improving data retention of a flash memory of claim 7, wherein the NOR flash memory further comprises spacers disposed on sidewalls of the floating gate.
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| CN201611111224.5A CN106782656B (en) | 2016-12-02 | 2016-12-02 | Method for improving data retention of flash memory |
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| CN201611111224.5A CN106782656B (en) | 2016-12-02 | 2016-12-02 | Method for improving data retention of flash memory |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101861624A (en) * | 2007-09-17 | 2010-10-13 | 桑迪士克公司 | Nonvolatile memory and method for compensating during programming for perturbing charges of neighboring cells |
| CN103904037A (en) * | 2014-04-04 | 2014-07-02 | 武汉新芯集成电路制造有限公司 | Manufacturing method of NOR flash memory |
| CN104425387A (en) * | 2013-08-30 | 2015-03-18 | 北京兆易创新科技股份有限公司 | Method for making NOR flash memory and NOR flash memory |
| CN105659328A (en) * | 2013-10-15 | 2016-06-08 | 桑迪士克技术有限公司 | Double verify method in multi-pass programming to suppress read noise |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9343172B2 (en) * | 2013-08-13 | 2016-05-17 | Freescale Semiconductor, Inc. | Extended protection for embedded erase of non-volatile memory cells |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101861624A (en) * | 2007-09-17 | 2010-10-13 | 桑迪士克公司 | Nonvolatile memory and method for compensating during programming for perturbing charges of neighboring cells |
| CN104425387A (en) * | 2013-08-30 | 2015-03-18 | 北京兆易创新科技股份有限公司 | Method for making NOR flash memory and NOR flash memory |
| CN105659328A (en) * | 2013-10-15 | 2016-06-08 | 桑迪士克技术有限公司 | Double verify method in multi-pass programming to suppress read noise |
| CN103904037A (en) * | 2014-04-04 | 2014-07-02 | 武汉新芯集成电路制造有限公司 | Manufacturing method of NOR flash memory |
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