CN111798906A - Method, system, storage medium and terminal for improving data retention capacity of non-flash memory - Google Patents
Method, system, storage medium and terminal for improving data retention capacity of non-flash memory Download PDFInfo
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- CN111798906A CN111798906A CN202010604177.8A CN202010604177A CN111798906A CN 111798906 A CN111798906 A CN 111798906A CN 202010604177 A CN202010604177 A CN 202010604177A CN 111798906 A CN111798906 A CN 111798906A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
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Abstract
The invention discloses a method, a system, a storage medium and a terminal for improving the data retention capacity of a non-flash memory, wherein the Vt value of data 0 is detected and repaired at regular time, and when the Vt value of the data 0 is detected to be lower than a set value, program operation is carried out on the data, the Vt value is improved, and the normal Vt value is restored; the detection and repair operation is carried out on all nonvolatile memory units in the chip when the chip is in an idle state, when a timer in the chip reaches a set time, the chip automatically detects whether the chip is in a busy state, and when the chip is confirmed to be in the idle state, the Vt value detection and repair function of data 0 is started; the upper computer can also actively start the repair operation of the flash data 0.
Description
Technical Field
The invention relates to the field of data retention time of a nor flash memory, in particular to a method, a system, a storage medium and a terminal for improving the data retention capacity of a non-flash memory.
Background
One main performance index of a Nor Flash (non-volatile Flash) Flash memory is data retention time, the data retention time of the currently adopted double-layer poly floating gate process at normal temperature is 10 years, and the requirement of the Nor Flash (non-volatile Flash) Flash memory in high-temperature environment application with higher requirement on the data retention time is difficult to meet; the general improvement method is to improve the process manufacturing flow, improve the quality of the oxide layer and other improvement measures so as to improve the data retention time, but the space for improving the method is limited, and various nor flash manufacturers do not realize great breakthrough at present.
Therefore, the prior art still needs to be improved and developed.
Disclosure of Invention
The invention aims to provide a method, a system, a storage medium and a terminal for improving the data retention capacity of a non-flash memory.
The technical scheme of the invention is as follows: a method for improving data retention capability of a non-flash memory specifically comprises the following steps:
s1: judging whether the threshold voltage of the data 0 of the storage unit in the chip is lower than the preset threshold voltage value, if so, skipping to S2, otherwise, skipping to S3;
s2: repairing the data 0 of the storage unit, improving the threshold voltage of the data 0, and recovering the normal value;
s3: data 0 of the memory cell is not repaired.
In the technical scheme, by detecting and repairing the Vt value of the data 0, when the Vt value of the data 0 is lower than a set value, program operation is carried out on the Vt value, the Vt value is improved, the normal Vt value is restored, and the data retention time of the nor flash is prolonged.
The method for improving the data retention capability of the non-flash memory further comprises the following steps after S3:
s4: judging whether the data 0 of all the storage units in the chip are repaired, if so, jumping to S5, otherwise, jumping to S1;
s5: the repair of the in-chip memory cell data 0 is completed and the flow proceeds to S1.
In the technical scheme, omission is prevented by detecting and repairing the data 0 of all the storage units in the chip.
In the method for improving the data retention capability of the non-flash memory, the repairing of the data 0 of the memory cell increases the threshold voltage of the data 0 by performing a Program operation on the data 0 of the memory cell, and restores the normal value again.
The method for improving the data retention capacity of the non-flash memory comprises the step of judging whether the preset threshold voltage value is larger than or equal to the voltage applied to the control gate of the memory cell when the read operation is executed.
The method for improving the data retention capability of the non-flash memory further comprises the following steps before S1:
s06: judging whether the chip is in an idle state, if so, jumping to S1, otherwise, jumping to S07;
s07: the current state of the chip is not changed and the process goes to S06.
In the technical scheme, the data 0 of the storage unit is detected and repaired when the chip is in an idle state, so that the operating pressure of the chip is prevented from increasing.
The method for improving the data retention capability of the non-flash memory further comprises the following steps before S06:
s01: normally timing;
s02: judging whether the timing time reaches the preset time, if so, jumping to S06, otherwise, jumping to S03;
s03: the current state of the chip is not changed and the process goes to S01.
The method for improving the data retention capability of the non-flash memory further comprises the following steps before S06:
s04: judging whether a starting instruction of the upper computer is received, if so, jumping to S06, and if not, jumping to S05;
s05: the current state of the chip is not changed and the process goes to S04.
In this technical solution, the detection and repair of the data 0 of the storage unit may be started by setting a fixed start time or by an upper computer instruction according to actual needs, or other starting means that may occur to those skilled in the art are all within the protection scope of this technical solution.
A system for using the method for improving data retention capability of the non-flash memory as described in any one of the above, comprising:
a threshold voltage judging module (A1) for judging whether the threshold voltage of the memory cell data 0 in the chip is lower than the threshold voltage preset value;
and a repair module (A2) for repairing data 0 in the memory cell and restoring the threshold voltage of data 0 to the normal value.
A storage medium having stored therein a computer program which, when run on a computer, causes the computer to perform the method of any one of the above.
A terminal comprising a processor and a memory, the memory having stored therein a computer program, the processor being adapted to perform the method of any preceding claim by invoking the computer program stored in the memory.
The invention has the beneficial effects that: the invention provides a method, a system, a storage medium and a terminal for improving the data retention capacity of a non-flash memory, wherein the Vt value of data 0 is detected and repaired at regular time, and when the Vt value of the data 0 is detected to be lower than a set value, program operation is carried out on the data to improve the Vt value of the data so as to restore the normal Vt value of the data; the detection and repair operation is carried out on all nonvolatile memory units in the chip when the chip is in an idle state, when a timer in the chip reaches a set time, the chip automatically detects whether the chip is in a busy state, and when the chip is confirmed to be in the idle state, the Vt value detection and repair function of data 0 is started; the upper computer can also actively start the repair operation of the flash data 0.
Drawings
FIG. 1 is a flow chart of the steps of the method for improving the data retention capability of a non-flash memory according to the present invention.
FIG. 2 is a graph of Vt distributions after normal program operation and erase operation of a memory cell of the present invention.
FIG. 3 is a diagram illustrating the memory cell data 0 after Vt reduction in accordance with the present invention.
FIG. 4 is a graph showing the set voltages for Vt value of data 0 of the memory cell of the present invention being lowered to less than Vt2 and greater than Vt 1.
FIG. 5 is a graph showing the Vt values of the memory cell of the present invention after data 0 repair.
Fig. 6 is a block schematic diagram of the system of the present invention.
Fig. 7 is a structural view of a terminal in the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
In the Nor flash data retention, data 0 and 1 of the Nor flash are represented by different Vt (threshold voltage) values of the floating gate memory cell, a high Vt value represents data 0, a low Vt value represents data 1, and different data can be stored by changing the Vt value of the memory cell. Erase operations may lower the Vt of the cell, and Program operations may raise the Vt of the cell. The Vt of data 1 is generally set near the Vt after the ultraviolet light irradiation treatment, which remains substantially constant with time. Data 0 has a relatively high Vt after Program operation, but slowly decreases with time, which can cause data read errors when its Vt decreases sufficiently. The period of time from the Program operation to the data loss of data 0 is called data retention time, and the data retention time is mainly related to temperature, and the data retention time is shorter as the temperature is higher.
As shown in fig. 1, a method for improving data retention capability of a non-flash memory specifically includes the following steps:
s1: judging whether the threshold voltage of the data 0 of the storage unit in the chip is lower than the preset threshold voltage value, if so, skipping to S2, otherwise, skipping to S3;
s2: repairing the data 0 of the storage unit, improving the threshold voltage of the data 0, and recovering the normal value;
s3: data 0 of the memory cell is not repaired.
In certain embodiments, the following steps are further included after S3:
s4: judging whether the data 0 of all the storage units in the chip are repaired, if so, jumping to S5, otherwise, jumping to S1;
s5: the repair of the in-chip memory cell data 0 is completed and the flow proceeds to S1.
In some embodiments, the repairing of data 0 of the memory cell is performed by performing a Program operation on data 0 of the memory cell, so that the threshold voltage of data 0 is increased, and the normal value is restored.
In some embodiments, the threshold voltage preset value may be set according to actual needs. In this embodiment, the threshold voltage preset values are Vt1, Vt2, and Vt1< Vt2, where Vt1 is the voltage applied to the control gate of the memory cell during read operation. FIG. 2 is a graph of Vt distributions for a cell after a normal program operation in which electrons in the cell enter a floating gate, causing the Vt value to increase, and after an erase operation in which electrons in the cell move out of the floating gate, causing the Vt value to decrease; the middle dotted line 1 (i.e. Vt 1) is the voltage applied to the control gate of the memory cell during read operation, and the Vt value of the cell after erase operation is smaller than the voltage value defined by the dotted line 1, is in a conducting state, and is defined as bit 1; the Vt value of the cell after program operation is greater than the voltage value defined by the dotted line 1, is in the closed state and is defined as bit 0; since the electrons stored in the floating gate will leak slowly with time, the charges will become smaller gradually, and the Vt will also decrease slowly, as shown in fig. 3, when the Vt of the cell is lower than the dashed line 1, bit0 will be changed to bit1, and the data stored in the flash cell will be lost, so it is necessary to repair the Vt of bit0 before it decreases to the dashed line 1, and then to restore the Vt to normal again. As shown in FIG. 4, when the Vt value of bit0 decreases to a value less than the dashed line 2 (i.e., Vt 2) and greater than the voltage set by dashed line 1, a program operation is initiated to move the Vt value of bit0 to about its initial value again, and the final repair result is shown in FIG. 5. the above-described method of bit0 can recover the Vt value of bit0 that decreases over time.
In some embodiments, in order to avoid increasing the operating pressure of the chip, the detection and the refresh of the threshold voltage of the data 0 in the memory cell in the chip may be started only when the chip is in an idle state, and the detection and the refresh of the threshold voltage of the data 0 in the memory cell in the chip may not be started when the chip is in an operating state, which includes the following specific processes: before S1, the method further includes the following steps:
s06: judging whether the chip is in an idle state, if so, jumping to S1, otherwise, jumping to S07;
s07: the current state of the chip is not changed and the process goes to S06.
In some embodiments, the detection and repair operation of the threshold voltage of the memory cell data 0 in the chip can be started by different means according to actual needs:
(1) starting by setting a preset starting time, the method further comprises the following steps before S06:
s01: normally timing;
s02: judging whether the timing time reaches the preset time, if so, jumping to S06, otherwise, jumping to S03;
s03: the current state of the chip is not changed and the process goes to S01.
(2) The method is started by a host computer instruction, and before the step S06, the method further comprises the following steps:
s04: judging whether a starting instruction of the upper computer is received, if so, jumping to S06, and if not, jumping to S05;
s05: the current state of the chip is not changed and the process goes to S04.
In the technical scheme, the starting scheme of (1) or the starting scheme of (2) can be used independently, or the starting schemes of (1) and (2) can be used together, that is, the detection and repair operation of the threshold voltage of the data 0 of the memory cell in the chip can be started as long as any condition of (1), (2), (1) and (2) is met.
In order to avoid the influence of the last counted time on the next counted time, the following steps are further included before S01:
s00-1: the chip completes power-on reset;
s00-2: the count time is cleared and the flow goes to S01.
As shown in fig. 6, a system adopting the method for improving data retention capability of a non-flash memory as described above includes:
a threshold voltage judging module A1 for judging whether the threshold voltage of the memory cell data 0 in the chip is lower than the preset threshold voltage value;
and a repair module A2 for repairing data 0 of the memory cell to restore the normal threshold voltage of data 0.
In some embodiments, the system further includes a storage unit determining module a3 for determining whether the data 0 of all storage units in the chip has been repaired.
In some embodiments, the system further includes a chip determining module A4 for determining whether the chip is in an idle state.
In certain embodiments, the system further comprises:
a timer a5 for normal timing;
and a timing judgment module A6 for judging whether the timing time reaches the preset time.
In some embodiments, the system further includes an instruction receiving module a7 that receives a start instruction of the upper computer.
The present invention also provides a storage medium having a computer program stored therein, which when run on a computer causes the computer to perform the method of any of the above to implement the following functions: and judging whether the threshold voltage of the data 0 of the storage unit in the chip is lower than a preset threshold voltage value or not, if so, repairing the data 0 of the storage unit to improve the threshold voltage of the data 0 and restore the normal value, otherwise, not repairing the data 0 of the storage unit.
Referring to fig. 7, an embodiment of the present invention further provides a terminal, as shown in fig. 7, a terminal B300 includes a processor B301 and a memory B302. The processor B301 is electrically connected to the memory B302. The processor B301 is a control center of the terminal B300, connects various parts of the entire terminal using various interfaces and lines, and performs various functions of the terminal and processes data by running or calling a computer program stored in the memory B302 and calling data stored in the memory B302, thereby performing overall monitoring of the terminal B300.
In this embodiment, the processor B301 in the terminal B300 loads instructions corresponding to one or more computer program processes into the memory B302 according to the following steps, and the processor B301 runs the computer program stored in the memory B302, so as to implement various functions: and judging whether the threshold voltage of the data 0 of the storage unit in the chip is lower than a preset threshold voltage value or not, if so, repairing the data 0 of the storage unit to improve the threshold voltage of the data 0 and restore the normal value, otherwise, not repairing the data 0 of the storage unit.
Memory B302 may be used to store computer programs and data. The memory B302 stores a computer program containing instructions executable in the processor. The computer program may constitute various functional modules. The processor B301 executes various functional applications and data processing by calling a computer program stored in the memory B302.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A method for improving data retention capability of a non-flash memory is characterized by comprising the following steps:
s1: judging whether the threshold voltage of the data 0 of the storage unit in the chip is lower than the preset threshold voltage value, if so, skipping to S2, otherwise, skipping to S3;
s2: repairing the data 0 of the storage unit, improving the threshold voltage of the data 0, and recovering the normal value;
s3: data 0 of the memory cell is not repaired.
2. The method of claim 1, further comprising the following steps after S3:
s4: judging whether the data 0 of all the storage units in the chip are repaired, if so, jumping to S5, otherwise, jumping to S1;
s5: the repair of the in-chip memory cell data 0 is completed and the flow proceeds to S1.
3. The method of claim 1, wherein the repairing of data 0 of the memory cell is performed by performing a Program operation on data 0 of the memory cell to increase the threshold voltage of data 0 and restore the normal value.
4. The method of claim 1, wherein the threshold voltage preset value is equal to or greater than a voltage applied to a control gate of the memory cell during a read operation.
5. The method of claim 1, further comprising the following steps before S1:
s06: judging whether the chip is in an idle state, if so, jumping to S1, otherwise, jumping to S07;
s07: the current state of the chip is not changed and the process goes to S06.
6. The method of claim 5, further comprising the following steps before S06:
s01: normally timing;
s02: judging whether the timing time reaches the preset time, if so, jumping to S06, otherwise, jumping to S03;
s03: the current state of the chip is not changed and the process goes to S01.
7. The method of claim 5 or 6, further comprising the following steps before S06:
s04: judging whether a starting instruction of the upper computer is received, if so, jumping to S06, and if not, jumping to S05;
s05: the current state of the chip is not changed and the process goes to S04.
8. A system for using the method of any of claims 1-7 to improve data retention capability of a non-flash memory, comprising:
a threshold voltage judging module (A1) for judging whether the threshold voltage of the memory cell data 0 in the chip is lower than the threshold voltage preset value;
and a repair module (A2) for repairing data 0 in the memory cell and restoring the threshold voltage of data 0 to the normal value.
9. A storage medium having stored thereon a computer program which, when run on a computer, causes the computer to perform the method of any one of claims 1 to 7.
10. A terminal, characterized in that it comprises a processor (B301) and a memory (B302), said memory (B302) having stored therein a computer program, said processor (B301) being adapted to perform the method of any of claims 1 to 7 by calling said computer program stored in said memory (B302).
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010604177.8A CN111798906A (en) | 2020-06-29 | 2020-06-29 | Method, system, storage medium and terminal for improving data retention capacity of non-flash memory |
| PCT/CN2020/128142 WO2022000929A1 (en) | 2020-06-29 | 2020-11-11 | Method for improving data retention capability of nor flash memory, system, storage medium, and terminal |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010604177.8A CN111798906A (en) | 2020-06-29 | 2020-06-29 | Method, system, storage medium and terminal for improving data retention capacity of non-flash memory |
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| CN111798906A true CN111798906A (en) | 2020-10-20 |
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| WO (1) | WO2022000929A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2022000929A1 (en) * | 2020-06-29 | 2022-01-06 | 芯天下技术股份有限公司 | Method for improving data retention capability of nor flash memory, system, storage medium, and terminal |
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| CN114879911A (en) * | 2022-05-19 | 2022-08-09 | 珠海趣印科技有限公司 | Data storage method and device and electronic equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111798906A (en) * | 2020-06-29 | 2020-10-20 | 深圳市芯天下技术有限公司 | Method, system, storage medium and terminal for improving data retention capacity of non-flash memory |
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- 2020-11-11 WO PCT/CN2020/128142 patent/WO2022000929A1/en active Application Filing
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