CN112346556A - Method, device, computer equipment and medium for improving low power consumption efficiency of chip - Google Patents
Method, device, computer equipment and medium for improving low power consumption efficiency of chip Download PDFInfo
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- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/325—Power saving in peripheral device
- G06F1/3268—Power saving in hard disk drive
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0625—Power saving in storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
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Abstract
The invention discloses a method, a device, computer equipment and a medium for improving the low power consumption efficiency of a chip, wherein the method comprises the following steps: the firmware runs, and the solid state disk works; judging whether a low power consumption command is received or not; if a low power consumption command is received, storing the data in the DDR, and entering a first type low power consumption state; when the DDR is in the first type low power consumption state, DDR self-refreshing is reserved; judging whether the time in the first type low power consumption state exceeds a preset time or not; and if the preset time is exceeded, controlling the DDR to be powered off, and entering a second type low power consumption state. Although the DDR self-refresh has certain power consumption increase in the whole process, firmware is loaded from the DDR and data is recovered, so that the exiting process is greatly shortened, the power consumption value is saved, and the efficiency is improved.
Description
Technical Field
The invention relates to a solid state disk, in particular to a method, a device, computer equipment and a medium for improving the low power consumption efficiency of a chip.
Background
Low power consumption is a necessary function of a chip and is also very important in a solid state disk. The traditional low power consumption flow is as follows: when the SSD (solid state disk) enters a low power consumption state, a command is quickly sent to enable the chip to exit the low power consumption state. In the fast forward and backward process, the loading of the firmware and the recovery of the data take a lot of time, and during the recovery, the solid state disk is in a high-speed running state, the power consumption is high, and a lot of power consumption is consumed.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a method, a device, computer equipment and a medium for improving the low power consumption efficiency of a chip.
In order to achieve the purpose, the invention adopts the following technical scheme:
in a first aspect, a method for improving low power consumption efficiency of a chip, the method comprising:
the firmware runs, and the solid state disk works;
judging whether a low power consumption command is received or not;
if a low power consumption command is received, storing the data in the DDR, and entering a first type low power consumption state; when the DDR is in the first type low power consumption state, DDR self-refreshing is reserved;
judging whether the time in the first type low power consumption state exceeds a preset time or not;
and if the preset time is exceeded, controlling the DDR to be powered off, and entering a second type low power consumption state.
The further technical scheme is as follows: the second type of low power consumption state consumes less power than the first type of low power consumption state.
The further technical scheme is as follows: after the step of judging whether the time in the first type low power consumption state exceeds the preset time, the method further comprises the following steps:
if the preset time is not exceeded, judging whether a command for exiting the first type low power consumption state is received;
and if a command of exiting the first type low power consumption state is received, the DDR exits the self-refresh state and recovers a firmware program from the DDR.
The further technical scheme is as follows: after the step of controlling the DDR to power down and entering the second type low power consumption state, the method further comprises the following steps:
judging whether a command for exiting the second type low power consumption state is received;
if a command to exit the second type low power state is received, the firmware program is reloaded from the NAND or NOR.
In a second aspect, an apparatus for improving low power consumption efficiency of a chip includes a starting unit, a first determining unit, a first executing unit, a second determining unit, and a second executing unit;
the starting unit is used for running firmware and working the solid state disk;
the first judging unit is used for judging whether a low-power-consumption command is received or not;
the first execution unit is used for saving the data in the DDR and entering a first type low power consumption state; when the DDR is in the first type low power consumption state, DDR self-refreshing is reserved;
the second judging unit is used for judging whether the time in the first type low power consumption state exceeds a preset time or not;
and the second execution unit is used for controlling the DDR to be powered off and entering a second type low power consumption state.
The further technical scheme is as follows: the device also comprises a third judging unit and a first restoring unit;
the third judging unit is used for judging whether a command for exiting the first type low power consumption state is received or not;
and the first recovery unit is used for the DDR to exit from a self-refresh state and recover a firmware program from the DDR.
The further technical scheme is as follows: the device also comprises a fourth judging unit and a second restoring unit;
the fourth judging unit is used for judging whether a command for exiting the second type low power consumption state is received;
and the second recovery unit is used for reloading the firmware program from the NAND or the NOR.
In a third aspect, a computer device comprises a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor executes the computer program to implement the method steps for improving the low power consumption efficiency of a chip as described above.
In a fourth aspect, a storage medium stores a computer program comprising program instructions that, when executed by a processor, cause the processor to perform the method steps of improving the low power consumption efficiency of a chip as described above.
Compared with the prior art, the invention has the beneficial effects that: the method comprises the steps that after a low-power-consumption command is received by a solid state disk, the solid state disk enters a first type low-power-consumption state, data are stored in a DDR, DDR self-refreshing is reserved, if the command for quitting the first type low-power-consumption state is received within preset time, the DDR quits the self-refreshing state, a firmware program is recovered from the DDR, if no command exceeds the preset time, the DDR is controlled to be powered off, and then the solid state disk enters a second type low-power-consumption state. Although the DDR self-refresh has certain power consumption increase in the whole process, firmware is loaded from the DDR and data is recovered, so that the exiting process is greatly shortened, the power consumption value is saved, and the efficiency is improved.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented according to the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more apparent, the following detailed description will be given of preferred embodiments.
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FIG. 1 is a flowchart of an embodiment of a method for improving low power efficiency of a chip according to the present invention;
FIG. 2 is a schematic block diagram of an embodiment of an apparatus for improving low power efficiency of a chip according to the present invention;
FIG. 3 is a schematic block diagram of a computer device of the present invention.
Detailed Description
In order to more fully understand the technical content of the present invention, the technical solution of the present invention will be further described and illustrated with reference to the following specific embodiments, but not limited thereto.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
The invention provides a method for improving the low power consumption efficiency of a chip, which is mainly applied to a solid state disk and can effectively save the power consumption value of the solid state disk. Before describing the present invention, a conventional low power flow will be described.
The traditional low-power-consumption flow is that when a solid state disk receives a command for entering low power consumption, the solid state disk directly enters the low-power-consumption flow, stores data (data such as a mapping table of an FTL Flash Translation Layer), then powers down a chip, maintains a low-power-consumption state, exits from the low-power-consumption state after receiving the command, loads firmware from an NAND or an NOR again, runs the firmware, recovers the stored data, and finally performs normal read-write operation. However, in most cases, in this process, after the host puts the SSD (solid state disk) into the low power consumption state, the host sends the command quickly to let the chip exit from the low power consumption state, so that during the quick forward/backward process, the firmware is loaded, and a large amount of time is spent on data recovery. For the solid state disk, most of the data to be restored exists in the DDR, and the DDR can enter a self-refresh low power consumption mode.
Referring to fig. 1, a method for improving low power consumption efficiency of a chip includes the following steps:
s10, operating the firmware, working the solid state disk, and executing S20;
s20, judging whether a low power consumption command is received, if so, executing a step S30, otherwise, executing a step S201;
s201, working normally;
s30, saving the data in the DDR, entering a first type low power consumption state, and executing a step S40;
s40, judging whether the time in the first type low power consumption state exceeds a preset time, if so, executing a step S401, and if not, executing a step S402;
s401, controlling DDR power failure, entering a second type low power consumption state, and executing S50;
s402, judging whether a command for exiting the first type low power consumption state is received or not, and executing S60;
s50, judging whether a command of exiting the second type low power consumption state is received, if so, executing a step S70, and if not, executing a step S401;
s60, the DDR exits from the self-refresh state and the firmware program is recovered from the DDR;
s70, reload the firmware program from NAND or NOR.
Specifically, after the solid state disk normally works and operates, when a low power consumption command is received, the solid state disk firstly enters a special low power consumption state, namely a first type low power consumption state, and in the state, except that the DDR enters self-refresh, other solid state disks are all in the low power consumption state. And then, when the command of exiting the first type low power consumption state is not received within the preset time, closing the DDR self-refresh (power down) to enter a lower power consumption state, namely a second type low power consumption state, and then, when the command of exiting the second type low power consumption state is received, reloading the firmware program from the NAND or the NOR. However, when a command for exiting the first type low power consumption state is received within a certain time, the DDR exits the self-refresh state and recovers the firmware program from the DDR without reloading from the NAND/NOR, and meanwhile, because the original data is still retained in the DDR, the firmware program does not need to be recovered again, which greatly shortens the subsequent initialization process and saves the power consumption value. Compared with the traditional power consumption, although the power consumption value occupied by the DDR self-refresh is increased, the recovery time of the firmware is greatly shortened, and the data is reserved in the DDR, so that the recovery time is greatly shortened, the power consumption value occupied by the DDR self-refresh is offset, positive benefits are generated, the power consumption value is reduced, and the power consumption value in the whole using process is greatly reduced.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
Corresponding to the method for improving the low power consumption efficiency of the chip, the invention also provides a device for improving the low power consumption efficiency of the chip. Referring to fig. 2, the apparatus 1 for improving chip low power consumption efficiency includes a starting unit 11, a first determining unit 12, a first executing unit 13, a second determining unit 14, a second executing unit 15, a third determining unit 16, a first recovering unit 17, a fourth determining unit 18, and a second recovering unit 19;
the starting unit 11 is used for running firmware and working the solid state disk;
a first judgment unit 12 for judging whether a low power consumption command is received;
the first execution unit 13 is configured to save the data in the DDR and enter a first type low power consumption state; when the DDR is in the first type low power consumption state, DDR self-refreshing is reserved;
a second judging unit 14, configured to judge whether the time in the first type low power consumption state exceeds a preset time;
the second execution unit 15 is used for controlling the DDR to be powered off and entering a second type low power consumption state;
a third judging unit 16, configured to judge whether a command to exit the first type low power consumption state is received;
the first recovery unit 17 is used for the DDR to exit from the self-refresh state and recover the firmware program from the DDR;
a fourth judging unit 18, configured to judge whether a command to exit the second type low power consumption state is received;
a second recovery unit 19 for reloading the firmware program from the NAND or NOR.
As shown in fig. 3, the present invention also provides a computer device, which includes a memory, a processor and a computer program stored in the memory and running on the processor, wherein the processor executes the computer program to implement the method steps for improving the low power consumption efficiency of the chip.
The computer device 700 may be a terminal or a server. The computer device 700 includes a processor 720, memory, and a network interface 750, which are connected by a system bus 710, where the memory may include non-volatile storage media 730 and internal memory 740.
The non-volatile storage medium 730 may store an operating system 731 and computer programs 732. The computer programs 732, when executed, may cause the processor 720 to perform any of a number of methods to improve the efficiency of low power consumption by the chip.
The processor 720 is used to provide computing and control capabilities, supporting the operation of the overall computer device 700.
The internal memory 740 provides an environment for the operation of the computer program 732 in the non-volatile storage medium 730, and when the computer program 732 is executed by the processor 720, the processor 720 may be enabled to perform any method for improving the low power consumption efficiency of the chip.
The network interface 750 is used for network communication such as sending assigned tasks and the like. Those skilled in the art will appreciate that the configuration shown in fig. 3 is a block diagram of only a portion of the configuration relevant to the present teachings and is not intended to limit the computing device 700 to which the present teachings may be applied, and that a particular computing device 700 may include more or less components than those shown, or may combine certain components, or have a different arrangement of components. Wherein the processor 720 is configured to execute the program code stored in the memory to perform the following steps:
the firmware runs, and the solid state disk works;
judging whether a low power consumption command is received or not;
if a low power consumption command is received, storing the data in the DDR, and entering a first type low power consumption state; when the DDR is in the first type low power consumption state, DDR self-refreshing is reserved;
judging whether the time in the first type low power consumption state exceeds a preset time or not;
and if the preset time is exceeded, controlling the DDR to be powered off, and entering a second type low power consumption state.
The further technical scheme is as follows: the second type of low power consumption state consumes less power than the first type of low power consumption state.
The further technical scheme is as follows: after the step of judging whether the time in the first type low power consumption state exceeds the preset time, the method further comprises the following steps:
if the preset time is not exceeded, judging whether a command for exiting the first type low power consumption state is received;
and if a command of exiting the first type low power consumption state is received, the DDR exits the self-refresh state and recovers a firmware program from the DDR.
The further technical scheme is as follows: after the step of controlling the DDR to power down and entering the second type low power consumption state, the method further comprises the following steps:
judging whether a command for exiting the second type low power consumption state is received;
if a command to exit the second type low power state is received, the firmware program is reloaded from the NAND or NOR.
It should be understood that, in the embodiment of the present Application, the Processor 720 may be a Central Processing Unit (CPU), and the Processor 720 may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, and the like. Wherein a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
Those skilled in the art will appreciate that the configuration of computer device 700 depicted in FIG. 3 is not intended to be limiting of computer device 700 and may include more or less components than those shown, or some components in combination, or a different arrangement of components.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present invention may be implemented in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the methods according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
It will be clear to those skilled in the art that, for convenience and simplicity of description, the foregoing division of the functional units is merely illustrated, and in practical applications, the above distribution of functions may be performed by different functional units according to needs, that is, the internal structure of the apparatus may be divided into different functional units to perform all or part of the functions described above. Each functional unit in the embodiments may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units are only used for distinguishing one functional unit from another, and are not used for limiting the protection scope of the application. For the specific working process of the units in the above-mentioned apparatus, reference may be made to the corresponding process in the foregoing method embodiment, which is not described herein again.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described device embodiments are merely illustrative, and for example, the division of the units is only one type of logical function division, and other division manners may be available in actual implementation, for example, a plurality of units or components may be combined or integrated into another device, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The technical contents of the present invention are further illustrated by the examples only for the convenience of the reader, but the embodiments of the present invention are not limited thereto, and any technical extension or re-creation based on the present invention is protected by the present invention. The protection scope of the invention is subject to the claims.
Claims (9)
1. The method for improving the low power consumption efficiency of the chip is characterized by comprising the following steps:
the firmware runs, and the solid state disk works;
judging whether a low power consumption command is received or not;
if a low power consumption command is received, storing the data in the DDR, and entering a first type low power consumption state; when the DDR is in the first type low power consumption state, DDR self-refreshing is reserved;
judging whether the time in the first type low power consumption state exceeds a preset time or not;
and if the preset time is exceeded, controlling the DDR to be powered off, and entering a second type low power consumption state.
2. The method of claim 1, wherein the second type of low power consumption state consumes less power than the first type of low power consumption state.
3. The method for improving low power consumption efficiency of a chip according to claim 1, wherein after the step of determining whether the time in the first type of low power consumption state exceeds a preset time, the method further comprises:
if the preset time is not exceeded, judging whether a command for exiting the first type low power consumption state is received;
and if a command of exiting the first type low power consumption state is received, the DDR exits the self-refresh state and recovers a firmware program from the DDR.
4. The method for improving low power consumption efficiency of chips according to claim 1, wherein after the step of controlling the DDR to power down and enter the second type low power consumption state, the method further comprises:
judging whether a command for exiting the second type low power consumption state is received;
if a command to exit the second type low power state is received, the firmware program is reloaded from the NAND or NOR.
5. The device for improving the low power consumption efficiency of the chip is characterized by comprising a starting unit, a first judging unit, a first executing unit, a second judging unit and a second executing unit;
the starting unit is used for running firmware and working the solid state disk;
the first judging unit is used for judging whether a low-power-consumption command is received or not;
the first execution unit is used for saving the data in the DDR and entering a first type low power consumption state; when the DDR is in the first type low power consumption state, DDR self-refreshing is reserved;
the second judging unit is used for judging whether the time in the first type low power consumption state exceeds a preset time or not;
and the second execution unit is used for controlling the DDR to be powered off and entering a second type low power consumption state.
6. The apparatus for improving low power consumption efficiency of a chip according to claim 5, further comprising a third determining unit and a first recovering unit;
the third judging unit is used for judging whether a command for exiting the first type low power consumption state is received or not;
and the first recovery unit is used for the DDR to exit from a self-refresh state and recover a firmware program from the DDR.
7. The apparatus for improving low power consumption efficiency of a chip according to claim 5, further comprising a fourth determining unit and a second recovering unit;
the fourth judging unit is used for judging whether a command for exiting the second type low power consumption state is received;
and the second recovery unit is used for reloading the firmware program from the NAND or the NOR.
8. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method steps of any of claims 1 to 4 when executing the computer program to improve the low power consumption efficiency of a chip.
9. A storage medium storing a computer program comprising program instructions which, when executed by a processor, cause the processor to perform the method steps of improving the low power consumption efficiency of a chip as claimed in any one of claims 1 to 4.
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| CN111813455A (en) * | 2020-07-08 | 2020-10-23 | 深圳忆联信息系统有限公司 | Low-power-consumption realization method and device of solid state disk, computer equipment and storage medium |
| CN111857596A (en) * | 2020-07-23 | 2020-10-30 | 深圳忆联信息系统有限公司 | SSD low-power-consumption realization method and device, computer equipment and storage medium |
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| CN113094197A (en) * | 2021-04-09 | 2021-07-09 | 中国工商银行股份有限公司 | Method, device, equipment and storage medium for judging instruction submission abnormity |
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