JP2013200924A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device with high controllability.SOLUTION: A nonvolatile semiconductor memory device comprises a memory cell array and a control circuit. In the memory cell array, a plurality of NAND cell units including a plurality of memory cells connected in series in a first direction are arranged in a second direction intersecting the first direction. The memory cells each include: a semiconductor layer; a charge accumulation layer formed on the semiconductor layer across a gate insulating layer; and a control gate which extends in the second direction and faces the charge accumulation layer across an inter-gate insulating layer. The control circuit is for writing data to the memory cells in units of pages, where the plurality of memory cells arranged in the second direction are regarded as a page. During write operation to the plurality of memory cells in units of pages, the control circuit adjusts a write condition of each of the memory cells in accordance with write data to each of the memory cells and write data to a memory cell adjacent to each of the memory cells in a page to be written.

Description

  The technology described in this specification relates to a nonvolatile semiconductor memory device.

  A NAND flash memory is known as a nonvolatile semiconductor memory device that can be electrically rewritten and can be highly integrated. A memory transistor of a conventional NAND flash memory has a stack gate structure in which a charge storage layer (floating gate) and a control gate are stacked via an insulating film. A plurality of memory transistors are connected in series in the column direction so that adjacent ones share a source or drain, and select gate transistors are arranged at both ends to constitute a NAND cell unit. One end of the NAND cell unit is connected to the bit line, and the other end is connected to the source line. A memory cell array is configured by arranging NAND cell units in a matrix. A NAND cell unit arranged in the row direction is called a NAND cell block. The gates of the select gate transistors arranged in the same row are connected to the same select gate line, and the control gates of the memory transistors arranged in the same row are connected to the same word line. When N memory transistors are connected in series in the NAND cell unit, the number of word lines included in one NAND cell block is N.

  In such a NAND flash memory, as the distance between memory cells decreases with miniaturization, the proximity effect due to the increase in inter-cell capacity of the memory cells increases, and the threshold distribution of the memory cells becomes wider. It becomes difficult to secure various disturbances and retention margins.

JP 2009-295232 A JP 2009-123256 A

  An object of the present invention is to provide a nonvolatile semiconductor memory device with high controllability.

  A nonvolatile semiconductor memory device according to an embodiment includes a plurality of memory cells connected in series in a first direction, a source line side select gate transistor connected between the plurality of memory cells and the source line, and a plurality of memory cells A plurality of NAND cell units each including a bit line side select gate transistor connected between the first and second bit lines are arranged in a second direction orthogonal to the first direction, and the memory cell includes a semiconductor layer, a semiconductor layer, A memory having a gate insulating layer formed on the gate insulating layer, a charge storage layer formed on the gate insulating layer, and a control gate facing the charge storage layer through the inter-gate insulating layer and extending in the second direction A cell array and a control circuit for writing data to the memory cells in units of pages using a plurality of memory cells arranged in the second direction as pages, and the control circuit includes a plurality of pages in units of pages. In write operation to the memory cell, adjusting the write condition of each memory cell in accordance with the write data to the memory cell adjacent to the write data and the memory cells for each memory cell in a page to be written.

1 is a block diagram showing an overall configuration of a nonvolatile semiconductor memory device according to a first embodiment. It is a schematic cross section showing a memory cell array structure of the nonvolatile semiconductor memory device. It is an equivalent circuit diagram of the same memory cell array. It is a perspective view of the memory cell array. It is sectional drawing of the memory cell array. It is sectional drawing cut | disconnected by the AA 'line, BB' line, and CC 'line of FIG. It is the schematic for demonstrating the write-in operation | movement which concerns on a comparative example. It is the schematic for demonstrating the write-in operation | movement. 3 is a flowchart showing a write operation of the nonvolatile semiconductor memory device according to the first embodiment. It is a flowchart which shows grouping of the same write operation. It is the schematic for demonstrating weak writing of the write-in operation | movement. It is the schematic for demonstrating the pulse allocation of the write-in operation | movement. It is the schematic for demonstrating the pulse allocation of the write-in operation | movement. It is the schematic for demonstrating the weighting of the write-in operation | movement. FIG. 10 is a schematic diagram for explaining a write operation of the nonvolatile semiconductor memory device according to the second embodiment.

  Embodiments will be described below with reference to the accompanying drawings.

[First Embodiment]
[overall structure]
FIG. 1 is a block diagram of a nonvolatile semiconductor memory device according to the first embodiment of the present invention.

  This nonvolatile semiconductor memory device includes a memory cell array 1 including a plurality of NAND strings in which a plurality of memory cells MC are NAND-connected.

  Column control for controlling the bit line BL of the memory cell array 1 at a position adjacent to the bit line BL direction of the memory cell array 1 to perform data erasure of the memory cell, data writing to the memory cell, and data reading from the memory cell. A circuit 2 is provided.

  In addition, the word line WL of the memory cell array 1 is selected at a position adjacent to the word line WL direction of the memory cell array 1 and is necessary for erasing data in the memory cell, writing data to the memory cell, and reading data from the memory cell. A row control circuit 3 is provided for applying an appropriate voltage.

  The data input / output buffer 4 is connected to an external host 9 via an I / O line, and receives write data, receives an erase command, outputs read data, and receives address data and command data. The data input / output buffer 4 sends the received write data to the column control circuit 2, receives the data read from the column control circuit 2, and outputs it to the outside. An address supplied from the outside to the data input / output buffer 4 is sent to the column control circuit 2 and the row control circuit 3 via the address register 5.

  The command supplied from the host 9 to the data input / output buffer 4 is sent to the command interface 6. The command interface 6 receives an external control signal from the host 9, determines whether the data input to the data input / output buffer 4 is write data, a command, or an address, and if it is a command, receives it as a received command signal to the state machine 7. Forward.

  The state machine 7 manages the entire nonvolatile memory. The state machine 7 receives commands from the host 9 via the command interface 6 and performs read, write, erase, data input / output management, and the like.

  The external host 9 can also receive status information managed by the state machine 7 and determine the operation result. This status information is also used for control of writing and erasing.

  The data input / output buffer 4 is connected to a comparator 61 that detects and adds the write data received by the data input / output buffer 4 and transfers it to the state machine 7. As the comparator 61, a logic circuit such as an adder circuit can be used.

  In addition, the voltage generator 60 is controlled by the state machine 7. By this control, the voltage generation circuit 60 can output a pulse having an arbitrary voltage and arbitrary timing. During the write operation, the state machine 7 adjusts the write voltage using the scheduled write data held in the data input / output buffer 4 and group information described later held in the cache, and the information output from the comparator 61 is changed. It is possible to adjust the verify voltage by referring to it.

  Here, the formed pulse can be transferred to an arbitrary wiring selected by the column control circuit 2 and the row control circuit 3. Note that peripheral circuit elements other than the memory cell array 1 can be formed on the Si substrate immediately below the memory array 1 when the memory cell array 1 is formed in a wiring layer. It is also possible to make it equal to the area of the memory cell array 1.

[Memory cell array]
Next, the configuration of the memory cell array 1 of the nonvolatile semiconductor memory device according to the first embodiment will be described.

  In this embodiment, as one of the cell structures for securing the coupling between the floating gate (charge storage layer) and the control gate, the control gate is buried on both sides of the floating gate instead of the stack gate structure, and the floating gate and both sides thereof are embedded. A gate structure for coupling to the control gate.

  FIG. 2 is a diagram showing the structure of the memory cell array 1 according to the present embodiment, and FIG. 3 is a circuit diagram of the memory cell array 1.

The memory cell array 1 includes a NAND string in which _M non-volatile memory cells MC _{0 to} MC _M−1 that can be electrically rewritten are connected in series, and select gate transistors S1 and S2 connected to both ends of the NAND string. A plurality of NAND cell units NU are arranged. One end (selection gate transistor S1 side) of the NAND cell unit NU is connected to the bit line BL, and the other end (selection gate transistor S2 side) is connected to the common source line CELSRC. The gate electrodes of the select gate transistors S1 and S2 are connected to select gate lines SGD and SGS. Control gate electrodes arranged on both sides of the memory cells MC _{0 to} MC _M-1 are connected to word lines WL _{0 to} WL _M , respectively. The bit lines BL are connected to the sense amplifier circuit 2a included in the column control circuit 2, word line _WL 0 to WL _M and the select gate lines SGD, SGS is connected to a row decoder circuit 3a included in the row control circuit 3 ing.

  In the p-type well 51 formed on the substrate, an n-type diffusion layer 52 that functions as a source and drain of a MOSFET constituting the memory cell MC is formed. A floating gate (FG) 54 is formed on the well 51 via a gate insulating film 53 functioning as a tunnel insulating film, and both sides of the floating gate 54 are interposed via an inter-gate insulating layer (IPD) 55. A control gate (CG) 56 is formed. The control gate 56 constitutes a word line WL. Further, the selection gate transistors S 1 and S 2 have a selection gate 57 on the well 51 through a gate insulating layer 53. The selection gate 57 constitutes selection gate lines SGS and SGD. Memory cell MC and select gate transistors S1, S2 are NAND-connected in such a manner that adjacent ones share a drain and a source.

[Memory cell]
In the case of 1 bit / cell in which 1 bit of data is stored in one memory cell MC, 1 page of data is stored in the memory cell MC formed along the word line WL intersecting the NAND cell unit NU. In the case of 2 bits / cell in which 2-bit data is stored in one memory cell MC, two pages (upper page UPPER, lower page LOWER) of data are stored in the memory cell MC formed along the word line WL. Is memorized. Similarly, in the case of 4 bits / cell storing 4 pages of data, the present invention is also applicable to a configuration in which 4 pages of data are stored in the memory cells MC formed along the word line WL. In this embodiment, the 2-bit / cell system is adopted, but a 1-bit / cell system, a 3-bit / cell system, or a 4-bit / cell system may be used.

[Memory block]
One block BLK includes a plurality of NAND cell units NU sharing the word line WL. One block BLK forms one unit of data erasing operation. In one memory cell array 1, the number of word lines WL in one block BLK is M + 1, and the number of pages in one block is 2 bits / cell, which is effective per NAND cell unit in one block. When the number of memory cells (number of memory cells excluding dummy cells) M = 64, M × 2 = 128 pages.

[Memory Cell Array Structure of First Embodiment]
Next, the memory cell array structure according to the first embodiment will be described.
4 is a perspective view of the memory cell array structure according to the first embodiment, FIG. 5 is a cross-sectional view as viewed from the GC (gate) direction of FIG. 4, and FIG. 6 is AA ′, BB ′ of FIG. 5 is a cross-sectional view taken along line AA (active area) in FIG. In order to make the internal structure visible, a part of the structure is omitted.

  In this memory cell array structure, the memory cell array structure shown in FIG. 2 is turned upside down and stacked, and the upper and lower memory cell array layers share a control gate.

  That is, as shown in FIGS. 4 and 5, the first semiconductor layer 11 and the second semiconductor layer 21, which form the body forming the channel, are arranged on the top and bottom of the insulator base 30, and the first semiconductor layer 11 and the second semiconductor layer 21 are interposed therebetween. The first floating gate 13 facing the upper surface of the first semiconductor layer 11 via the gate insulating layer 12 and the second floating electrode facing the lower surface of the second semiconductor layer 21 via the second gate insulating layer 22. The floating gates 23 are stacked one above the other through the first insulating layer 31. These semiconductor layers 11, 21, gate insulating layers 12, 22 and floating gates 13, 23 are layers extending in the AA direction (first direction), as is clear from the AA ′ cross section of FIG. The insulating layers 15 and 25 are insulated from each other in the GC direction (second direction).

  A plurality of stacked structures of floating gates 13 and 23 are formed at predetermined intervals in the AA direction along the semiconductor layers 11 and 21 so as to form a NAND array. Control gates 33 extending in the GC direction are formed on both sides of the stack of floating gates 13 and 23 in the AA direction via an inter-gate insulating layer (IPD: interpoly insulating layer) 32. The control gate 33 is provided in common to the floating gates 13 and 23 so as to be coupled to the upper and lower floating gates 13 and 23 from the side surface. A mask material 33 m is provided between the control gate 33 and the second gate insulating layer 22. The lower first semiconductor layer 11, the first gate insulating layer 12, the first floating gate 13, the inter-gate insulating layer 32, and the control gate 33 are included in the configuration of the lower first memory cell MC1. included. The upper second semiconductor layer 21, the second gate insulating layer 22, the second floating gate 23, the intergate insulating layer 32, and the control gate 33 are included in the configuration of the upper second memory cell MC2. .

  The first selection gate 16 and the second selection gate forming the selection gate transistors S11, S12, S21, and S22 are positioned adjacent to the control gates 33 at both ends in the arrangement direction of the stacked structure of the floating gates 13 and 23. 26 is arranged. The select gates 16 and 26 are stacked one above the other through the first insulating layer 31 and face the semiconductor layers 11 and 21 through the gate insulating layers 12 and 22, respectively. A first selection gate line 17 extending in the GC direction is embedded in the first selection gate 16, and a second selection gate line 27 extending in the GC direction and a mask material 27m are embedded in the second selection gate 26. ing. These select gate lines 17 and 27 are insulated from each other through an interlayer insulating layer 34.

  The lower first NAND cell unit NU1 includes a lower NAND-connected memory cell MC1 and select gate transistors S11 and S21. The first memory cell array layer 10 includes a first element isolation insulating layer 15. Through a plurality of NAND cell units NU1 arranged in the GC direction. The upper second NAND cell unit NU2 includes an upper NAND-connected memory cell MC2 and select gate transistors S12 and S22, and the second memory cell array layer 20 includes a plurality of NANDs arranged in the GC direction. Cell unit NU2 is included.

  In the semiconductor layers 11 and 21 at one end of the NAND cell units NU1 and NU2, a bit line contact 35 extending in common up and down to the bit line BL (not shown) is formed. Further, in the semiconductor layers 11 and 21 at the other ends of the NAND cell units NU1 and NU2, a source line contact 36 is formed which extends vertically in common to these and connects to a source line (not shown). Further, a word line contact 37 is formed at the end of the control gate 33, and a select gate line contact 38 is connected to the ends of the select gate lines 17 and 27.

  The bit line contact 35 includes a lower contact 35a and an upper contact 35b. Similarly, the source line contact 36 includes a lower contact 36a and an upper contact 36b. The lower contacts 35 a and 36 a are connected to the first semiconductor layer 11 through a first groove 81 provided in the first gate insulating layer 12. The lower contacts 35a and 36a in the present embodiment are formed simultaneously with the first floating gate 13 and the first select gate 16 as described later. Accordingly, the widths of the lower contacts 35a, 36a and the first semiconductor layer 11 in the GC direction are substantially the same. The lower contacts 35a and 36a are made of the same material as that of the first floating gate 13, and are formed in the same straight line at the same interval as the first semiconductor layer via the first element isolation insulating layer 15. Has been. The upper contacts 35b and 36b are formed so as to penetrate the second semiconductor layer 21, the second gate insulating layer 22, and the first insulating layer 31 and to be connected to the upper portions of the lower contacts 35a and 36a. . The upper contacts 35a and 36a are also made of the same material as that of the first floating gate 13.

  According to the above configuration, the floating gates 13 and 23 of the memory cells MC1 and MC2 corresponding to the upper and lower sides of the upper and lower NAND cell units NU1 and NU2 are simultaneously driven by the coupling with the word lines WL on both sides, and the common bit Connected to line BL. On the other hand, the selection gate transistors S11 to S22 are provided independently for the upper and lower bit lines BL, and either one is selectively activated to selectively activate the NAND cell units NU1 and NU2. Can be.

  In addition, since the control gates 33 common to both the upper and lower floating gates 13 and 23 are disposed on the both sides, they are hardly affected by the proximity effect in the AA direction and the diagonal direction due to the shielding effect. On the other hand, although affected by the proximity effect in the GC direction, that is, the direction in which the control gate 33 extends, this is reduced by the operation described below.

[Write operation of comparative example]
Next, an operation method of the nonvolatile semiconductor memory device according to the comparative example will be described. Hereinafter, write data for the memory cell MC will be described as data E, A, B, and C from the lowest.

As shown in FIG. 7, among the memory cells MCn−1, MCn, MCn + 1 connected to the bit lines BLn−1, BLn, BLn + 1 and included in the same page, the memory cell MCn is the target memory cell, and the word line WL The adjacent memory cells MCn−1 and MCn + 1 in the direction are defined as adjacent memory cells MCn−1 and MCn + 1. When writing write data to the target memory cell MCn, the voltage of the control gate 56 constituting the word lines WL _k , WL _{k + 1} on both sides of the floating gate 54 of the memory cell MCn is raised to a predetermined write voltage. At this time, for example, the potential VDD (power supply voltage) is applied to the bit line connected to the non-selected memory cell in the same page to make the non-selected memory cell non-selected, and the bit line connected to the selected memory cell has the potential 0 V, for example. Is applied to set the selected memory cell to a selected state, thereby selectively writing. For the control gates other than the control gate 56 on both sides of the memory cell MCn, by applying a potential 0V or Vpass which is an intermediate potential between the write voltage and 0V, the voltage is lowered, so that the memory cells other than the page to be written are applied. Prevents erroneous writing.

  Next, an example of the write operation will be described in more detail.

  FIG. 8 is a diagram illustrating an example of a data write pulse and a verify pulse applied in the comparative example. The write pulse is divided and supplied for each data level. First, a write pulse from data E to data A, B, C is applied to the memory cell MC to which data A, B, C is written, with the memory cell MC to which data E in the page to be written is written prohibited. . Next, the memory cell MC into which the data E and A are written is set in a write-inhibited state, and a step-up pulse for writing the data B and C is applied. Finally, a further step-up pulse for writing data C is applied by setting the memory cell MC to which data E, A, and B are written to a write-inhibited state.

  Next, a write verify for data A is executed, then a write verify for data B is executed, and finally a write verify for data C is executed.

  Thereafter, the write pulse is increased by a predetermined voltage, and the same write pulse application and verify operation are repeated.

  In a memory cell array having a gate structure in which control gates are embedded on both sides of a floating gate to couple the floating gate to the control gates on both sides, the coupling ratio between the floating gates is larger than that of the stack gate structure. . Therefore, in the writing method according to the comparative example, for example, when data E is written in the target memory cell MCn and data C is written in the adjacent memory cells MCn−1 and MCn + 1, erroneous writing occurs in the target memory cell due to the proximity effect. there is a possibility.

[Write Operation According to this Embodiment]
In order to solve the above problem, in the present embodiment, 1. 1. Weak writing, which will be described later, is performed on memory cells of a page to be written in advance, and the memory cells are grouped according to the writing speed; A write pulse to be applied to each memory cell is selected according to the result of grouping and data to be written to adjacent memory cells.

  FIG. 9 is a flowchart showing an example of the write operation according to the present embodiment.

  In the write operation according to the present embodiment, first, an erase operation is collectively performed on a plurality of memory cells MC included in a predetermined erase unit (step S1), and then a memory cell that is a target of the write operation is selected. Group into a plurality of groups (step S2).

  FIG. 10 is a flowchart illustrating an example of a grouping method. In the present embodiment, grouping is performed according to the write speed of the selected memory cell MCn.

  When grouping, first, weak writing is performed on the selected memory cell MCn using a predetermined weak writing voltage (step S21). If the verification is not completed, the weak writing voltage is increased to perform weak writing. The verification is repeated (steps S22 and S23).

  FIG. 11 is a diagram showing the threshold distribution after weak writing. A weak write verify level WPv is set between the erase level and the data E verify level VE, and the write voltage Vpgm when the write voltage Vpgm exceeds the weak write verify level WPv is measured while the write voltage Vpgm is sequentially stepped up.

  When weak write verification is completed in step S22, a group of memory cells MC is determined based on the write voltage Vpgm at the time of completion of verification (step S24). For example, when the write voltage when the weak write verify is completed is 10V or less, the memory cell MC has the fastest write group GR1, and when the weak write voltage when the verify is completed is 11V or less, the memory cell MC is The group GR2 with fast writing, the memory cell MC when the weak write voltage at the time of verifying is 12V or less, the memory cell MC when the group GR3 with the next fastest writing, and the weak write voltage at the completion of verification with 12V or more. MC is grouped as a group GR4 with the slowest writing.

  The determined group information can be held in a cache provided in the state machine 7 or can be held in another location such as a part of the memory cell array 1. In the present embodiment, the memory cells MC are grouped into four groups, but the number of groups in which the memory cells MC are divided can be adjusted as appropriate.

  Next, a write voltage is assigned to the selected memory cell MCn using the write data to be written to the selected memory cell MCn and the group information calculated in Step S2 (Step S3). In the present embodiment, as shown in FIG. 12, writing is performed using writing voltages P1 to P5 having 5 levels of intensity with a potential difference of 1 V to 2 V, respectively. For example, as shown in FIG. 13, a write voltage is assigned to a group having a higher write speed by assigning a lower voltage, a slower group having a higher voltage, and a write data having a lower threshold voltage having a lower voltage. It is conceivable to set a high voltage.

  In the present embodiment, a write voltage (for example, P3) assigned when writing predetermined write data (for example, data A) to a memory cell MC belonging to a predetermined group (for example, GR3), and a write speed higher than that of the predetermined group. Other data having a higher threshold voltage than the predetermined write data (for example, data B) or other data having a lower threshold voltage than other predetermined data (for example, data B). For example, the write voltage (for example, P3) assigned when writing the data E) overlaps. By setting the write voltage in this way, it is possible to reduce the type of voltage to be generated and simplify the circuit configuration.

  Next, the write voltage for the selected memory cell MCn is weighted according to the write data for the adjacent memory cells MCn−1 and MCn + 1 (step S4).

  The weighting of the write voltage is performed by processing the write data for one page held in the data input / output buffer 4 in the comparator 11 and outputting it as weight data to the state machine 7. In the present embodiment, the calculation process performed by the comparator 11 is a simple addition process. That is, for each memory cell MCn, the write data for the adjacent memory cells MCn−1 and MCn + 1 is added to obtain weight data for one page. In this embodiment, since the 2-bit / cell system (four values) is adopted, there are 4 × 4 = 16 combinations of adjacent memory cells MCn−1 and MCn + 1. Accordingly, although it is conceivable to set the weights to 16 levels, in this embodiment, as shown in FIG. 14, there are 3 levels (0, 1, 0 in the figure) according to the write data to the adjacent memory cells MCn−1 and MCn + 1. 2) Weighting is performed.

  The state machine 7 weights the value of the write voltage assigned in step S3 according to the weight data. That is, the voltage to be applied to each memory cell according to the weight data is reselected from the write voltages P1 to P5. For example, in this embodiment, when data C is written to adjacent memory cells MCn−1 and MCn + 1, the weight data of the memory cell of interest is 2 (see FIG. 14). Therefore, when the write voltage P5 is assigned to the target memory cell in step S2, the write voltage P3 is assigned again to the target memory cell.

  The influence of the proximity effect on the target memory cell MCn resulting from the write operation to the adjacent memory cells MCn−1 and MCn + 1 becomes more significant as the write data to the target memory cell MCn is smaller. Therefore, even with the same weighting, different weighting can be performed depending on the write data for the selected memory cell MCn. That is, when the write data for the selected memory cell MCn is low (for example, data E), the weight is strongly reflected, and when the write data is high (for example, data C), it is compared with the case where the write data is low. It is possible to reflect it weakly.

  Next, writing is performed on the memory cells in the selected page (steps S5 to S7). That is, first, the voltage P1 is applied to the memory cells MC to which the write voltages P1 to P5 in the page are assigned. Next, the memory cell MC to which the write voltage P1 is assigned is set in the write inhibit state, and the write voltage P2 is applied to the memory cells MC to which the write voltages P2 to P5 are assigned. Similarly, the write voltages P1 to P5 are sequentially applied to the selected memory cells in the page in accordance with the assignment of the write voltages P1 to P5 (step S5). Thereafter, verification is performed four times according to the four types of write data E, A, B, and C (step S6). If the write is not completed, the write voltages P1 to P5 are increased by a predetermined voltage, and the write is performed. Voltage application and verification are repeated (step S7). The verification for the write data E can be omitted.

According to the write operation as described above, the applied voltage can be adjusted according to the characteristics of the individual memory cells MC by grouping according to the write speed of the memory cells MC, thereby improving controllability and writing time. Can be shortened. Further, in the nonvolatile semiconductor memory device according to the present embodiment, it is possible to reduce the adjacent effect that occurs during the write operation and to provide a highly controllable nonvolatile semiconductor memory device.
[Second Embodiment]
Next, a nonvolatile semiconductor memory device according to a second embodiment will be described. The nonvolatile semiconductor memory device according to this embodiment is basically the same as the nonvolatile semiconductor memory device according to the first embodiment. However, in the nonvolatile semiconductor memory device according to this embodiment, weight data is used. Accordingly, not only the write voltage but also the verify voltage is adjusted. That is, for example, when the weight data is set as shown in FIG. 14 as in the first embodiment, the verify voltage is set to a value lower than the specified value according to the weight data as shown in FIG.

In the present embodiment, nine types of verify voltages (from the larger one: 1. VC0, 1, 2 (when data C is written to the target cell and the weight data of the target cell is 0, 1, 2) Verify voltage (the same applies hereinafter), 2. VB0,1, 3.VB2, 4.VA0, 5.VA1, 6.VA2, 7.VE0, 8.VE1, 9.VE2) are used. In the present embodiment, when the original verify voltage of the target memory cell is low, such as when data E is written to the target memory cell, the amount of decrease of the verify voltage corresponding to the weight data is set large, and the data is stored in the target memory cell. When the original verify voltage of the memory cell of interest is high, such as when B and C are written, the decrease amount of the verify voltage corresponding to the weight data is set small. For example, when the write voltage applied to the target memory cell is higher than the write voltage applied to the adjacent memory cell, the weighting for the verify voltage can be omitted. In this embodiment, when data C is written to the target memory cell, weighting for the verify voltage is omitted, and when data B is written to the target memory cell, weighting is performed only when the weight data is 2, When data A and E are written in the cell, the verify voltage is adjusted according to the weight data 1 and 2. In this embodiment, the verify voltage is adjusted based on the weight data output from the comparator. For example, the verify voltage is adjusted by comparing the write voltages P1 to P5 applied to the memory cell of interest and the adjacent memory cell, respectively. It is also possible to perform.
[Other Embodiments]
As mentioned above, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Column control circuit, 3 ... Row control circuit, 4 ... Data input / output buffer, 5 ... Address register, 6 ... Command I / F, 7 ... State machine, 10 ... Voltage generation circuit, 11 ... Comparator .

Claims (6)

A plurality of memory cells connected in series in a first direction, a source line side select gate transistor connected between the plurality of memory cells and a source line, and connected between the plurality of memory cells and a bit line. A plurality of NAND cell units each including a bit line side select gate transistor are arranged in a second direction orthogonal to the first direction, and the memory cell is formed on the semiconductor layer and the semiconductor layer. A memory cell array having a gate insulating layer, a charge storage layer formed on the gate insulating layer, and a control gate facing the charge storage layer via an inter-gate insulating layer and extending in the second direction;
A plurality of the memory cells arranged in the second direction as a page, and a control circuit for writing data to the memory cell in page units,
The control circuit includes:
A comparator for detecting write data of the plurality of selected memory cells included in the page to which the data is written;
Measuring the write speed of the memory cell;
In the write operation to the plurality of memory cells in the page unit, the plurality of memory cells to be written are grouped into a plurality of groups according to the write speed, and a write condition is adjusted according to the group And
During the write operation, the write condition of each memory cell is further adjusted according to the write data for the memory cell adjacent to each memory cell and the write data for each memory cell in the page to be written,
The nonvolatile semiconductor memory device, wherein the further adjustment of the write condition is performed according to the output of the comparator. A plurality of memory cells connected in series in a first direction, a source line side select gate transistor connected between the plurality of memory cells and a source line, and connected between the plurality of memory cells and a bit line. A plurality of NAND cell units each including a bit line side select gate transistor are arranged in a second direction orthogonal to the first direction, and the memory cell is formed on the semiconductor layer and the semiconductor layer. A memory cell array having a gate insulating layer, a charge storage layer formed on the gate insulating layer, and a control gate facing the charge storage layer via an inter-gate insulating layer and extending in the second direction;
A plurality of the memory cells arranged in the second direction as a page, and a control circuit for writing data to the memory cell in page units,
The control circuit includes:
In the write operation to the plurality of memory cells in the page unit, the write condition of each memory cell is determined according to the write data for each memory cell and the write data for the memory cell adjacent to each memory cell in the page to be written. A non-volatile semiconductor memory device characterized by adjusting. The control circuit further includes a comparator for detecting write data of a plurality of the selected memory cells included in a page to which the data is written,
The nonvolatile semiconductor memory device according to claim 2, wherein the write condition is adjusted according to an output of the comparator.   3. The control circuit according to claim 2, wherein the control circuit measures a writing speed of the memory cell, groups the memory cell into a plurality of groups according to the result, and adjusts a writing condition according to the group. Or the non-volatile semiconductor memory device of 3. The write voltage assigned when writing one data to the memory cells belonging to one group overlaps with the write voltage assigned when writing other data to the memory cells belonging to another group. The nonvolatile semiconductor memory device according to claim 4. The control circuit adjusts a verify condition of each memory cell in accordance with write data to a memory cell adjacent to each memory cell in a page to be written in a write operation to the plurality of memory cells in the page unit. The nonvolatile semiconductor memory device according to claim 2, wherein:

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