WO2009031191A1 - クロック出力回路 - Google Patents
クロック出力回路 Download PDFInfo
- Publication number
- WO2009031191A1 WO2009031191A1 PCT/JP2007/067135 JP2007067135W WO2009031191A1 WO 2009031191 A1 WO2009031191 A1 WO 2009031191A1 JP 2007067135 W JP2007067135 W JP 2007067135W WO 2009031191 A1 WO2009031191 A1 WO 2009031191A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- frequency
- signal
- time
- rise time
- outputting means
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
- H03K5/06—Shaping pulses by increasing duration; by decreasing duration by the use of delay lines or other analogue delay elements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00058—Variable delay controlled by a digital setting
- H03K2005/00065—Variable delay controlled by a digital setting by current control, e.g. by parallel current control transistors
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Abstract
バッファ回路から出力されるクロック信号の立上り時間および立下り時間の調整を精度よく行う。 クロック信号出力手段(1)は、クロック信号を出力する。バッファ回路(2)は、制御信号に応じて、クロック信号の立上り時間と立下り時間とを調整して出力する。立上り時間周波数出力手段(3a)は、制御信号に応じて、バッファ回路(2)の立上り時間に応じた周波数の立上り時間信号を出力する。立下り時間周波数出力手段(3b)は、制御信号に応じて、バッファ回路(2)の立下り時間に応じた周波数の立下り時間信号を出力する。制御信号出力手段(4)は、立上り時間信号の周波数と立下り時間信号の周波数とに基づいて、制御信号をバッファ回路(2)、立上り時間周波数出力手段(3a)、および立下り時間周波数出力手段(3b)に出力する。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009531032A JPWO2009031191A1 (ja) | 2007-09-03 | 2007-09-03 | クロック出力回路 |
PCT/JP2007/067135 WO2009031191A1 (ja) | 2007-09-03 | 2007-09-03 | クロック出力回路 |
US12/701,910 US20100141319A1 (en) | 2007-09-03 | 2010-02-08 | Clock signal output circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2007/067135 WO2009031191A1 (ja) | 2007-09-03 | 2007-09-03 | クロック出力回路 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/701,910 Continuation US20100141319A1 (en) | 2007-09-03 | 2010-02-08 | Clock signal output circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2009031191A1 true WO2009031191A1 (ja) | 2009-03-12 |
Family
ID=40428515
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2007/067135 WO2009031191A1 (ja) | 2007-09-03 | 2007-09-03 | クロック出力回路 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20100141319A1 (ja) |
JP (1) | JPWO2009031191A1 (ja) |
WO (1) | WO2009031191A1 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101929242B1 (ko) * | 2013-07-03 | 2018-12-17 | 삼성전자주식회사 | 주파수 선택도를 개선한 초재생 수신기 회로 및 초재생 수신 방법 |
EP4203313A4 (en) * | 2020-11-16 | 2024-03-20 | Changxin Memory Tech Inc | GENERATION CIRCUIT AND METHOD FOR GENERATION OF PULSE SIGNAL AND MEMORY |
TWI764813B (zh) * | 2021-08-18 | 2022-05-11 | 立積電子股份有限公司 | 驅動電路 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09261035A (ja) * | 1996-03-26 | 1997-10-03 | Nec Corp | Cmos装置 |
JP2000196435A (ja) * | 1998-12-25 | 2000-07-14 | Nec Corp | 出力バッファ回路 |
JP2001119277A (ja) * | 1999-10-18 | 2001-04-27 | Nec Corp | スルーレート調整可能な出力回路を備えた半導体回路およびその調整方法ならびに自動調整装置 |
JP2002164770A (ja) * | 2000-11-24 | 2002-06-07 | Fujitsu Ltd | 半導体集積回路 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5610548A (en) * | 1995-09-08 | 1997-03-11 | International Business Machines Corporation | Split drive clock buffer |
US6130563A (en) * | 1997-09-10 | 2000-10-10 | Integrated Device Technology, Inc. | Output driver circuit for high speed digital signal transmission |
US6331800B1 (en) * | 2000-07-21 | 2001-12-18 | Hewlett-Packard Company | Post-silicon methods for adjusting the rise/fall times of clock edges |
US7053680B2 (en) * | 2002-06-12 | 2006-05-30 | Fujitsu Limited | Complement reset buffer |
US7071747B1 (en) * | 2004-06-15 | 2006-07-04 | Transmeta Corporation | Inverting zipper repeater circuit |
US7038513B2 (en) * | 2004-06-29 | 2006-05-02 | Intel Corporation | Closed-loop independent DLL-controlled rise/fall time control circuit |
KR100868017B1 (ko) * | 2007-05-11 | 2008-11-11 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 데이터 출력 회로 |
US20090167368A1 (en) * | 2007-12-27 | 2009-07-02 | Chan Hong H | Pre-driver circuit having a post-boost circuit |
-
2007
- 2007-09-03 JP JP2009531032A patent/JPWO2009031191A1/ja not_active Withdrawn
- 2007-09-03 WO PCT/JP2007/067135 patent/WO2009031191A1/ja active Application Filing
-
2010
- 2010-02-08 US US12/701,910 patent/US20100141319A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09261035A (ja) * | 1996-03-26 | 1997-10-03 | Nec Corp | Cmos装置 |
JP2000196435A (ja) * | 1998-12-25 | 2000-07-14 | Nec Corp | 出力バッファ回路 |
JP2001119277A (ja) * | 1999-10-18 | 2001-04-27 | Nec Corp | スルーレート調整可能な出力回路を備えた半導体回路およびその調整方法ならびに自動調整装置 |
JP2002164770A (ja) * | 2000-11-24 | 2002-06-07 | Fujitsu Ltd | 半導体集積回路 |
Also Published As
Publication number | Publication date |
---|---|
US20100141319A1 (en) | 2010-06-10 |
JPWO2009031191A1 (ja) | 2010-12-09 |
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