WO2009030857A3 - Generateur et procede de generation de fonction pseudo-aleatoire a cle secrete - Google Patents

Generateur et procede de generation de fonction pseudo-aleatoire a cle secrete Download PDF

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Publication number
WO2009030857A3
WO2009030857A3 PCT/FR2008/051529 FR2008051529W WO2009030857A3 WO 2009030857 A3 WO2009030857 A3 WO 2009030857A3 FR 2008051529 W FR2008051529 W FR 2008051529W WO 2009030857 A3 WO2009030857 A3 WO 2009030857A3
Authority
WO
WIPO (PCT)
Prior art keywords
bits
generator
random function
rounds
cryptographic
Prior art date
Application number
PCT/FR2008/051529
Other languages
English (en)
Other versions
WO2009030857A2 (fr
Inventor
Yannick Seurin
Jacques Patarin
Henri Gilbert
Original Assignee
France Telecom
Yannick Seurin
Jacques Patarin
Henri Gilbert
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by France Telecom, Yannick Seurin, Jacques Patarin, Henri Gilbert filed Critical France Telecom
Priority to EP08829862A priority Critical patent/EP2204007A2/fr
Publication of WO2009030857A2 publication Critical patent/WO2009030857A2/fr
Publication of WO2009030857A3 publication Critical patent/WO2009030857A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
    • H04L9/0625—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation with splitting of the data block into left and right halves, e.g. Feistel based algorithms, DES, FEAL, IDEA or KASUMI
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
    • H04L9/0656—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher
    • H04L9/0662—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher with particular pseudorandom sequence generator

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Storage Device Security (AREA)

Abstract

L'invention concerne un générateur de fonction pseudo-aléatoire à clé secrète K d'un bloc d'entrée de m bits vers un bloc de sortie de n bits utilisant un nombre déterminé α de schémas cryptographiques Φ1(m1, n1),..., Φi(mi, ni),..., Φα(mα,nα) imbriqués en couches selon une structure récursive, chaque schéma cryptographique courant Φi(mi, ni) associant à mi bits d'entrée ni bits de sortie en un nombre de tours ri, chaque tour utilisant une fonction élémentaire interne f(i) construite à partir de ti schémas cryptographiques Φi+1(mi+1,ni+1) de ni+1 bits vers mi+1 bits, avec ni+1 < ni, mi+1 <mi et ti ≥ 1, chaque schéma cryptographique Φi(mi, ni) définissant un nombre minimal d'opérations comp(mi, ni, ri ), dépendant dudit nombre de tours ri, nécessaire pour le distinguer d'une fonction aléatoires associant mi bits d'entrée ni bits de sortie, le générateur comportant des moyens de calculs (7) pour calculer, pour chaque schéma cryptographique Φi(mi, ni), ledit nombre de tours ri de sorte que ledit nombre d'opérations comp(mi, ni, ri ) qui lui est associé soit supérieur ou égal à un nombre prédéterminé 2c, c étant un nombre entier.
PCT/FR2008/051529 2007-09-05 2008-08-26 Generateur et procede de generation de fonction pseudo-aleatoire a cle secrete WO2009030857A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP08829862A EP2204007A2 (fr) 2007-09-05 2008-08-26 Generateur et procede de generation de fonction pseudo-aleatoire a cle secrete

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0757357A FR2920617A1 (fr) 2007-09-05 2007-09-05 Generateur et procede de generation de fonction pseudo- aleatoire a cle secrete.
FR0757357 2007-09-05

Publications (2)

Publication Number Publication Date
WO2009030857A2 WO2009030857A2 (fr) 2009-03-12
WO2009030857A3 true WO2009030857A3 (fr) 2009-05-14

Family

ID=39324188

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR2008/051529 WO2009030857A2 (fr) 2007-09-05 2008-08-26 Generateur et procede de generation de fonction pseudo-aleatoire a cle secrete

Country Status (3)

Country Link
EP (1) EP2204007A2 (fr)
FR (1) FR2920617A1 (fr)
WO (1) WO2009030857A2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5682526B2 (ja) * 2011-03-28 2015-03-11 ソニー株式会社 データ処理装置、およびデータ処理方法、並びにプログラム

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998036524A1 (fr) * 1997-02-14 1998-08-20 At & T Corp. Systeme et procede de construction de chiffrements par blocs
US6185304B1 (en) * 1998-02-23 2001-02-06 International Business Machines Corporation Method and apparatus for a symmetric block cipher using multiple stages

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998036524A1 (fr) * 1997-02-14 1998-08-20 At & T Corp. Systeme et procede de construction de chiffrements par blocs
US6185304B1 (en) * 1998-02-23 2001-02-06 International Business Machines Corporation Method and apparatus for a symmetric block cipher using multiple stages

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
FRANZON P D ET AL: "Chip-Package Co-Implementation of a Triple DES Processor", IEEE TRANSACTIONS ON ADVANCED PACKAGING, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 27, no. 1, 1 February 2004 (2004-02-01), pages 194 - 202, XP011111153, ISSN: 1521-3323 *

Also Published As

Publication number Publication date
FR2920617A1 (fr) 2009-03-06
EP2204007A2 (fr) 2010-07-07
WO2009030857A2 (fr) 2009-03-12

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