WO2009030129A1

WO2009030129A1 - Information transceiving method of asynchronous serial data line and asynchronous serial transceiver

Info

Publication number: WO2009030129A1
Application number: PCT/CN2008/071466
Authority: WO
Inventors: Keping Feng
Original assignee: Maipu Communication Technology Co., Ltd.
Priority date: 2007-09-05
Filing date: 2008-06-27
Publication date: 2009-03-12
Also published as: CN101383819B; CN101383819A

Abstract

The field of data communication, especially the asynchronous serial transceiving technology is involved in this invention. The problem to be solved is: providing a method and an asynchronous serial transceiver to implement the method for quantificationally transceiving the non-character information independent of the external timer. The technology scenario is that: in the information transceiving method of asynchronous serial data line, the asynchronous serial transceiver transceives the character information, and also transceives non-character information. The asynchronous serial transceiver to implement the method includes: the character transceiver; the break controller connecting with the character transceiver; non-character recognizer; quantificational receiver. The asynchronous serial transceiver can directly transceive the non-character serial in this invention that lower system overhead and software complexity are achieved compared to the existing technologies.

Description

Heterogeneous serial data line information transmitting and receiving method and heterogeneous serial transceiver

The invention relates to the field of data communication, in particular to a heterogeneous serial data transceiving technology.

Background technique

The information on the different serial data signal line includes character data information and non-character information, and the non-character information includes an Idle sequence and a Break sequence. The Idle sequence is a continuous logic 1, indicating that the interface data signal line is idle. The Break sequence is a continuous logical 0 greater than or equal to one character length (including start and stop bits) as an in-band control signal.

Existing universal isochronous transceivers are not capable of independently quantifying the receipt and transmission of non-character information sequences. As shown in Figure 1, the universal isochronous transceiver (UART) includes a character transceiver, an interrupt controller, a receive data signal line (RXD) connected to the input of the character transceiver, an output terminal of the character transceiver and a transmit data signal line. (TXD) is connected, the control end of the character transceiver is connected to the interrupt controller, and the character transceiver and the interrupt controller communicate with the system through the local bus (Localjms), respectively.

Specifically, the universal isochronous transceiver receives the Idle sequence without directly generating any receiving action, and the application system can only indirectly determine that the unreceived information is the received Idle sequence; and indirectly sends the Idle sequence by stopping the sending method. The universal isochronous transceiver can only generate report information at the beginning and end of the receive Break sequence; control the start and end of the send Break sequence.

Some communication protocols need to directly receive and transmit Idle and Break sequences. The implementation of such communication protocols by using a universal isochronous transceiver requires an external timer. Under the control software, the Idle and Break sequences are received and sent indirectly.

At present, the use of external timers to solve the problem of receiving and transmitting Idle sequences and Break sequences in heterogeneous serial data communication requires a large system overhead, greatly increasing the complexity of the software, and seriously degrading the performance of the system when controlling multiple heterogeneous serial ports. .

Summary of the invention

The technical problem to be solved by the present invention is to provide a method for quantitatively transmitting and receiving non-character information without relying on an external timer and an isochronous serial transceiver implementing the method.

The technical solution adopted by the present invention to solve the above technical problem is: providing a method for transmitting and receiving information of a different serial data line, wherein the heterogeneous serial transceiver transmits and receives character data information through a different serial data line, and is characterized in that Including the steps to send and receive non-character information: a. When the heterogeneous serial transceiver receives non-character information from the different serial data lines, it identifies the sequence type of the non-character information and counts the sequence length of the non-character information, quantitatively receives the non-character information, and reports the received non-character to the system. Character information event;

b. When the heterogeneous serial transceiver sends non-character information to the different serial data line, the non-character information is quantitatively transmitted according to the non-character information event received from the system.

Non-character information is an Idle sequence or a Break sequence.

Specifically, the quantitative receiving non-character information is as follows: when receiving the Idle sequence, the following is: pre-setting the Idle sequence minimum value, the Idle sequence segment report length, and the Idle sequence maximum value; the Idle sequence maximum value> Idle Sequence segmentation report length> Idle sequence minimum; classification process is as follows:

(1) If the Idle sequence length of the Idle sequence to be received is the minimum value, after the isochronous serial transceiver counts the length of the Idle sequence, the isochronous serial transceiver ignores the Idle sequence and does not report to the system that the Idle sequence event is received;

(2) If the Idle sequence minimum value <Idle sequence length Idle sequence segmentation report length to be received, the Idle sequence length of the heterogeneous serial transceiver is equal to the statistical Idle sequence length, and reports the received Idle sequence event to the system. ;

(3) If the Idle sequence segment report length <the length of the Idle sequence to be received < 1 (11 ₆ sequence maximum, whenever the length of the Idle sequence is equal to the length of the Idle sequence segment report, the isochronous serial transceiver will The system reports that the Idle sequence event is received once and the re-segmentation statistics Idle sequence length is cleared until the end of the Idle sequence, and the Idle sequence event is reported to the system for the last time; except for the last report receiving the Idle sequence event, The serial length of the Idle sequence received by the serial transceiver is equal to the length of the Idle sequence segment report; the last time the Idle sequence event is received, the Idle sequence length of the heterogeneous serial transceiver is equal to the Idle sequence of the last segmentation statistics. length;

(4) If the Idle sequence maximum value is to be received by the Idle sequence length, whenever the statistical Idle sequence length is equal to the Idle sequence segment report length, the heterogeneous serial transceiver reports to the system that the Idle sequence event is received and cleared. Zero re-segmentation statistics Idle sequence length, until the accumulated Idle sequence length is equal to the Idle sequence maximum, the heterogeneous serial transceiver stops counting and reports to the system the Idle sequence event is received last time; except the last report receives the Idle sequence In addition to the event, the length of the Idle sequence received by the heterogeneous serial transceiver is equal to the length of the Idle sequence segment report; the last time the Idle sequence event is received, the isochronous serial transceiver quantizes the received Idle sequence. The length of the Idle sequence is the length of the last segmentation when the length is equal to the maximum value of the Idle sequence; the Idle sequence to be received refers to a continuous Idle sequence on the isochronous serial data line. Specifically, the non-character information is sent in the step b, and when the Idle sequence is sent, the following is: pre-setting the length of the Idle sequence to be sent;

When the isochronous serial transceiver sends the Idle sequence to be sent, and other character information or non-character information sequence needs to be sent according to the system sending event queue order, the isochronous serial transceiver sends the sequence according to the system sending event queue. Content to be sent;

When the isochronous serial transceiver sends the Idle sequence to be transmitted, and the isochronous serial transceiver does not have any content to transmit, the Idle sequence continues to be transmitted until the system sends an event.

Specifically, the quantitative receiving non-character information is as follows: when receiving the Break sequence, the following is: pre-setting a Break sequence maximum value, a Break sequence segment report length, and the Break sequence maximum value > Break sequence segment report length ;

(1) When the length of the Break sequence to be received is equal to the length of one character, the heterogeneous serial data transceiver reports to the system that the Break sequence event is received, and proceeds to step (2);

(2) If the length of the Break sequence length of the Break sequence to be received is the length of the segment sequence report, the isochronous serial transceiver reports the receipt of the Break sequence and the Break sequence termination event to the system immediately after counting the length of the Idle sequence; The length of the Break sequence received by the device is equal to the length of the statistical Break sequence;

(3) If the Break sequence segment report length <the length of the Break sequence to be received <81^&1^ sequence maximum, whenever the length of the statistical Break sequence is equal to the length of the Break sequence segment report, the isochronous serial transceiver will The system reports that the Break sequence event is received once and the resegmentation statistics Break sequence length is cleared until the end of the Break sequence, and the last time the report receives the Break sequence event and the Break sequence termination event; except for the last report received Break In addition to the sequence event, the length of the Break sequence received by the heterogeneous serial transceiver is equal to the length of the Break sequence segment report; the last time the report receives the Break sequence event, the length of the Break sequence received by the heterogeneous serial transceiver is equal to the last time. The length of the Break sequence of the segment statistics;

(4) If the Break sequence to be received is the maximum value of the Break sequence; whenever the length of the Break sequence is equal to the length of the Break sequence segment report, the isochronous serial transceiver reports to the system that the Break sequence event is received and cleared. Re-segmentation statistics the length of the Break sequence until the accumulated Break sequence length is equal to the maximum value of the Break sequence. The heterogeneous serial transceiver stops counting and reports to the system the last time the receipt of the Break sequence event is not reported until the end of the Break sequence. Break sequence termination event; except for the last report receipt of the Break sequence event, the length of the Break sequence received by the heterogeneous serial transceiver is equal to the length of the Break sequence segment report; the last report receives the sequence sequence event in the Break sequence event The length of the Break sequence received by the device is equal to the length of the Break sequence when the last segment statistics are accumulated to the maximum value of the Break sequence; the Break sequence to be received refers to a consecutive Break sequence on the different serial data lines.

Specifically, the step b sends the non-character information quantitatively, and when the Break sequence is sent, the specific: the length of the Break sequence to be sent is preset;

When the isochronous serial transceiver sends the Break sequence to be sent, and other character information or non-character information sequence needs to be sent according to the sequence of the event queue sent by the system, the isochronous serial transceiver sends the sequence according to the system sending event queue. Content to be sent;

When the isochronous serial transceiver sends the Break sequence to be sent, and the isochronous serial transceiver has nothing to send, the isochronous serial transceiver sends the Idle sequence until it receives the system to send the event.

The invention also provides an isochronous serial transceiver implementing the above method, comprising a character transceiver, an interrupt controller, an interrupt controller connected to the character transceiver, a non-character information identifier, a quantitative receiving unit, and a non-character The input end of the information recognizer and the input end of the character transceiver are respectively connected to the receiving data signal line; the non-character information identifier is connected to the quantitative receiving unit; the output end of the quantitative receiving unit is connected to the interrupt controller;

The non-character information identifier is used to identify a sequence type of non-character information;

The quantitative receiving unit is configured to count the sequence length of the non-character information, and quantitatively receive the non-character from

Specifically, the quantitative receiving unit includes a counter, a receiving comparator, a receiving comparison register, a non-character information controller, a receiving length register, and a receiving queue controller; the non-character information identifier is connected to the counter; and the receiving comparison register and the receiving comparator are The input terminal is connected, and the other input terminal of the receiving comparator is connected to the counter; the non-character information controller is respectively connected to the receiving comparator, the counter, and the non-character information identifier; the control end of the non-character information controller is connected to the counter; the non-character The output end of the information controller is respectively connected to the receiving length register and the receiving queue controller, and the output end of the receiving queue controller is connected to the interrupt controller;

The counter is configured to count a sequence length of non-character information to be received;

The receiving comparison register is configured to store a preset control receiving sequence length value; The receiving comparator is configured to compare a sequence length of the non-character information to be received and a control receiving sequence length value, and output the comparison result to the non-character information controller;

The receive length register is configured to store quantitatively received non-character information;

The non-character information controller is configured to write the quantitatively received non-character information into the receiving length register according to the comparison result, and report the receiving non-character information event to the receiving queue controller; the receiving queue controller is used to The report events of the non-character information controller and the character transceiver are organized into a queue, and an event report signal is sent to the interrupt controller in sequence.

Specifically, the quantitative receiving unit includes an Idle sequence quantitative receiving unit and a Break sequence quantitative receiving unit, and the preset control receiving sequence length value saved by the receiving comparing register includes: an Idle sequence minimum value, and an Idle sequence segment report length. , Idle sequence maximum. The preset control receiving sequence length value stored in the receiving comparison register further includes: a Break sequence segment report length, and a Break sequence maximum value.

Further, the heterogeneous serial transceiver further includes a quantitative transmitting unit, and the output of the quantitative transmitting unit is connected to the transmitting data signal line.

The quantitative transmitting unit includes a sending queue controller and a transmission length register; the character transceiver is connected to one input terminal of the transmission queue controller; the transmission length register is connected to another input terminal of the transmission queue controller; and the output of the transmission queue controller is The end connection sends a data signal line, and the sending queue controller is also connected to the interrupt controller;

The sending length register is configured to save the set non-character information to be sent; the sending queue controller is configured to organize the received sending event into a queue, according to the set length of the non-character information sequence to be sent, The sequence sends a data signal line to send.

The quantitative transmitting unit includes an Idle sequence quantitative transmitting unit and a Break sequence quantitative transmitting unit, and the set non-character information to be sent stored in the sending length register includes an Idle sequence and a Break sequence 歹 1”.

The invention has the beneficial effects that the heterogeneous serial transceiver can directly transmit and receive non-character information sequences, and the implementation method thereof can effectively reduce the system overhead and reduce the software complexity compared with the existing methods. DRAWINGS

Figure 1 is a schematic diagram of a general-purpose heterotransistor;

2 is a schematic diagram of an isochronous serial transceiver of the present invention;

3 is a block diagram of a logic circuit of an embodiment of an isochronous serial transceiver of the present invention.

detailed description In order to quantitatively transmit and receive non-character information, the present invention adds a non-character information identifier, a quantitative receiving unit, and a quantitative transmitting unit to the general-purpose heterogeneous transceiver (including the character transceiver and the interrupt controller). As shown in FIG. 2, the input end of the non-character information identifier and the input end of the character transceiver are respectively connected to the receiving data signal line; the non-character information identifier is connected to the quantitative receiving unit; the quantitative receiving unit and the quantitative transmitting unit are respectively disconnected. Controller.

A non-character information recognizer is used to identify a sequence type of non-character information;

The quantitative receiving unit is configured to count the sequence length of the non-character information sequence;

The quantitative receiving unit comprises a counter, a receiving comparator, a receiving comparison register, a non-character information controller, a receiving length register, and a receiving queue controller; the non-character information identifier is connected to the counter; and the counter is used for counting the non-character information identifier recognized by the identifier The sequence length of the non-character information sequence (non-character information to be received); the receive compare register is connected to one input of the receive comparator, and the other input of the receive comparator is connected to the counter; the non-character information controller is compared with the receive The counter, the non-character information identifier is connected; the control end of the non-character information controller is connected to the counter;

The receive comparator, the receive compare register, and the non-character information controller are used to quantitatively receive the non-character information sequence.

The non-character information recognizer is connected to the counter. The non-character information recognizer outputs a signal to the non-character information controller to inform that it has received the non-character information; the receiving comparator receives the sequence length of the non-character information sequence counted by the counter on the one hand, and receives the comparison register in the other hand on the other hand. The determined length value is compared with the sequence length of the non-character information sequence counted by the counter, and the comparison result is sent to the non-character information controller, and the comparison result is used to control the non-character information sequence directly obtained by the non-character information controller from the counter. The sequence length is subjected to quantitative reception processing, that is, the control non-character information controller writes the quantitatively received non-character information into the reception length register and reports to the reception queue controller that the non-character information sequence event is received; the character transceiver, the non-character The output of the information controller is connected to the receiving queue controller, and the receiving queue controller organizes the reporting events from the non-character information controller and the character transceiver into a queue, and sequentially issues an event reporting signal to the interrupt controller.

The quantitative sending unit comprises a sending queue controller and a sending length register; the character transceiver is connected to an input end of the sending queue controller, and the sending length register stores a preset non-character information sending comparison value; the sending length register and the sending queue control The other input of the device is connected; the output of the transmit queue controller is connected to send the data signal line; the send queue controller root According to the set length of the non-character information sequence to be sent, the transmission state of the current non-character information sequence is controlled, and the heterogeneous serial data is sent to the transmission data signal line in a quantitative manner, thereby achieving the purpose of quantitative transmission.

Of course, the non-character information can be quantitatively transmitted and received without setting the quantitative transmitting unit. After the quantitative receiving unit sends an event reporting signal to the interrupt controller in sequence, the system sends the isochronous serial data.

Example

Taking the heterogeneous serial transceiver of the Idle sequence and the Break sequence of the present invention as an example, the quantitative receiving unit includes an Idle sequence quantitative receiving unit and a Break sequence quantitative receiving unit; the quantitative transmitting unit includes an Idle sequence quantitative transmitting unit, and a Break sequence quantitative transmitting unit. unit. The length of the character data is in bytes; since both the Idle sequence and the Break sequence are repeated symbol sequences, the length of the Idle sequence and the Break sequence are in units of symbols.

For the Idle sequence, the quantitative transceiver is the maximum and minimum lengths that limit the length of the Idle sequence received by the isoband serial transceiver from the isochronous serial data line and the Idle sequence to the isochronous serial data line; The serial transceiver receives the Break sequence from the different serial data lines and the maximum length of the Break sequence transmitted to the different serial data lines.

To implement the Idle sequence quantitative reception and transmission, the following 5 registers and 2 counters are required:

1) Idle sequence minimum register: A read/write register, which is one of the receive compare registers, used to set the maximum length of the Idle sequence fragment desired to be deleted by the system, that is, the minimum length of the received Idle sequence, to avoid receiving Idle sequence fragments;

2) Idle sequence maximum register: A read/write register, which is one of the receive compare registers, is used to set a desired limit length value for a long Idle sequence, that is, the maximum length of the received Idle sequence, and the receive length is limited;

3) Idle sequence segment report register: read/write register, which is one of the receive compare registers, used to set the desired report interval length value by the system when the received Idle sequence limit register setting value is large, the transceiver segment of the present invention Reporting Idle sequence events to the system to improve the real-time performance of the report;

4) receiving the Idle sequence length register: a read-only register, configured to load the received quantitative Idle sequence length value when the transceiver reports to the system that the Idle sequence event is received;

5) Idle sequence report counter: internal counter, used to count the length of the newly received Idle sequence after the last Idle sequence event is received. The transceiver reports that the count value of the Idle sequence report counter is loaded when the Idle sequence event is received. Receive the Idle sequence length register, Clear the receiving Idle sequence report counter and restart counting;

6) Idle sequence accumulation counter: an internal counter for accumulating the length of the continuous Idle sequence from the start of the Idle sequence;

7) Idle sequence transmission length register: A read/write register, used to set the length of the Idle sequence length to be sent by the system, and control the length of the Idle sequence sent by the heterogeneous serial transceiver.

To implement the quantitative receive and transmit component of the Break sequence, the following four registers and two counters are required:

1) Break sequence maximum register: A read/write register, which is one of the receive compare registers, is used to set a desired limit length value for a long Break sequence, which is the maximum length of the receive Break sequence, and limits the receive length. ;

2) Break sequence segment report register: A read/write register, which is one of the receive compare registers, which is used to set the desired report interval length value when the Receive Break sequence limit register is set to a large value; The segment reports to the system the receipt of the Break sequence event to ensure the real-time nature of the report;

3) Receive Break Sequence Register: A read-only register, which is one of the receive compare registers, is used to report the received Break sequence event to the system when the heterogeneous serial transceiver reports the received Break sequence event, and loads the received quantitative Break sequence length value;

4) Break sequence report counter: The internal counter is used to count the length of the newly received Break sequence after the last report receives the Break sequence event; the isochronous serial transceiver reports that it will receive the Break sequence report counter when it receives the Break sequence event. The count value is loaded into the receive Break sequence register, cleared to receive the Break sequence report counter, and restarts counting;

5) Break sequence length accumulation counter: internal counter, used to accumulate the length of the continuous break sequence;

6) Break sequence transmission length register: A read/write register for writing the length of the Break sequence to be sent by the system, and controlling the length of the Break sequence sent by the heterogeneous serial transceiver.

The character data, the Break sequence and the Idle sequence appear serially on the data line of the different serial interface. The present invention uses the receive event queue to express the time sequence between the received character, the Break sequence and the Idle sequence event. Use the send event queue to express the chronological order of the characters, break sequences, and Idle sequences that need to be sent.

The heterogeneous serial transceiver quantitative receiving Idle sequence specifically includes the following processing:

Preset Idle sequence minimum, Idle sequence segmentation report length, Idle sequence maximum The value of the set Idle sequence is stored in the Idle sequence minimum value register, the Idle sequence segment value is stored in the Idle sequence segment report register, and the Idle sequence maximum value is stored in the Idle sequence maximum value register; Value > Idle sequence segment report length > Idle sequence minimum; The Idle sequence to be received refers to a continuous Idle sequence on the isochronous serial data line;

(1) If the Idle sequence length of the Idle sequence to be received is the minimum value, after the isochronous serial transceiver counts the length of the Idle sequence, the isochronous serial transceiver ignores the Idle sequence; does not report the receipt of the Idle sequence event to the system;

(3) If the Idle sequence segment report length <the length of the Idle sequence to be received < 1 (11 ₆ sequence maximum, whenever the length of the Idle sequence is equal to the length of the Idle sequence segment report, the isochronous serial transceiver will The system reports that the Idle sequence event is received once and the re-segmentation statistics Idle sequence length is cleared. For the Idle sequence divided into multiple segments, the accumulated Idle sequence length is not cleared, and the Idle sequence length is continuously accumulated from the Idle sequence start point. Until the end of the Idle sequence, the last time the system receives the Idle sequence event; except for the last time the Idle sequence event is received, the Idle sequence length of the heterogeneous serial transceiver is equal to the Idle sequence segment report length; In the last report received Idle sequence event, the length of the Idle sequence received by the heterogeneous serial transceiver is equal to the length of the Idle sequence of the last statistics;

(4) If the Idle sequence maximum value is to be received by the Idle sequence length, whenever the statistical Idle sequence length is equal to the Idle sequence segment report length, the heterogeneous serial transceiver reports to the system that the Idle sequence event is received and cleared. Zero re-segmentation statistics The length of the Idle sequence. For the Idle sequence divided into multiple segments, the accumulated Idle sequence length is unclear, and the length of the Idle sequence is continued from the start of the Idle sequence until the accumulated Idle sequence length is equal to Idle. When the sequence is at the maximum, the isochronous serial transceiver stops counting and reports to the system the last time the Idle sequence event is received. After that, the isochronous serial transceiver no longer reports the receipt of the long-length Idle sequence event until the start of the next Idle sequence. Recounting; except for the last report receiving the Idle sequence event, the Idle sequence length of the heterogeneous serial transceiver is equal to the length of the Idle sequence segment report; the last time the Idle sequence event is received, the isochronous serial transceiver The length of the Idle sequence that is quantitatively received is equal to the length of the Idle sequence of the last segmentation count when the maximum value of the Idle sequence is accumulated. The heterogeneous serial transceiver quantitatively receives the Break sequence specifically includes the following processes: pre-setting the Break sequence maximum value, the Break sequence segment report length, and storing the set Break sequence segment report length in the Break sequence segment report register. The maximum value of the Break sequence is stored in the Maximum sequence register of the Break sequence, and the maximum value of the Break sequence is > the length of the Break sequence segment report; the Break sequence to be received refers to a consecutive Break sequence of the different serial data lines;

(4) If the Break sequence to be received is the maximum value of the Break sequence; whenever the length of the Break sequence is equal to the length of the Break sequence segment report, the isochronous serial transceiver reports to the system that the Break sequence event is received and cleared. Re-segmentation statistics Break sequence length, until the accumulated Break sequence length is equal to the Break sequence maximum, the heterogeneous serial transceiver stops counting and reports to the system the last received Break sequence event until the Break sequence end point reports the Break sequence Termination event; except for the last report receipt of the Break sequence event, the length of the Break sequence received by the heterogeneous serial transceiver is equal to the length of the Break sequence segment report; the last report received the Break sequence event, the different serial transceiver The length of the quantitatively received Break sequence is equal to the length of the Break sequence of the last segmentation statistics when the maximum value of the Break sequence is accumulated.

The isochronous serial transceiver quantitatively transmits the Idle sequence, and includes the following steps: according to the length of the Idle sequence to be sent preset in the transmission length register;

When the isochronous serial transceiver sends the Idle sequence to be sent, and sends the event team according to the system. If the column order has other character information or non-character information sequences to be sent, the heterogeneous serial transceiver sends the content to be sent according to the sequence of the event queue sent by the system;

The heterogeneous serial transceiver quantitatively transmits the Break sequence, and includes the following steps: according to the pre-set break sequence to be sent in the Transmit Length register;

When the length of the Break sequence to be transmitted is equal to the set Break sequence transmission comparison value, and the heterogeneous serial transceiver has no content to transmit, the Idle sequence is transmitted until the system sends the event.

As shown in FIG. 3, the interface connected to the system by the different serial serial transceiver includes an interrupt request signal line INT and a local bus Local_bus, and the interface connected to the different serial level conversion circuit includes a transmission signal line TXD and a received signal. Line RXD. The isochronous serial control signal line is not shown in Fig. 3, and will not be described below.

The receiving data signal line RXD in the different serial serial transceiver is respectively connected with the non-character information identifier and the character transceiver; the non-character information identifier is connected by the Idle serial quantitative receiving unit and the Break sequence quantitative receiving unit respectively; the quantitative transmitting unit and the interrupt The controller is connected, and the quantitative transmitting unit is also connected to the character transceiver and the transmission data signal line TXD.

In FIG. 3, the Idle sequence quantitative receiving unit includes an Idle sequence reporting counter, an Idle sequence accumulating counter, an Idle sequence segment reporting register, an Idle sequence minimum register, an Idle sequence maximum register, an Idle sequence controller, a receiving Idle sequence length register, Receive queue controller.

The Idle sequence quantitation transmitting unit includes an Idle sequence transmission length register and a transmission queue controller.

The Break sequence quantitative receiving unit includes a Break Sequence Report Counter, a Break Sequence Accumulation Counter, a Break Sequence Segment Report Register, a Break Sequence Maximum Register, a Break Sequence Controller, a Receive Break Sequence Length Register, and a Receive Queue Controller.

The Break sequence quantitative transmitting unit includes a Break sequence transmission length register and a transmission queue controller. The character transceiver is configured to send and receive different character data, and the function and the use method of the received character of the heterogeneous serial transceiver of the present invention are the same as those of the universal isochronous transceiver. The character transceiver of the present invention also increases the output of one signal: Re _C _ch _ar signal (received character signal). The Re _C _ch _ar signal is logic 0 from the start bit of a character symbol sequence to the end of the stop bit, and the other time is logic 1, that is, when the Re _C _ch _ar signal is logic 1, it indicates the slave data signal line RXD. A non-character symbol was received on it.

The character transceiver starts from the start bit, detects that the data bit symbol is all 0s, and the stop bit symbol is also 0, that is, the Break sequence is determined, and the output detects the Break sequence signal to the Break sequence controller. Since the character transceiver checks the length of the entire character symbol to recognize the Break sequence, the Re _C _ch _ar signal output by the character transceiver is logic 0 during the entire character symbol length check, that is, when the Break sequence occurs, the character The transceiver outputs the Rec-char signal to the logical 1 starting position that lags the start of the actual Break sequence by one character length.

The character transceiver starts from the end of the stop bit and detects that the data line symbol is 1, that is, the Idle sequence is determined, and the output Rec_char signal changes from logic 0 to logic 1, so when the Idle sequence occurs, the character transceiver outputs Re _C. The _ch _ar signal has the same starting position as the logical 1 and the starting position of the actual Idle sequence.

A non-character information identifier for identifying whether the non-character symbol received on the received data signal line RXD is an Idle sequence or a Break sequence. The non-character information recognizer outputs the Idle signal and the Break signal. When the output signal is logic 1, it indicates that the corresponding sequence is received, and the output signal is logic 0 to indicate that the corresponding sequence is not received.

The Idle signal is output to the Idle sequence report counter and the Idle sequence accumulation counter. The Idle sequence report counter and the Idle sequence accumulation counter are counted while the non-character information recognizer outputs the Idle signal to logic 1, and the frequency of the clock signal used for counting is the same as the character baud rate.

The count output of the Idle sequence report counter is used as an input value of the comparator 1, and the set value of the Idle sequence segment report register is used as another input value of the comparator 1, once the count output value of the Idle sequence report counter is greater than or equal to The set value of the Idle sequence segment report register, the comparison result signal of comparator 1 is logic 1, otherwise it is logic 0. The comparison result signal of the comparator 1 is output to the Idle sequence controller.

The count output of the Idle sequence accumulation counter is used as an input value of the comparator 2, and the set value of the Idle sequence minimum value register is taken as another input value of the comparator 2, once the Idle The count output value of the sequence length accumulation counter is greater than or equal to the set value of the Idle sequence minimum value register, and the comparison result signal of the comparator 2 is logic 1, otherwise it is logic 0. The comparison result signal of the comparator 2 is output to the Idle sequence controller.

The count output of the Idle sequence accumulation counter is used as an input value of the comparator 3, and the set value of the Idle sequence maximum value register is used as another input value of the comparator 3, once the count output value of the Idle sequence length accumulation counter is greater than or equal to the Idle sequence. The set value of the maximum value register, the comparison result signal of comparator 3 is logic 1, otherwise it is logic 0. The comparison result signal of comparator 3 is output to the Idle sequence controller.

The input signal of the Idle sequence controller includes, in addition to the comparison result signals output from the comparator 1, the comparator 2, and the comparator 3, an Idle signal output from the non-character information recognizer and a count output signal of the Idle sequence length report counter.

When the state of the Idle signal output by the non-character information recognizer is logic 1, when the comparison result signal state of the comparator 1 is logic 1, the comparison result signal state of the comparator 3 is logic 0, and the comparison result signal state of the comparator 2 is logic 0 becomes logic 1, indicating that the currently received Idle sequence length reaches the segment length but does not reach the Idle sequence maximum value. The Idle sequence controller writes the count output value of the Idle sequence length report counter to the receive Idle sequence length register, and receives it. The queue controller reports receipt of an Idle sequence event. The Idle sequence controller also clears the Idle sequence length report counter by clearing signal 1 (logic 0 level signal).

When the state of the Idle signal output by the non-character information recognizer is logic 1, when the comparison result signal state of the comparator 3 changes from logic 0 to logic 1, indicating that the currently received Idle sequence length reaches the maximum value of the Idle sequence, the Idle sequence controller will The count output value of the Idle sequence length report counter is written to the receive Idle sequence length register and the Idle sequence event is reported to the receive queue controller. The Idle sequence controller issues a clear signal 1 (logic 0 level signal) to clear and block the Idle sequence length report counter, issues a clear signal 2 clear and blocks the receive Idle sequence length accumulation counter, during the subsequent period of the Idle sequence The clear and blocked state is maintained until the Idle sequence is terminated, and the Idle sequence controller issues a clear signal 1 (logic 1 level signal) and a clear signal 2 (logic 1 level signal) to release the length of the Idle sequence. Report counter and Idle sequence length accumulation counter blockade.

When the comparison result of the comparator 1 is logic 0, indicating that the Idle sequence is fragmented, the receiving Idle sequence reports that the controller has no action.

When the state of the Idle signal output by the non-character information recognizer changes from logic 1 to logic 0, it indicates The Idle sequence is terminated.

Since the start position of the Break signal lags the start of the actual Break sequence by one character length, the following counts for the length of the Break sequence do not include the value of one character length of the actual Break sequence header.

The Break signal is output to the Break Sequence Report Counter and the Receive Break Sequence Accumulator Counter. The Break sequence report counter and the Break sequence accumulation counter are counted during the non-character information recognizer output Break signal is logic 1, and the counted clock signal frequency is the same as the character baud rate.

The count output of the Break sequence report counter is used as an input value of the comparator 4, and the set value of the Break sequence segment report register is used as another input value of the comparator 4, once the count output value of the Break sequence report counter is greater than or equal to the receive Break The set value of the sequence segment report register, the comparison result signal of comparator 4 is logic 1, otherwise it is logic 0. The comparison result signal of the comparator 4 is output to the Break sequence controller.

The count output of the Break sequence accumulation counter is used as an input value of the comparator 5, and the set value of the Break sequence maximum value register is used as another input value of the comparator 5, once the count output value of the Break sequence accumulation counter is greater than or equal to the Break sequence maximum value register. The set value of Comparator 5 is logic 1 and otherwise logic 0. The comparison result of the comparator 5 is output to the Break sequence controller.

The input signal of the receive sequence sequence controller includes, in addition to the comparison result signals output by the comparator 4 and the comparator 5, a Break signal output by the non-character information recognizer and a count output signal of the Break sequence report counter, and a character transceiver output. Break sequence detection signal.

When the status of the Break sequence detection signal output by the character transceiver is logic 1, it indicates that the character transceiver detects a Break sequence of one character length, and the Break sequence controller reports to the receiving queue controller that a character sequence Break sequence event is received, and the write sequence is received. The value of the Break Sequence Length Data Register is one character length, and the Break sequence detection signal in the character transceiver is cleared by clearing the signal 5.

When the state of the Break signal output by the non-character information recognizer is logic 1, when the comparison result signal state of the comparator 4 changes from logic 0 to logic 1, the comparison result signal state of the comparator 5 is logic 0, indicating that the current Break sequence length is reached. The segment length does not reach the maximum value of the Break sequence. The Break sequence controller writes the count output value of the Break sequence report counter to the receive Break sequence length register, and reports to the receive queue controller that a persistent Break sequence event is received. Break The sequence controller also clears the Break sequence length report counter by clearing the signal 3.

When the state of the Break signal output by the non-character information recognizer is logic 1, when the comparison result signal state of the comparator 5 changes from logic 0 to logic 1, indicating that the current Break sequence length reaches the maximum value of the Break sequence, the Break sequence controller will perform the Break sequence. The count output value of the report counter is written to the receive Break sequence length register and the receive queue sequence event is reported to the receive queue controller. The Break sequence controller sends a clear signal 3 (logic 0 level signal) to clear and blocks the Break sequence report counter, issues a clear signal 4 (logic 0 level signal) to clear and blocks the receive Break sequence accumulation counter, in this Break The clearing and blocking state is maintained for the subsequent period of the sequence until the Break sequence terminates the Break sequence controller to issue a clear signal 3 (logic 1 level signal) and a clear signal 4 (logic 1 level signal) to remove the Break. The sequence report counter and the Break sequence accumulate counters are blocked, and the receipt of the Break sequence termination event is reported.

When the state of the Break signal output by the non-character information recognizer changes from logic 1 to logic 0, it indicates that the Break sequence is terminated. When the comparison result signal state of the comparator 5 is logic 0, indicating that the length of the currently received Break sequence does not reach the maximum value of the Break sequence, the Break sequence controller writes the count output value of the Break sequence report counter into the receive Break sequence register, and receives the The queue controller reports that a Break sequence termination event has been received. The Break sequence controller simultaneously issues a clear signal. 3 Clear The Break sequence reports the counter and issues a clear signal. 4 Clears the Break sequence accumulation counter.

The reporting events received by the receiving queue controller include:

1) The received character event reported by the character transceiver;

2) the detected break sequence event reported by the character transceiver;

3) receiving the received Idle sequence event reported by the Idle sequence report controller;

4) receiving the Break sequence report controller report that the received sequence length of the Break sequence event;

5) receiving the received continuous break sequence event reported by the Break Sequence Report Controller;

6) The Break sequence report controller receives the Receive Sequence termination event.

The receiving queue controller organizes the various report events that it receives into a queue, and issues an event report signal to the interrupt controller in sequence, and the interrupt controller generates an interrupt request signal INT after receiving the event report signal. The interrupt controller controls the receive queue controller not to issue a new event report signal if the existing interrupt request signal INT is not responding.

Idle sequence transmission length register for controlling the isochronous serial transceiver to send an Idle sequence The length of the column, the system sends a length register to the Idle sequence to set the length of the Idle sequence length to be sent.

The Break sequence transmission length register is configured to control the length of the Break sequence sent by the heterogeneous serial transceiver, and the length of the Break sequence to be sent is written by the system to the Break sequence transmission length register.

The sending queue controller organizes various transmission events it receives into a queue, and sends them in sequence to the transmitting data signal line TXD. When the sending queue controller sends the character data, the Break sequence or the Idle sequence, or the remaining unsent parts reach the set level, the sending queue controller sends an event reporting signal to the interrupt controller, and the interrupt controller receives the sending event report. An interrupt request signal INT is generated after the signal. The interrupt controller controls the transmit queue controller not to issue a new transmit event report signal if the existing interrupt request signal INT is not responded.

The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention. It should be covered by the scope of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

Claim

1. The method for sending and receiving serial data line information is different. The different serial serial transceiver transmits and receives character data information through the different serial data lines, and is characterized in that it further includes the steps of transmitting and receiving non-character information:

a. When the heterogeneous serial transceiver receives non-character information from the different serial data lines, it identifies the sequence type of the non-character information and counts the sequence length of the non-character information, quantitatively receives the non-character information, and reports the received non-character to the system. Character information event;

2. The method for transmitting and receiving heterogeneous serial data line information according to claim 1, wherein the non-character information is an Idle sequence.

The method for transmitting and receiving data of the different serial data line according to claim 2, wherein the step (a) receives the non-character information quantitatively, and when receiving the Idle sequence, specifically: presetting the Idle sequence minimum value, Idle Sequence segmentation report length, Idle sequence maximum value; Idle sequence maximum value> Idle sequence segmentation report length> Idle sequence minimum value; classification processing process is as follows:

(4) If the Idle sequence maximum value is to be received by the Idle sequence length, whenever the statistical Idle sequence length is equal to the Idle sequence segment report length, the heterogeneous serial transceiver reports to the system that the Idle sequence event is received and cleared. Zero re-segmentation statistics Idle sequence length until the accumulated Idle When the sequence length is equal to the maximum value of the Idle sequence, the isochronous serial transceiver stops counting and reports to the system the Idle sequence event is received. The Idle sequence transceiver receives the Idle sequence event. The sequence length is equal to the Idle sequence segment report length; the last time the Idle sequence event is received, the length of the Idle sequence received by the heterogeneous serial transceiver is equal to the Idle sequence length of the last segmentation. The Idle sequence to be received refers to a continuous Idle sequence on the heterologous serial data line.

4. The method according to claim 3, wherein the step b is to send non-character information quantitatively, and the method for transmitting the Idle sequence is: according to the system in the transmission length register The length of the Idle sequence to be sent;

The method for transmitting and receiving an isochronous serial data line information according to any one of claims 2 to 4, wherein the non-character information further comprises a break sequence.

The method for transmitting and receiving data of the different serial data line according to claim 5, wherein the quantitatively receiving the non-character information according to step a is specifically: when the Break sequence is received, the maximum value of the Break sequence is preset. Sequence segment report length, the maximum value of the Break sequence > Break sequence segment report length;

(3) If the Break sequence segment report length <the length of the Break sequence to be received <81^&1^ sequence maximum, whenever the length of the statistical Break sequence is equal to the length of the Break sequence segment report, the isochronous serial transceiver will The system reports that the Break sequence event is received once and the resegmentation statistics Break sequence length is cleared until the end of the Break sequence, and the last time the report receives the Break sequence event and the Break sequence termination event; except for the last report received Break Preface In addition to the column event, the length of the Break sequence received by the heterogeneous serial transceiver is equal to the length of the Break sequence segment report; the last time the report receives the Break sequence event, the length of the Break sequence received by the heterogeneous serial transceiver is equal to the last time. The length of the Break sequence of the segment statistics;

(4) If the Break sequence to be received is the maximum value of the Break sequence; whenever the length of the Break sequence is equal to the length of the Break sequence segment report, the isochronous serial transceiver reports to the system that the Break sequence event is received and cleared. Re-segmentation statistics Break sequence length, until the accumulated Break sequence length is equal to the Break sequence maximum, the heterogeneous serial transceiver stops counting and reports to the system the last received Break sequence event until the Break sequence end point reports the Break sequence Termination event; except for the last report receipt of the Break sequence event, the length of the Break sequence received by the heterogeneous serial transceiver is equal to the length of the Break sequence segment report; the last report receives the quasi-sequence transceiver in the Break sequence event. The length of the received Break sequence is equal to the length of the Break sequence when the last segmentation statistics are accumulated to the maximum value of the Break sequence; the Break sequence to be received refers to a consecutive Break sequence on the different serial data lines.

7. The method for transmitting and receiving heterogeneous serial data line information according to claim 6, wherein the step b transmits the non-character information quantitatively, and when transmitting the Break sequence, the specific: according to the transmission length register, the system has been preset. The length of the Break sequence to be sent;

8. The heterogeneous serial transceiver comprises a character transceiver, an interrupt controller, and the interrupt controller is connected to the character transceiver, and is characterized in that it further comprises a non-character information identifier and a quantitative receiving unit; the input of the non-character information identifier The input end of the end and the character transceiver are respectively connected to the receiving data signal line; the non-character information identifier is connected to the quantitative receiving unit; the output end of the quantitative receiving unit is connected to the interrupt controller;

9. The meta-synchronous serial transceiver according to claim 8, wherein the quantitative receiving unit comprises a counter, a receiving comparator, a receiving comparison register, a non-character information controller, a receiving length register, and a receiving queue controller; The information identifier is connected to the counter; the receiving comparison register is connected to one input of the receiving comparator, and the other input of the receiving comparator is connected to the counter; the non-character information controller and the receiving comparator, the counter, and the non-character information identifier respectively Connected; the control end of the non-character information controller is connected to the counter; the output end of the non-character information controller is respectively connected to the receive length register and the receive queue controller, and the output end of the receive queue controller is connected to the interrupt controller;

The receiving comparison register is configured to store a preset control receiving sequence length value; the receiving comparator is configured to compare a sequence length of the non-character information to be received and a control receiving sequence length value, and output the comparison result to the non-character information control Device

10. The heterogeneous serial transceiver according to claim 9, wherein the quantitative receiving unit comprises an Idle sequence quantitative receiving unit, and the preset control receiving sequence length value saved by the receiving comparing register comprises: Idle Sequence minimum, Idle sequence segmentation report length, Idle sequence maximum.

The all-in-one serial transceiver according to claim 10, wherein the quantitative receiving unit further comprises a Break sequence quantitative receiving unit, and the preset control receiving sequence length value stored in the receiving comparing register further includes : Break sequence segment report length, Break sequence maximum.

12. The meta-synchronous serial transceiver according to claim 8 or 9, further comprising a quantitative transmitting unit, wherein the output of the quantitative transmitting unit is connected to the transmitting data signal line.

13. The heterogeneous serial transceiver of claim 12, wherein the quantitative transmitting unit comprises a transmit queue controller and a transmit length register; the character transceiver is coupled to an input of the transmit queue controller; The register is connected to another input of the transmit queue controller; the output of the transmit queue controller is connected to the transmit data signal line, and the transmit queue controller is further Connected to the interrupt controller;

The all-in-one serial transceiver according to claim 13, wherein the quantitative transmitting unit comprises an Idle sequence quantitative transmitting unit, a Break sequence quantitative transmitting unit, and the set length to be sent in the transmission length register. The non-character information includes an Idle sequence and a Break sequence.