CN108462528B - FC link timeout processing circuit - Google Patents
FC link timeout processing circuit Download PDFInfo
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- CN108462528B CN108462528B CN201611142329.7A CN201611142329A CN108462528B CN 108462528 B CN108462528 B CN 108462528B CN 201611142329 A CN201611142329 A CN 201611142329A CN 108462528 B CN108462528 B CN 108462528B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/03—Arrangements for fault recovery
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/07—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
- H04B10/075—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal
- H04B10/079—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
- H04B10/0795—Performance monitoring; Measurement of transmission parameters
Abstract
The invention belongs to the technology of computing-electric digital data processing, and relates to an FC link timeout processing circuit which comprises an MAC credit management module 1, a link state management module 2, a link timeout value configuration register 3, a link timeout counter 4, a link timeout judgment module 5 and a link state control register module 6. The MAC credit management module 1 and the link state management module 2 are connected with a link timeout counter 4, the link timeout value configuration register 3, the link timeout counter 4 and the link timeout judgment module 5 are connected, and the link state control register module is connected with the link timeout judgment module 5 and the link state management module 2. The invention can realize FC link timeout processing.
Description
Technical Field
The invention belongs to the technical field of computer hardware, and particularly relates to an FC link timeout processing circuit.
Background
FC (fibre channel) is a high-speed serial protocol, and when a link is overtime due to various external reasons, a timeout recovery mechanism and related circuits are needed to recover the link, and the circuits need to solve the problem of real-time judgment and reset of FC link overtime. However, the related technical data of the circuit for solving the problem is not seen in China, and no detailed and practicable data can be referred to in foreign countries due to technical blockade.
Disclosure of Invention
The purpose of the invention is as follows:
the invention aims to provide an FC link timeout processing circuit, which controls a link to execute reset operation when the link is timed out.
The technical scheme is as follows:
the solution of the invention is:
the invention provides an FC link timeout processing circuit which comprises an MAC credit management module, a link state management module, a link timeout value configuration register, a link timeout counter, a link timeout judgment module and a link state control register module, wherein the MAC credit management module is connected with the link timeout counter, the link state management module is respectively connected with the link timeout counter and the link state control register module, the link timeout value configuration register is connected with the link timeout judgment module, and the link timeout judgment module is respectively connected with the link timeout counter and the link state control register module.
The MAC credit management module is used for managing the current available credit value of the MAC and sending the current available credit value of the MAC to the link timeout counter,
the link state management module is used for monitoring and managing the link state of the MAC and sending the current link state to the link overtime counter; controlling the skipping of the link state according to the configuration value of the link state control register module; controlling the link to perform a reset operation if the current link state is configured as a link reset state (LR) state;
the link timeout value configuration register is used for storing a link timeout threshold value;
the link overtime counter detects the current available credit value of the MAC and the current link state, when the link state is Active and the current available credit value of the MAC is 0, the count value of the counter is added, the current link state is non-Active or the current link state is Active but the current available credit value of the MAC is non-0, the counter is cleared, and the link overtime counter sends the value of the counter to the link overtime judging module;
the link overtime judging module detects the value of the link overtime configuration register and the value of the counter, and when the value of the counter is smaller than the value of the link overtime configuration register, the link is not overtime; when the value of the counter is greater than or equal to the value of the link overtime configuration register, the link overtime is indicated, the link overtime judging module generates a link overtime signal with the width of one clock period and sends the signal to the link state control register module;
when receiving the link overtime signal from the link overtime judging module, the link state control register module sets the next link state value as the link reset state ((LR) and the enable bit as 0 after maintaining one clock, and sends the next link state value and the enable bit to the link state management module to control the link state management module to complete the link reset operation.
The invention has the technical effects that:
the FC link timeout processing circuit provided by the invention generates a timeout signal by setting the timeout value register and the link timeout counter, finishes the reset operation of the FC link by the link state control register and can finish the link automatic recovery processing under the condition of FC link timeout.
Drawings
Fig. 1 is a block diagram of the FC link timeout processing circuit of the present invention.
Detailed Description
The technical solution of the present invention is further described in detail with reference to the accompanying drawings, please refer to fig. 1.
Fig. 1 is a structural block diagram of an FC link timeout processing circuit of the present invention, and as shown in fig. 1, the present invention provides an FC link timeout processing circuit, which includes an MAC credit management module 1, a link state management module 2, a link timeout value configuration register 3, a link timeout counter 4, a link timeout determination module 5, and a link state control register module 6, where the MAC credit management module 1 is connected to the link timeout counter 4, the link state management module 2 is connected to the link timeout counter 4 and the link state control register module 6, the link timeout value configuration register 3 is connected to the link timeout determination module 5, and the link timeout determination module 5 is connected to the link timeout counter 4 and the link state control register module 6, respectively.
The MAC credit management module 1 is configured to manage a current available credit value of the MAC, and send the current available credit value of the MAC to the link timeout counter 4 through the 4a interface.
The link state management module 2 is configured to manage a link state of the MAC, control a jump of the link state according to a configuration value of the link state control register module 6, execute a link reset protocol when a next link state value in the link state control register module 6 is a link reset state value and an enable bit is 1, and set a current link state to be an LR1 state. The link state management module 2 is connected with the link overtime counter 4 and sends the current link state to the link overtime counter 4; the link state management module 2 is connected to the link state control register module 6.
The link timeout value configuration register 3 is used for storing a link timeout value, and can be configured by an external processor, and the link timeout value configuration register 3 is connected with the link timeout judging module 5.
The link timeout counter 4 detects the current available credit value of the MAC and the current link state on each clock rising edge, when the link state is Active and the current available credit value of the MAC is 0, the count value of the counter is added by 1, and when the current link state is non-Active or the current link state is Active but the current available credit value of the MAC is not 0, the counter is cleared. The link timeout counter 4 is connected with the link timeout judging module 5, and sends the value of the counter to the link timeout judging module 5 through the 4c interface.
The link timeout determining module 5 detects the value of the link timeout configuration register and the value of the counter on each clock rising edge, and generates a link timeout signal with a clock period width when the two values are equal. The link timeout judging module 5 is connected with the link state control register module 6, and sends the link timeout signal to the link state control register module 6.
The link state control register module 6 detects a link timeout signal at each clock rising edge, and when the link timeout signal is valid, the next link state value is a link reset state value and the enable bit is 1, and the enable bit maintains a clock and then automatically clears 0. The link state control register module 6 is connected to the link state management module 2, and sends the next link state value and the value of the enable bit to the link state management module 2.
The FC link timeout processing circuit provided by the invention generates a timeout signal by setting the timeout value register and the link timeout counter, finishes the reset operation of the FC link by the link state control register and can finish the link automatic recovery processing under the condition of FC link timeout. Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (1)
1. An FC link timeout processing circuit, characterized by: the system comprises an MAC credit management module (1), a link state management module (2), a link timeout value configuration register (3), a link timeout counter (4), a link timeout judging module (5) and a link state control register module (6), wherein the MAC credit management module (1) is connected with the link timeout counter (4), the link state management module (2) is respectively connected with the link timeout counter (4) and the link state control register module (6), the link timeout value configuration register (3) is connected with the link timeout judging module (5), the link timeout judging module (5) is respectively connected with the link timeout counter (4) and the link state control register module (6), the MAC credit management module (1) is used for managing the current available credit value of MAC and sending the current available credit value of MAC to the link timeout counter (4), the link state management module (2), the said link state management module (2), used for monitoring and managing the link state of MAC, send the present link state to the overtime counter of the link (4); controlling the jump of the link state according to the configuration value of the link state control register module (6); if the current link state device is configured as the link reset state 1(LR1) state, the control link performs a reset operation, said link timeout value configuration register (3) for storing a link timeout threshold value, said link timeout counter (4) for detecting a current available credit value and a current link status of the MAC, when the link status is Active and the current available credit value of the MAC is 0, the count value of the counter is incremented by 1, the current link state is non-Active or the current link state is Active but the current available credit value of the MAC is not 0, the counter is cleared, the link overtime counter (4) sends the value of the counter to the link overtime judging module (5), the link overtime judging module (5) detects the value of the link overtime configuration register and the value of the counter, when the value of the counter is smaller than the value of the link overtime configuration register, the link is indicated not to be overtime; when the value of the counter is greater than or equal to the value of the link timeout configuration register, the link timeout occurs, the link timeout judging module (5) generates a link timeout signal with a clock period width and sends the signal to the link state control register module (6), when the link timeout signal sent by the link timeout judging module (5) is received, the next link state value is the link reset state 1((LR1) and the enable bit is 1, the enable bit is automatically cleared 0 after maintaining one clock, the link state control register module (6) sends the next link state value and the value of the enable bit to the link state management module (2), and the link state management module (2) is controlled to complete the link reset operation.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611142329.7A CN108462528B (en) | 2016-12-12 | 2016-12-12 | FC link timeout processing circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611142329.7A CN108462528B (en) | 2016-12-12 | 2016-12-12 | FC link timeout processing circuit |
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| CN108462528A CN108462528A (en) | 2018-08-28 |
| CN108462528B true CN108462528B (en) | 2020-12-29 |
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| CN1674529A (en) * | 2005-03-30 | 2005-09-28 | 中国人民解放军国防科学技术大学 | Method for supporting link management of hot connection and disconnection |
| US7986630B1 (en) * | 2004-02-09 | 2011-07-26 | Lsi Corporation | High performance architecture for fiber channel targets and target bridges |
| CN103051482A (en) * | 2012-12-28 | 2013-04-17 | 中国航空工业集团公司第六三一研究所 | Method for isolating and restoring port based on FC (Fiber Channel) switchboard |
| US9094294B1 (en) * | 2012-11-15 | 2015-07-28 | Qlogic, Corporation | Methods and systems for an out-of-credit timer in a network device |
| CN105376117A (en) * | 2015-12-11 | 2016-03-02 | 中国航空工业集团公司西安航空计算技术研究所 | FC switch chip data monitoring test method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9887927B2 (en) * | 2013-10-10 | 2018-02-06 | Brocade Communications Systems, Inc. | End-to-end credit recovery |
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2016
- 2016-12-12 CN CN201611142329.7A patent/CN108462528B/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7986630B1 (en) * | 2004-02-09 | 2011-07-26 | Lsi Corporation | High performance architecture for fiber channel targets and target bridges |
| CN1674529A (en) * | 2005-03-30 | 2005-09-28 | 中国人民解放军国防科学技术大学 | Method for supporting link management of hot connection and disconnection |
| US9094294B1 (en) * | 2012-11-15 | 2015-07-28 | Qlogic, Corporation | Methods and systems for an out-of-credit timer in a network device |
| CN103051482A (en) * | 2012-12-28 | 2013-04-17 | 中国航空工业集团公司第六三一研究所 | Method for isolating and restoring port based on FC (Fiber Channel) switchboard |
| CN105376117A (en) * | 2015-12-11 | 2016-03-02 | 中国航空工业集团公司西安航空计算技术研究所 | FC switch chip data monitoring test method |
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Effective date of registration: 20221012 Address after: Room S303, Innovation Building, No. 25, Gaoxin 1st Road, Xi'an, Shaanxi 710075 Patentee after: XI'AN XIANGTENG MICROELECTRONICS TECHNOLOGY Co.,Ltd. Address before: No.15, Jinye 2nd Road, Xi'an, Shaanxi 710000 Patentee before: AVIC XI''AN AERONAUTICS COMPUTING TECHNIQUE RESEARCH INSTITUTE |
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