WO2009028206A1 - 復号方法、復号装置、インタリーブ方法及び送信装置 - Google Patents

復号方法、復号装置、インタリーブ方法及び送信装置 Download PDF

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Publication number
WO2009028206A1
WO2009028206A1 PCT/JP2008/002367 JP2008002367W WO2009028206A1 WO 2009028206 A1 WO2009028206 A1 WO 2009028206A1 JP 2008002367 W JP2008002367 W JP 2008002367W WO 2009028206 A1 WO2009028206 A1 WO 2009028206A1
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WO
WIPO (PCT)
Prior art keywords
decoding
row
check matrix
processing operation
check
Prior art date
Application number
PCT/JP2008/002367
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English (en)
French (fr)
Inventor
Yutaka Murakami
Shutai Okamura
Masayuki Orihashi
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Panasonic Corporation
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Filing date
Publication date
Application filed by Panasonic Corporation filed Critical Panasonic Corporation
Priority to CN2008801040954A priority Critical patent/CN101785188B/zh
Priority to US12/674,898 priority patent/US8286050B2/en
Priority to EP08790521.2A priority patent/EP2182639B1/en
Publication of WO2009028206A1 publication Critical patent/WO2009028206A1/ja
Priority to US13/599,905 priority patent/US8448040B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1131—Scheduling of bit node or check node processing
    • H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1131—Scheduling of bit node or check node processing
    • H03M13/114—Shuffled, staggered, layered or turbo decoding schedules
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/23—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using convolutional codes, e.g. unit memory codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2742—Irregular interleaver wherein the permutation pattern is not obtained by a computation rule, e.g. interleaver based on random generators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Error Detection And Correction (AREA)

Abstract

　高速な復号動作を可能とする復号装置。復号部２１５は、検査行列による検査式の次数がＤであり、前記検査行列のｊ＋１行目の検査式とｊ行目の検査式との関係がｎビットだけシフトした関係にある場合、行処理演算部４０５＃１～４０５＃３及び列処理演算部４１０＃１～４１０＃３が、“（Ｄ＋１）×Ｎ（Ｎ：自然数）”毎に検査行列の列が区切られ、かつ“（Ｄ＋１）×Ｎ／ｎ”毎に検査行列の行が区切られて形成されたプロトグラフを、行処理演算及び列処理演算の処理単位として演算を行う。
PCT/JP2008/002367 2007-08-31 2008-08-29 復号方法、復号装置、インタリーブ方法及び送信装置 WO2009028206A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN2008801040954A CN101785188B (zh) 2007-08-31 2008-08-29 解码方法、解码装置、交织方法以及发送装置
US12/674,898 US8286050B2 (en) 2007-08-31 2008-08-29 Decoding method, decoding device, interleaving method, and transmitter
EP08790521.2A EP2182639B1 (en) 2007-08-31 2008-08-29 Low-density parity check convolution code (ldpc-cc) decoding method and decoding device
US13/599,905 US8448040B2 (en) 2007-08-31 2012-08-30 Decoding method and decoding apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007226822A JP4823176B2 (ja) 2007-08-31 2007-08-31 復号方法及び復号装置
JP2007-226822 2007-08-31

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US12/674,898 A-371-Of-International US8286050B2 (en) 2007-08-31 2008-08-29 Decoding method, decoding device, interleaving method, and transmitter
US13/599,905 Continuation US8448040B2 (en) 2007-08-31 2012-08-30 Decoding method and decoding apparatus

Publications (1)

Publication Number Publication Date
WO2009028206A1 true WO2009028206A1 (ja) 2009-03-05

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US (2) US8286050B2 (ja)
EP (1) EP2182639B1 (ja)
JP (1) JP4823176B2 (ja)
CN (1) CN101785188B (ja)
WO (1) WO2009028206A1 (ja)

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JP6511284B2 (ja) * 2015-02-13 2019-05-15 パナソニック株式会社 最小値選択回路、復号器及び最小値選択方法
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Also Published As

Publication number Publication date
EP2182639A1 (en) 2010-05-05
CN101785188B (zh) 2013-04-03
US20120324309A1 (en) 2012-12-20
JP4823176B2 (ja) 2011-11-24
EP2182639B1 (en) 2017-05-17
US8448040B2 (en) 2013-05-21
JP2009060453A (ja) 2009-03-19
EP2182639A4 (en) 2010-11-10
US8286050B2 (en) 2012-10-09
CN101785188A (zh) 2010-07-21
US20110113300A1 (en) 2011-05-12

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