JP4823176B2 - 復号方法及び復号装置 - Google Patents
復号方法及び復号装置 Download PDFInfo
- Publication number
- JP4823176B2 JP4823176B2 JP2007226822A JP2007226822A JP4823176B2 JP 4823176 B2 JP4823176 B2 JP 4823176B2 JP 2007226822 A JP2007226822 A JP 2007226822A JP 2007226822 A JP2007226822 A JP 2007226822A JP 4823176 B2 JP4823176 B2 JP 4823176B2
- Authority
- JP
- Japan
- Prior art keywords
- row
- processing
- decoding
- column
- check matrix
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1131—Scheduling of bit node or check node processing
- H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1131—Scheduling of bit node or check node processing
- H03M13/114—Shuffled, staggered, layered or turbo decoding schedules
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/23—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using convolutional codes, e.g. unit memory codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2742—Irregular interleaver wherein the permutation pattern is not obtained by a computation rule, e.g. interleaver based on random generators
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Probability & Statistics with Applications (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Computing Systems (AREA)
- Error Detection And Correction (AREA)
Description
A. J. Felstorom, and K. Sh. Zigangirov, "Time-Varying Periodic Convolutional Codes With Low-Density Parity-Check Matrix," IEEE Transactions on Information Theory, Vol.45, No.6,pp2181-2191, September 1999. G. Richter, M. Kaupper, and K. Sh. Zigangirov, "Irregular low-density parity-Check convolutionalcodes based on protographs, "Proceeding of IEEE ISIT 2006, pp1633-1637. J. Zhang, and M. P. C. Fossorier, "Shuffled iterative decoding," IEEE Trans. Commun., vol.53, no.2, pp.209-213, Feb. 2005. D. Hocevar, "A reduced complexity decoder architecture via layered decoding of LDPC codes," in Signal Processing Systems SIPS 2004. IEEE Workshop on, pp.107-112, Oct. 2004. B. Lu, G. Yue, and X. Wang, "Performance analysis and design optimization of LDPC-coded MIMO OFDM systems" IEEE Trans. Signal Processing., vol.52, no.2, pp.348-361, Feb. 2004. B. M. Hochwald, and S. ten Brink, "Achieving near-capacity on a multiple-antenna channel" IEEE Trans. Commun., vol.51, no.3, pp.389-399, March 2003. S. Baro, J. Hagenauer, and M. Wizke, "Iterative detection of MIMO transmission using a list-sequential (LISS) detector" Proceeding of IEEE ICC 2003, pp2653-2657. S. Lin, D. J. Jr., Costello, "Error control coding : Fundamentals and applications," Prentice-Hall. R. D. Gallager, "Low-Density Parity-Check Codes," Cambridge, MA: MIT Press, 1963. M. P. C. Fossorier, M. Mihaljevic, and H. Imai, "Reduced complexity iterative decoding of low density parity check codes based on belief propagation," IEEE Trans. Commun., vol.47., no.5, pp.673-680, May 1999. J. Chen, A. Dholakia, E. Eleftheriou, M. P. C. Fossorier, and X.-Yu Hu, "Reduced-complexity decoding of LDPC codes," IEEE Trans. Commun., vol.53.,no.8, pp.1288-1299, Aug. 2005.
(1)復号アルゴリズム
(1−1)LDPC-CCの一般的な復号アルゴリズム
先ず、本発明による復号方法を説明する前に、LDPC-CCの一般的な復号アルゴリズムを説明する。
Hmn=1を満たす全ての組(m,n)に対して、対数尤度比β(0) mn=λnと設定する。また、ループ変数(反復回数)lsum=1と設定し、ループ最大回数をlsum,maxと設定する。
m=1,2,・・・,Mの順にHmn=1を満たす全ての組(m,n)に対して、次の更新式を用いて対数尤度比α(i) mnを更新する。但し、iは反復回数を表す。また、fはGallagerの関数である。
もしlsum<lsum,maxならばlsumをインクリメントして、step A・2に戻る。lsum=lsum,maxの場合、次式に示すように符号語wを推定して、sum-product復号を終了する。
ところで、非特許文献3及び非特許文献4でも指摘されているように、sum-product復号は、良好な受信品質得るためには、上記反復復号の反復回数を多く設定しなければならないという欠点がある。
図6に、本実施の形態の送信装置の構成例を示す。符号化部102は、送信ディジタル信号101をLDPC―CC符号化し、これにより得た符号化データ103をインタリーブ部104に出力する。
実施の形態1では、LDPC-CCのBP復号において、演算規模が小さく、かつ、良好な受信品質を得ることができる方法及び構成について説明した。
本実施の形態では、受信側で実施の形態2で説明した復号を行う場合に適した、送信側でのインタリーブ方法を提示する。本実施の形態では、一例として、送信装置が図6のように、符号化を行った後にインタリーブを施す場合の構成について説明する。
ここでは、これまで説明してきたLDPC-CCのパリティ検査行列とは異なる形のパリティ検査行列を用いたLDPC-CCへの実施方法について説明する。ここでは、特に、非特許文献2に示されているように、プロトグラフと特定の位置とに、“1”が存在するパリティ検査行列を用いたLDPC-CCへの実施方法について詳しく説明する。
102 符号化部
104 インタリーブ部
200 受信装置
213 デインタリーバ
215,500 復号部
405#1,405#2,405#3 行処理演算部
407,512#1〜512#Z 行処理後データ記憶部
410#1,410#2,410#3 列処理演算部
412,518#1〜518#Z 列処理後データ記憶部
416,522 対数尤度比演算部
418,524 判定部
505,510,514,516,520 接続切替部
507#1〜507#Z 行・列処理演算部
Claims (4)
- LDPC-CC(Low-Density Parity-Check Convolutional Code)をBP(Belief-Propagation)復号する復号方法であって、
パリティ検査行列を用いて行処理演算及び列処理演算を行う演算ステップと、
前記演算ステップでの演算結果を用いて符号語を推定するステップと、
を含み、
前記パリティ検査行列による検査式の次数がDであり、前記パリティ検査行列のj+1行目の検査式とj行目の検査式との関係がnビットだけシフトした関係にある場合、
前記演算ステップでは、
“(D+1)×N(N:自然数)”毎に前記パリティ検査行列の列が区切られ、かつ“(D+1)×N/n”毎に前記パリティ検査行列の行が区切られて形成されたプロトグラフを、前記行処理演算及び列処理演算の処理単位として演算を行い、
前記プロトグラフは、前記“(D+1)×N(N:自然数)”毎に規則的に配置される
復号方法。 - 畳み込み符号をBP(Belief-Propagation)復号する復号方法であって、
パリティ検査行列を用いて行処理演算及び列処理演算を行う演算ステップと、
前記演算ステップでの演算結果を用いて符号語を推定するステップと、
を含み、
前記パリティ検査行列による検査式の次数がDであり、前記パリティ検査行列のj+1行目の検査式とj行目の検査式との関係がnビットだけシフトした関係にある場合、
前記演算ステップでは、
“(D+1)×N(N:自然数)”毎に前記パリティ検査行列の列が区切られ、かつ“(D+1)×N/n”毎に前記パリティ検査行列の行が区切られて形成されたプロトグラフを、前記行処理演算及び列処理演算の処理単位として演算を行い、
前記プロトグラフは、前記“(D+1)×N(N:自然数)”毎に規則的に配置される
復号方法。 - 前記演算ステップは、
複数のグループに分割された、前記プロトグラフ単位の行処理演算及び列処理演算を、逐次的に行う逐次演算ステップと、
複数の前記逐次的演算を、時間をずらしながら並列に行う並列演算ステップと、
を含む請求項1又は請求項2に記載の復号方法。 - LDPC-CC(Low-Density Parity-Check Convolutional Code)をBP(Belief-Propagation)復号する復号装置であって、
パリティ検査行列を用いて行処理演算を行う行処理演算部と、
前記パリティ検査行列を用いて列処理演算を行う列処理演算部と、
前記行処理演算部及び前記列処理演算部での演算結果を用いて符号語を推定する判定部と、
を有し、
前記パリティ検査行列による検査式の次数がDであり、前記パリティ検査行列のj+1行目の検査式とj行目の検査式との関係がnビットだけシフトした関係にある場合、
前記行処理演算部及び前記列処理演算部は、
“(D+1)×N(N:自然数)”毎に前記パリティ検査行列の列が区切られ、かつ“(D+1)×N/n”毎に前記パリティ検査行列の行が区切られて形成されたプロトグラフを、前記行処理演算及び列処理演算の処理単位として演算を行い、
前記プロトグラフは、前記“(D+1)×N(N:自然数)”毎に規則的に配置される
復号装置。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007226822A JP4823176B2 (ja) | 2007-08-31 | 2007-08-31 | 復号方法及び復号装置 |
EP08790521.2A EP2182639B1 (en) | 2007-08-31 | 2008-08-29 | Low-density parity check convolution code (ldpc-cc) decoding method and decoding device |
US12/674,898 US8286050B2 (en) | 2007-08-31 | 2008-08-29 | Decoding method, decoding device, interleaving method, and transmitter |
CN2008801040954A CN101785188B (zh) | 2007-08-31 | 2008-08-29 | 解码方法、解码装置、交织方法以及发送装置 |
PCT/JP2008/002367 WO2009028206A1 (ja) | 2007-08-31 | 2008-08-29 | 復号方法、復号装置、インタリーブ方法及び送信装置 |
US13/599,905 US8448040B2 (en) | 2007-08-31 | 2012-08-30 | Decoding method and decoding apparatus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007226822A JP4823176B2 (ja) | 2007-08-31 | 2007-08-31 | 復号方法及び復号装置 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011136302A Division JP5171997B2 (ja) | 2011-06-20 | 2011-06-20 | 復号方法及び復号装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009060453A JP2009060453A (ja) | 2009-03-19 |
JP4823176B2 true JP4823176B2 (ja) | 2011-11-24 |
Family
ID=40386939
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007226822A Expired - Fee Related JP4823176B2 (ja) | 2007-08-31 | 2007-08-31 | 復号方法及び復号装置 |
Country Status (5)
Country | Link |
---|---|
US (2) | US8286050B2 (ja) |
EP (1) | EP2182639B1 (ja) |
JP (1) | JP4823176B2 (ja) |
CN (1) | CN101785188B (ja) |
WO (1) | WO2009028206A1 (ja) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103281091B (zh) | 2007-09-28 | 2017-10-27 | 松下电器产业株式会社 | 编码方法、编码器、解码器、发送装置和接收装置 |
US8516351B2 (en) * | 2009-07-21 | 2013-08-20 | Ramot At Tel Aviv University Ltd. | Compact decoding of punctured block codes |
US8375278B2 (en) * | 2009-07-21 | 2013-02-12 | Ramot At Tel Aviv University Ltd. | Compact decoding of punctured block codes |
US9397699B2 (en) * | 2009-07-21 | 2016-07-19 | Ramot At Tel Aviv University Ltd. | Compact decoding of punctured codes |
US8516352B2 (en) * | 2009-07-21 | 2013-08-20 | Ramot At Tel Aviv University Ltd. | Compact decoding of punctured block codes |
JP2011051841A (ja) | 2009-09-02 | 2011-03-17 | Ismanj:Kk | シリコン合金焼結体の製造方法 |
US9131238B2 (en) * | 2010-06-18 | 2015-09-08 | The Trustees Of Princeton University | System and method for lossy source-channel coding at the application layer |
JP5485069B2 (ja) | 2010-08-06 | 2014-05-07 | パナソニック株式会社 | 誤り訂正復号装置及び誤り訂正復号方法 |
US8879640B2 (en) * | 2011-02-15 | 2014-11-04 | Hong Kong Applied Science and Technology Research Institute Company Limited | Memory efficient implementation of LDPC decoder |
CN102687445B (zh) | 2011-12-30 | 2015-01-21 | 华为技术有限公司 | 前向纠错编、解码方法、装置及系统 |
WO2013140727A1 (ja) * | 2012-03-19 | 2013-09-26 | パナソニック株式会社 | 復号装置 |
EP2905904B1 (en) * | 2012-10-05 | 2018-12-05 | Sun Patent Trust | Coding method, decoding method, coder, and decoder |
WO2015141903A1 (ko) * | 2014-03-17 | 2015-09-24 | 엘지전자 주식회사 | 무선 통신 시스템에서의 순방향 에러 정정을 위한 저밀도 패리티 체크 코드의 디코딩 방법 및 장치 |
US20160020787A1 (en) * | 2014-07-18 | 2016-01-21 | Kabushiki Kaisha Toshiba | Decoding apparatus, decoding method and non-transitory computer-readable recording medium containing a decoding program |
JP6511284B2 (ja) * | 2015-02-13 | 2019-05-15 | パナソニック株式会社 | 最小値選択回路、復号器及び最小値選択方法 |
EP3447926B1 (en) | 2016-05-16 | 2021-09-15 | Huawei Technologies Co., Ltd. | Convolutional ldpc decoding method, device, decoder, and system |
CN110024297B (zh) * | 2016-10-14 | 2023-07-18 | 马维尔亚洲私人有限公司 | 低密度奇偶校验解码器中的用于基于对数似然比的动态预处理选择方案的系统和方法 |
EP3700094B1 (en) * | 2017-11-27 | 2024-04-17 | Mitsubishi Electric Corporation | Error correction device and optical transmission/reception device |
US11012100B2 (en) * | 2019-06-03 | 2021-05-18 | The Regents Of The University Of California | Convolutional precoding and decoding of polar codes |
US11223372B2 (en) * | 2019-11-27 | 2022-01-11 | Hughes Network Systems, Llc | Communication throughput despite periodic blockages |
CN112165338B (zh) * | 2020-09-30 | 2023-05-02 | 电子科技大学 | 一种卷积码随机交织序列交织关系的估计方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7222289B2 (en) * | 2002-09-30 | 2007-05-22 | Certance Llc | Channel processor using reduced complexity LDPC decoder |
US7181676B2 (en) * | 2004-07-19 | 2007-02-20 | Texas Instruments Incorporated | Layered decoding approach for low density parity check (LDPC) codes |
US7143333B2 (en) * | 2004-08-09 | 2006-11-28 | Motorola, Inc. | Method and apparatus for encoding and decoding data |
WO2006016261A1 (en) * | 2004-08-13 | 2006-02-16 | Nokia Corporation | Structured puncturing of irregular low-density parity-check (ldpc) codes |
WO2006059688A1 (ja) * | 2004-12-02 | 2006-06-08 | Mitsubishi Denki Kabushiki Kaisha | 復号装置及び通信装置 |
US7500172B2 (en) * | 2005-02-26 | 2009-03-03 | Broadcom Corporation | AMP (accelerated message passing) decoder adapted for LDPC (low density parity check) codes |
US7499490B2 (en) * | 2005-06-24 | 2009-03-03 | California Institute Of Technology | Encoders for block-circulant LDPC codes |
US7343539B2 (en) * | 2005-06-24 | 2008-03-11 | The United States Of America As Represented By The United States National Aeronautics And Space Administration | ARA type protograph codes |
JP2007043635A (ja) | 2005-06-29 | 2007-02-15 | Samsung Electronics Co Ltd | 低密度パリティ検査符号の復号装置、復号方法および復号プログラム |
US7853862B2 (en) * | 2005-08-03 | 2010-12-14 | Qualcomm Incorporated | Systems and methods for a turbo low-density parity-check decoder |
CN100544212C (zh) * | 2006-01-23 | 2009-09-23 | 南京大学 | 高速的减少存储需求的低密度校验码解码器 |
JP4550857B2 (ja) | 2007-04-06 | 2010-09-22 | 株式会社日立製作所 | 情報処理装置の割当て方法、この方法を実行する管理サーバ及び端末 |
KR101077552B1 (ko) * | 2007-12-14 | 2011-10-28 | 한국전자통신연구원 | 복수의 기본 패리티 검사행렬을 이용한 저밀도 패리티 검사부호의 복호화 장치 및 그 방법 |
-
2007
- 2007-08-31 JP JP2007226822A patent/JP4823176B2/ja not_active Expired - Fee Related
-
2008
- 2008-08-29 CN CN2008801040954A patent/CN101785188B/zh not_active Expired - Fee Related
- 2008-08-29 EP EP08790521.2A patent/EP2182639B1/en not_active Not-in-force
- 2008-08-29 US US12/674,898 patent/US8286050B2/en active Active
- 2008-08-29 WO PCT/JP2008/002367 patent/WO2009028206A1/ja active Application Filing
-
2012
- 2012-08-30 US US13/599,905 patent/US8448040B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20120324309A1 (en) | 2012-12-20 |
CN101785188B (zh) | 2013-04-03 |
EP2182639B1 (en) | 2017-05-17 |
US8448040B2 (en) | 2013-05-21 |
US8286050B2 (en) | 2012-10-09 |
CN101785188A (zh) | 2010-07-21 |
WO2009028206A1 (ja) | 2009-03-05 |
EP2182639A4 (en) | 2010-11-10 |
JP2009060453A (ja) | 2009-03-19 |
US20110113300A1 (en) | 2011-05-12 |
EP2182639A1 (en) | 2010-05-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4823176B2 (ja) | 復号方法及び復号装置 | |
US8423876B2 (en) | Low-density parity check convolution code (LDPC-CC) encoder and LDPC-CC decoder | |
JP4555333B2 (ja) | 可変符号化率を有するブロック低密度パリティ検査符号の符号化/復号装置及び方法 | |
US9276611B2 (en) | Encoding method, encoder, and decoder | |
CN104467872B (zh) | 编码方法以及解码器 | |
JP6300993B2 (ja) | 変調信号復号方法及び変調信号復号装置 | |
US8910025B2 (en) | Method and apparatus of QC-LDPC convolutional coding and low-power high throughput QC-LDPC convolutional encoder and decoder | |
JP2009044732A (ja) | 送信装置及び送信方法 | |
JP5789014B2 (ja) | 符号化方法、符号化器、復号器 | |
JP2016154350A (ja) | 送信装置および送信方法 | |
JP5171997B2 (ja) | 復号方法及び復号装置 | |
KR20180122911A (ko) | 통신 또는 방송 시스템에서 채널 부호화/복호화 방법 및 장치 | |
KR20190000768A (ko) | 통신 또는 방송 시스템에서 채널 부호화/복호화 방법 및 장치 | |
JP2009118418A (ja) | 復号化装置、符号化装置、復号化方法、及び、符号化方法 | |
JP2009177649A (ja) | 符号化方法、符号化器、復号器 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20100125 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110419 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110620 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110816 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110906 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 Ref document number: 4823176 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140916 Year of fee payment: 3 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |