WO2009028200A1 - ２周波整合回路 - Google Patents

２周波整合回路 Download PDF

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Publication number
WO2009028200A1
WO2009028200A1 PCT/JP2008/002352 JP2008002352W WO2009028200A1 WO 2009028200 A1 WO2009028200 A1 WO 2009028200A1 JP 2008002352 W JP2008002352 W JP 2008002352W WO 2009028200 A1 WO2009028200 A1 WO 2009028200A1
Authority
WO
WIPO (PCT)
Prior art keywords
elements
inductance
inductor
load
segments
Prior art date
Application number
PCT/JP2008/002352
Other languages
English (en)
French (fr)
Inventor
Ushio Sangawa
Original Assignee
Panasonic Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corporation filed Critical Panasonic Corporation
Priority to JP2008551584A priority Critical patent/JP4308888B2/ja
Priority to US12/352,285 priority patent/US7573351B1/en
Publication of WO2009028200A1 publication Critical patent/WO2009028200A1/ja

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H04B1/0458—Arrangements for matching and coupling between power amplifier and antenna or between amplifying stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/38—Impedance-matching networks

Abstract

　入力端子（２）、素子（４ａ，４ｂ，４ｃ，４ｄ）、負荷（５）の接続形態を、電卓やデジタル時計などの数字の表示に適用される「７セグメントディスプレイ」状にする。すなわち、７セグメントディスプレイの横方向に延びる３つのセグメント中の、最上部と最下部にあるセグメントを入力端子（２）に割り当て、残り１つの横方向に延びるセグメントに負荷５を割り当てれば、残りの縦方向の４セグメントが素子（４ａ，４ｂ，４ｃ，４ｄ）に相当する。素子４ａ、４ｂ、４ｃ、４ｄは、それぞれ、２．１３２ｎＨのインダクタンスを有するインダクタ、８．２６６ｎＨのインダクタンスを有するインダクタ、０．５９６ｎＨのインダクタンスを有するインダクタ、２．０９７ｐＦのキャパシタンスを有するキャパシである。この回路構成により、素子総数が４に減じられることによって低損失性が実現され、また、構成回路中から共振回路が排除されるとともに梯子回路の規模が縮小されることにより、負荷５のインピーダンス変動に対して高安定なインピーダンス整合が行える。
PCT/JP2008/002352 2007-08-29 2008-08-28 ２周波整合回路 WO2009028200A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008551584A JP4308888B2 (ja) 2007-08-29 2008-08-28 ２周波整合回路及びそれを具備する携帯端末
US12/352,285 US7573351B1 (en) 2007-08-29 2009-01-12 Dual-frequency matching circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-222413 2007-08-29
JP2007222413 2007-08-29

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/352,285 Continuation US7573351B1 (en) 2007-08-29 2009-01-12 Dual-frequency matching circuit

Publications (1)

Publication Number Publication Date
WO2009028200A1 true WO2009028200A1 (ja) 2009-03-05

Family

ID=40386936

Family Applications (3)

Application Number Title Priority Date Filing Date
PCT/JP2008/002352 WO2009028200A1 (ja) 2007-08-29 2008-08-28 ２周波整合回路
PCT/JP2008/002353 WO2009028201A1 (ja) 2007-08-29 2008-08-28 ２周波整合回路
PCT/JP2008/002351 WO2009028199A1 (ja) 2007-08-29 2008-08-28 ２周波整合回路

Family Applications After (2)

Application Number Title Priority Date Filing Date
PCT/JP2008/002353 WO2009028201A1 (ja) 2007-08-29 2008-08-28 ２周波整合回路
PCT/JP2008/002351 WO2009028199A1 (ja) 2007-08-29 2008-08-28 ２周波整合回路

Country Status (4)

Country Link
US (3) US7573352B2 (ja)
JP (3) JP4308887B2 (ja)
CN (3) CN101569098A (ja)
WO (3) WO2009028200A1 (ja)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE536254C2 (sv) * 2010-11-12 2013-07-23 Osseofon Ab Anpassningsnät till benledningsvibrator
US9720022B2 (en) 2015-05-19 2017-08-01 Lam Research Corporation Systems and methods for providing characteristics of an impedance matching model for use with matching networks
KR101719551B1 (ko) 2013-10-28 2017-03-24 주식회사 하이딥 안테나 장치

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06252791A (ja) * 1993-02-26 1994-09-09 Nec Corp アンテナ用二周波整合回路
JP2000077964A (ja) * 1998-08-28 2000-03-14 Mitsubishi Electric Corp ２周波整合回路

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5746384A (en) 1980-08-21 1982-03-16 Ibm Magnetic bubble domain memory
JPS5746385A (en) 1980-09-03 1982-03-16 Fujitsu Ltd Address discrimination method of semiconductor memory
TW486861B (en) * 2001-07-04 2002-05-11 Ind Tech Res Inst Impedance matching circuit for a multi-band power amplifier
JP4216124B2 (ja) 2002-12-12 2009-01-28 三菱電機株式会社 ２周波整合回路
US7326872B2 (en) 2004-04-28 2008-02-05 Applied Materials, Inc. Multi-frequency dynamic dummy load and method for testing plasma reactor multi-frequency impedance match networks
JP4838536B2 (ja) 2005-05-20 2011-12-14 株式会社エヌ・ティ・ティ・ドコモ 整合回路

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06252791A (ja) * 1993-02-26 1994-09-09 Nec Corp アンテナ用二周波整合回路
JP2000077964A (ja) * 1998-08-28 2000-03-14 Mitsubishi Electric Corp ２周波整合回路

Also Published As

Publication number Publication date
JP4308885B2 (ja) 2009-08-05
CN101569098A (zh) 2009-10-28
JP4308887B2 (ja) 2009-08-05
JPWO2009028201A1 (ja) 2010-11-25
US20090189710A1 (en) 2009-07-30
US7579924B2 (en) 2009-08-25
US7573351B1 (en) 2009-08-11
JPWO2009028200A1 (ja) 2010-11-25
US20090121962A1 (en) 2009-05-14
US7573352B2 (en) 2009-08-11
CN101569096A (zh) 2009-10-28
JPWO2009028199A1 (ja) 2010-11-25
WO2009028201A1 (ja) 2009-03-05
WO2009028199A1 (ja) 2009-03-05
US20090121960A1 (en) 2009-05-14
JP4308888B2 (ja) 2009-08-05
CN101569099A (zh) 2009-10-28

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