WO2009023298A1

WO2009023298A1 - Method and system for factor graph soft-decision decoding of error correcting codes

Info

Publication number: WO2009023298A1
Application number: PCT/US2008/059873
Authority: WO
Inventors: Kambiz Homayounfar; Yongmei Wei
Original assignee: Phybit Pte. Ltd.
Priority date: 2008-04-10
Filing date: 2008-04-10
Publication date: 2009-02-19

Abstract

Method and system for a data decoder for iteratively decoding data received from a communication channel are provided. The decoder is configured to receive the data in the form of a stream of a plurality of bits, divide the bits into two groups, and select a suspicious error bits set from each of the two groups using LLR and syndrome patterns. The decoder is configured to determine a pseudo random permutation in each iteration using the selected suspicious error bits set, generate a parity check matrix Hb having n columns and n-k rows with augmented cycle-free subgraphs using the determined permutation, and decode the received data using generated parity check matrix Hb. A method and communication system for decoding error correcting encoded data are also provided.

Description

METHOD AND SYSTEM FOR FACTOR GRAPH SOFT-DECISION DECODING OF ERROR CORRECTING

CODES

BACKGROUND OF THE INVENTION

[0001] This invention relates generally to decoding of error-correcting codes and, more particularly, to iterative soft decision decoding of, for example, Reed-Solomon codes based on a factor graph framework.

[0002] Reed-Solomon (R-S) codes are widely used in a variety of commercial applications, most prominently in data storage systems such as CDs and DVDs, in data transmission technologies such as DSL & WiMAX, and in broadcast systems such as DVB and ATSC. In most of the current existing systems, RS codes are usually decoded via hard decision decoding (HDD) which can correct up to half of the minimum distance efficiently using algorithms such as the Berlckamp-Massey (BM) algorithm. Recently, research interest in developing soft-decision decoding (SDD) for R-S codes has increased. The reasons are two-folded. Firstly, optimal SDD normally provides a performance gain compared to the HDD. For example, a performance gain of about 1 -2 dB can be achieved for an additive white Gaussian noise (AWGN) channel and even more can be achieved for Rayleigh channel. Secondly, soft-decision decoding can yield soft output which is desired for certain applications such as turbo equalization. Turbo equalization is an iterative equalization and decoding technique that can achieve equally impressive performance gains for communication systems that send digital data over channels that require equalization, i.e. those which suffer from intersymbol interference (ISI).

[0003] There arc three major directions for soft-decision decoding of R-S. A first direction is the algebraic soft-decision based method (the Koetter-Vardy (KV) algorithm), which utilizes interpolation and factorization of polynomials defined in Galois-Field (GF) to achieve a list of codeword candidates. The codeword finally obtained from KV algorithm is the one among the list which minimizes the distance with the hard decision of the received vector. Because the parity check matrix in GF can be mapped into its binary image, the R-S code can be considered as the linear block code and the general decoding algorithm for linear block code can be applied. Generally, the decoding algorithms for linear block codes fall into two categories which are non-iterative decoder and iterative decoder.

[0004] The second direction of soft-decision decoding for R-S code is the non-iterative decoder for general linear block code, such as ordered statistics decoding and the box and matrix algorithm. Recently, iterative decoding algorithms, which is the third direction, are of emerging interest. One of the most popular iterative decoding algorithms is the sum-product algorithm, which uses the factor- graph framework. The sum-product algorithm works well only when the parity check matrix is sparse because the corresponding graph is free of short girth cycles. Unfortunately, the corresponding binary parity check matrix of R-S codes belongs to high density parity check matrix with highly cyclic graphs and the sura-product algorithm cannot be directly applied for decoding R-S codes. One method, by Jiang and Naraynan, (the J-N algorithm) adapts the parity check matrix in each iteration. After the adaptation, the cycles in the graph involved with a certain set of bits are removed through systematizing the corresponding sub-matrix using Gaussian elimination. The bits are selected solely based on the absolute values of their log likelihood ratios (LLR). A significant improvement in terms of word error rates (WER) is achieved because of the removal of the cycles.

[0005] However, the J-N method sometimes fails at a pseudo-equilibrium codeword or does not converge when there are loops between incorrect bits with high absolute values of LLR and those with low absolute values of LLR. Such loops are destructive because they often involve more than one incorrect bit, these incorrect bits reinforce each other during each iteration and resist the efforts of the algorithm to correct them. This results in an error floor at a relatively high Eb/N{). To reduce the error floor, HDD algorithms are incorporated in each iteration to guarantee the performance at any E_b/N₀. Adding HDD algorithms increases both the computational complexity, and the difficulty in hardware design because the hardware is required to be optimized for two totally different kinds of algorithms. BRIEF DESCRIPTION OF THE INVENTION

[0006] In one embodiment, an iterative decoder for decoding data received from a communication channel is configured to receive the data in the form of a stream of a plurality of bits, divide the bits into two groups, and select a suspicious eiTor bits set from each of the two groups using log likelihood ratios (LLR) and syndrome patterns. The decoder is configured to determine a pseudo random permutation in each iteration using the selected suspicious error bits set, generate a parity check matrix H_b having n columns and n-k rows with augmented cycle-free subgraphs using the determined permutation, and iteratively decode the received data using generated parity check matrix H_b.

[0007] In another embodiment, a method of iteratively decoding error correcting encoded data includes receiving the data in the form of a stream of a plurality of bits, dividing the bits into at least two groups, and determining a set of suspicious error bits from the two groups using LLR and syndrome patterns. The method further includes determining a pseudo random permutation in each iteration using the suspicious error bits selected from the determined set, generating a parity check matrix H_b having n columns and n-k rows with augmented cycle-free subgraphs using the determined permutation, and iteratively decoding the received data using generated parity check matrix H_b

[0008] In yet another embodiment, a communication system for iterative soft decision decoding of error correcting encoded data using an adaptive parity check matrix includes a communication channel providing a source of error correcting encoded data and a decoder. The decoder is configured to receive the data in the form of a stream of a plurality of bits, divide the bits into two groups, and select a suspicious error bits set from the two groups using LLR and syndrome patterns. The decoder is further configured to determine a pseudo random permutation in each iteration using the selected suspicious error bits set, generate a parity check matrix H_b having n columns and n-k rows with augmented cycle-free subgraphs using the determined permutation, and iteratively decode the received data using generated parity check matrix II_b. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a representation of an exemplary parity check matrix H for an (N, K) RS code over GF(2^m);

[0010] Figure 2 is a representation of an exemplary parity check matrix H_b with p, = i and the jth bit is an incorrect bit;

[0011] Figure 3 is a graph illustrating a numerical example of the percentage of the codeword at different Et/No, in which there are q incorrect bits not being among the bits with the n-k lowest absolute LLR;

[0012] Figure 4 is a graph illustrating a comparison between the BM method, the J-N method and the methods of embodiments of the present invention in additive white Gaussian noise (AWGN) channel;

[0013] Figure 5 is a graph illustrating a comparison between the BM method, the J-N method and the methods of embodiments of the present invention in Ray lei gh fading channel;

[0014] Figure 6 is a schematic block diagram of an electronic device for extracting Reed Solomon encoded data from a storage device; and

[0015] Figure 7 is a flow chart of an exemplary method of decoding a (n,k) Reed-Solomon code using a pseudo random degree-2 connection algorithm.

DETAILED DESCRIPTION OF THE INVENTION

[0016] The following detailed description illustrates the disclosure by way of example and not by way of limitation. The description clearly enables one skilled in the art to make and use the disclosure, describes several embodiments, adaptations, variations, alternatives, and uses of the disclosure, including what is presently believed to be the best mode of carrying out the disclosure. The disclosure is described as applied to a preferred embodiment, namely, soft decision decoding of Reed-Solomon codes using a factor graph framework. However, it is contemplated that this disclosure has general application to decoding of error-correcting codes in industrial, commercial, and residential applications.

[0017] As used herein, an element or step recited in the singular and proceeded with the word "a" or "an" should be understood as not excluding plural elements or steps, unless such exclusion is explicitly recited. Furthermore, references to "one embodiment" of the present invention are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features.

[0018] In various embodiments of the present invention, a new factor-graph based method removes the cycles between a set of suspicious incorrect bits. In addition to the bits with low absolute values of LLR, the set also includes those in between the suspicious incorrect bits with high absolute values of LLR, These suspicious high reliable bits are selected according to the syndrome patterns. Λs a result, most of the cycles involved with more than one incorrect bits are removed leading to parity check matrix with augmented cycle-free subgraphs. The proposed method eliminates the error floor at high E_t,/N₀ and improves the performance at moderate E_b/N₀. Since extra suspicious incorrect bits besides the unreliable ones have been included in the set which does not involve any loops, two steps in J-N algorithm which are reordering the absolute values of LLR and systematizing the sub-matrix, are removed from the iteration and done only once to reduce the computational complexity without deteriorating the performance. Further more, the performance- complexity tradeoff can be controlled through changing the number of extra selected suspicious bits with high values of LLR.

[0019] Figure 1 is a representation of an exemplary parity check matrix H for an (N, K) RS code over GF(2^m). In the exemplary embodiment, a represents the primitive clement of GF(2^m) and δ = N-K. Because each symbol in GF(2^m) can be represented in m bits, parity check matrix H can be mapped to a binary parity check matrix Hh having n columns and n-k rows with size of (n-k)^χn, where n ^■■-= N *m and k = K.xm. [0020] Let L represent the LLR vector associated with the received vector at the channel output. An embodiment of an adaptive parity check matrix based algorithm is described below in Table 1. This algorithm is comprised of two major steps, an adaptation of the parity check matrix H_b and an implementation of the sum-product algorithm to update the LLR vector.

Table 1

Input: Parity check matrix H_b, the maximum number of iterations L_m and LLR vcctor-L for the coded bits from the channel observation.

Step 1 : Initialization; Set η_{l k} ^m = 0 for all (/, k) with H_b(i, k) = 1. Set λ_k ^m =L(k). Set the loop counter I=I .

Step 2: Parity check matrix adaptation:

(a) Order the coded bits according to the absolute values of

^{iV i^}-

(b) Implement Gaussian elimination to systematize the (n-k) columns of Hb which is associated with the (n-k) unreliable bits.

(c) Implement degree-2 connection algorithm

1) Generate a random permutation of numbers from 1 to n-k, which are pi, p_2j...p_n-k

2) Add p,₊i^lh row to pi^tlη row for I=I to n-k-1 Step 3 : Sum-product decoding algorithm

(a) Check node update: For each (i, k) with Hφ,k) ™ /: Compute

^^[/J = -2tanh-( πtanh(- ' ⁷" ^{' >}—))

(b) Bit node update: For k=l , 2,...,n: Compute λ_k ^[l] = L(k) + ∑η_ιΛ ^[\ where icφ_{tj k} Ψ,, _k represents the collection of the row indices at which the values of H_b are nonzero for kth column, and φ_{t m} refers to the collection of the column indices at which the values of H_b are nonzero for zth row.

(c) Make a tentative decision: Set c_k = 1 if /L_A' ' > 0 , else set c_k = 0. If H_b^ = 0, stop. Otherwise, if l<L_m, set /=/+1 , go back to Step 2 for another iteration.

[0021 ] The sum-product algorithm fails mainly due to the existence of loops in the graph determined by the parity check matrix Hb. Through systematizing the columns of H_b associated with the n-k lowest absolute LLR values using Gaussian elimination in (b) of step 2, the loops involved with (n-k) unreliable bits are removed. To overcome the drawback that the unreliable bits receive too little extrinsic information from the checks, dcgree-2 random connection algorithm is applied after Gaussian elimination at each iteration as shown in (c) of step 2.

CYCLES IN THE GRAPH INVOLVING MORE THAN ONE INCORRECT BITS

[0022] Figure 2 is a representation of an exemplary parity check matrix Hh with p, = i and the jth bit is an incorrect bit. The sum-product algorithm (ails mainly due to the existence of loops determined by the parity check matrix H_b. The problem is more severe when more than one incorrect bit is involved in a loop. For example, if there are two incorrect bits within one loop and all other bits involved with the same checks are correct, the sign of η_{ι k} are always wrong and the LLR moves towards the wrong direction in each iteration. In this case, both of the two incorrect bits enforce each other and themselves in the wrong direction, which leads to decoding failure. Thus, it is important to remove the loops involving more than one incorrect bit.

[0023] However, the existing adaptive parity check matrix based iterative method removes a portion of such loops through systematizing the sub- matrix involved with the unreliable bits. When there are incorrect bits with high reliabilities, however, the existing method without removing any loops involved with these incorrect bits, even creates loops in between the unreliable bits and these incorrect bits. This is because the step of adding p ,₊/^h row to p ,"' row in the step 2 of Table 1 results in the existence of two ones in one column and loops are introduced if the values of the parity check matrix at the corresponding two rows associated with the incorrect bits arc both ones. Figure 2 illustrates an example with p, = / and the cycles in between the ith and jtli bit. Such a scenario happens often for R-S code with high code rate because the column weights of the binary parity check matrix is high. For example, the column weights for (204, 188) R-S code is around 54 to 64 with n- k-128. In this case, the existing algorithm fails to converge to the correct codeword.

[0024] Figure 3 is a graph illustrating the percentage among 5320 R-S codewords containing q incorrect bits not belonging to the (n-k) most reliable bits at different E_t/No,. Figure 3 facilitates a better understanding of the existence of incorrect bits with high absolute values of LLR. Generally, the percentage increases with the decreasing of E_t/No. More importantly, there always exist at least one incorrect bit with high absolute LLR for all E_t/N₀. It is found that there are no R-S codeword containing more than two incorrect bits with high absolute LLR above Eb/N₀- -5.7dB. A new adaptive parity check matrix algorithm with augmented cycle- free subgraph to remove a]1 the loops in between unreliable and reliable incorrect bits is described.

ADAPTIVE PARITY CHECK MATRIX WITH AUGMENTED CYCLE-FREE GRAPHS

[0025] If it is defined that the set of suspicious hard-decision error bits (SHDD-EB) is the set of bits whose reliabilities yields hard-decision errors. The pseudo random degree-2 connection algorithm creates a new parity check matrix that avoid loops between all SHDD-EB at each iteration. The algorithm generally includes two steps. The first step is to determine the SHDD-EB and the second step is to make the pseudorandom dcgree-2 connection.

DETERMINING THE SHDD-EB

[0026] After reordering all the bits with the ascending order of LLR, the bits arc divided into two groups. The first group is the (n-k) bits which have relative low absolute values of LLR. The second group is the remaining k bits which have relative high absolute values of LLR. The SHDD-EB is selected within each group. Firstly, all the (n-k) bits in the first group are included in the SIIDD-EB because the bits yielding the lower reliabilities have higher chances of being the incorrect bits. Secondly, a maximum of q bits which have the highest probabilities of being the incorrect bits are selected among the second group, where q represents the number of bits selected from the second group. These q bits are selected based on maximizing the correlation between the modulus-2 summation of the corresponding columns of H_b and syndrome vector. When q = 1, the bit is selected according to

/= argmax, ((H_Λ-v)'-A,) (1)

where y is the hard-decision of the LLR vector in each iteration and h, is the /th column of Hi₇.

[0027] When q =2, there arc possibilities that either one or two bits are selected from the second group according to

(^fl _oΛ , α, A ) = arg max_α ^ ((H _b ^■ y)^{' ■} ((a_oh , ) θ (a,h_k ))). (2)

where ^αo and ^a\ arc both either 1 or 0 determining whether /o and h are selected respectively (1 means selected).

PSEUDO-RANDOM DEGREE-2 CONNECTION

[0028] In this step, a pseudo-random permutation is determined to avoid introducing loops between the first-group SHDD-EB from the second group SHDD-EB. Then, each row of parity check matrix H₁, is added to its previous row to form a new parity check matrix.

[0029] To avoid the loops between the first-group SHDD-EB and the second group SHDD-EB, no patterns { 1 , 0, 1 } or {0, 1, 0} should exist in the yth column after the permutation if it is assumed that they^'th column corresponds to the suspicious incorrect bits with high absolute values of LLR as shown in Figure 2. If there arc patterns similar to { 1, 0, 1 } existing in theyth column, after adding P,₊/'¹ row to p,^th row as shown in Step 2 (Table 1 ), the parity check matrix will have loops between the suspicious incorrect bits.

[0030] To achieve the desired permutation, every possible peπnutation may be tried and the permutations that do not satisfy the above mentioned requirements may be discarded until a qualified permutation is found. However, such methods are computationally costly. In the exemplary embodiment, to simplify the computation, the following methods may be used for cases q=l and q=2. Additionally, this method can be extended to q=log? (n-k).

When One Bit In The Second Group Of SHDD-EB Is Selected

[0031] If it is assumed that the /th bit is the selected bit among the second group SlIDD-EB, the details of pseudo-random dcgree-2 connection are shown in the following first case:

[0032] Step 1 : Order the rows of the parity check matrix H_b following the rules that the values of Ir₁ is in a descending order, which defines a permutation ti, t₂,..., t_n-k. Suppose that the first row of hy being 0 is the t,th row.

[0033] Step 2. Randomly select a number r₀ from 2 to r-1 and another number ri from r to n-k-2. Switch rows from t_ro to t,.i with rows from t_ro to t, i, which defines the second permutation pi, p₂, ..., p_π-ι_<.

[0034] Step 3. Add p,+ith row to p,th row, for i =1 to n-k-1.

[0035] Step 1 guarantees non-existence of patterns like { 1, 0, 1 } or {0, 1, 0} . Step 2 introduces randomness and guarantees the bits among the second group, SHDD-EB receive extrinsic information from two instead of one check. The randomness is helpful in the sense that the different checks are involved in providing different correction information in each iteration. This facilitates avoiding that the algorithm fails if there are incorrect bits associated with the check information.

When Two Bits In The Second Group Of SHDD-EB Arc Selected [0036] If it is assumed that /_oth and /_/th bits arc the selected bits among the second-group SHDD-EB, the steps of pseudo-random degree-2 connection are shown in the following second case:

[0037] Step 1 : Reorder the rows of the parity check matrix Hb following the rules that the values of h_J0 is in a descending order, which defines a permutation ti. I₂ ,..., t_n__k. Suppose that the first row of h_j0 being zero is the t_rth row.

[0038] Step 2: Reorder the rows ti. t₂ ,..., t_r_ι of the parity check matrix H_b following the rules that the values of h_{j t} for these rows are in a descending order, which defines another permutation t' i . t'₂ ,..., t\ and suppose that the first row of h_j, being 0 is the t\oth row.

[0039] Step 3: Reorder rows t_r. t,+ι ,..., t_n._L of the parity check matrix H_b following the rules that the values of h, i for these rows are in an ascending order, which defines the third permutation and suppose that the first row of h,ι being 1 is the k|th row.

[0040] Step 4: Randomly select a number ro from max (2, ko) to r- 1 and another number π from r to n-k-max (2, n-k- ko). Switch rows from ro to r-1 with rows from r to ri, which defined the last permutation pi, p₂, ..., p_n-k-

[0041] Step 5: Add p,₊|th row to p,th row, for i =1 to n-k-1

[0042] For the second case, step 1 and step 5 are exactly the same as step 1 and step 3 for the first case. Step 1 guarantees the non-existence of patterns {1,

0, J ] or {⁽⁾, I, 0} in the ,/oth column and Steps 2 and 3 guarantee that there are no such patterns introduced in the ./i th row without introducing the patterns in the Vn th column. Step 4 in the second case has the same functionality as that of the step 2 in the first case.

SIMPLIFIED ADAPTIVE PARITY CHECK MATRIX BASED DECODING WITH PSEUDO-RANDOM DEGREE-2 CONNECTION ALGORITHM [0043] For the methods of embodiments of the present invention, extra suspicious incorrect bits are added to the set with the cycle-free sub-graph. The number of the incorrect bits with high absolute values of LLR is generally below 2 as shown in Figure 3. Therefore, the in the exemplary embodiment, a simplified algorithm removes these two procedures from each iteration to reduce the computational complexity. The details of this simplified algorithm are shown below in Table 2.

Table 2

Input: Parity check matrix H_b, the maximum number of iterations Lm and LLR vector-L for the coded bits from the channel observation.

Step 1 : Initialization: Set η_{l k} ^]0] = 0 for all (i, k) with H_b(i, k) = I. Set λ_k ^w ~L(k). Set the loop counter /=1.

Step 2: Parity check matrix adaptation:

(a) Order the coded bits according to the absolute values of

Step 3: Parity check matrix adaptation through pseudo-random degrcc- 2 connection algorithm

(a) Finding SHDD-SB according to eq (2).

(b) Pseudo random dcgree-2 connection algorithm. Step 4: Sum-product decoding algorithm

(a) Check node update: For each (/, k) with H_b(i,k) = 1: Compute

(b) Bit node update: For k=l, 2,..., n: Compute Λ_A'" = /W + ∑77,_,Λ where

φ_{n k} represents the collection of the row indices at which the values of H_b are nonzero for AIh column, and φ_{t m} refers to the collection of the column indices at which the values of H_b arc nonzero for /th row.

(c) Make a tentative decision: Set c_k - \ if λ_k ^U] > 0, else set c_k - 0. If H_bc_A - 0 , stop. Otherwise, if KL₁₁₁, set /=/+1 , go back to Step 3 for another iteration.

THE COMPUTATIONAL COMPLEXITY AND SIMULATION RESULTS

[0044] In addition to the computational cost for the traditional sum- product algorithm, the extra costs for the methods of embodiments of the present invention with q - 1 described in Table 2 and the J-N algorithm arc compared in Table 3 below. It is estimated that the maximum iteration is L_n, and the column weight is half of the total row number. In the step of pseudo random degree-2 connection of the method of embodiments of the present invention (or degrce-2 connection algorithm of the J-N algorithm), the computational cost for the permutations is trivial because only the final permuted indices are recorded instead of time-consuming data movements. For the method of embodiments of the present invention, compared with the J-N algorithm, sorting of LLR vector and Gaussian elimination are implemented only once before the iteration begins and the extra cost is from computing cq (1) in the step of detennining SHDD-SB. If it is estimated that a 'swap' operation requires three cycles and the remaining operations all require a single cycle, the total cycles for the proposed method and the J-N algorithm are approximately L_1n(Yi -Ic) and L_m(4nlog₂n + (n-k)(4.5n-},5k)), respectively. If L_m=10 and (204, 188) R-S code is used with n=1632 and k~1504, the cycles for the proposed method equals approximately 4,014,080 as compared to the J-N algorithm which equals approximately 7,209,300 for an approximate 44% savings. Another computational feature of the methods of embodiments of the present invention is that computing eq (1 ) can be easily paralleled while Gaussian elimination can not. Table 3 Computational complexity comparison

[0045] Figure 4 is a graph 400 illustrating a comparison between the BM method, the J-N method and the methods of embodiments of the present invention in AWGN channel. Figure 5 is a graph 500 illustrating a comparison between hard decision decoding (HDD), the J-N method and the methods of embodiments of the present invention in Rayleigh fading channel Graph 400 includes an x-axis 402 graduated in units of E_b/N₀ in dB. Graph 400 also includes a y-axis 404 illustrating levels of word error rate (WER) graduated in units of a ratio. Graph 400 shows respective traces 406, 408, 410, and 412 for the BM method, the J-N method and Method 1 and Method 2 in accordance with embodiments of the present invention. Method 1 represents the method described in Table 2 but without the step 2 moving out of the iteration. Method 2 represents the method of the embodiments of the present invention described in Table 2. Graph 500 includes an x-axis 502 graduated in units of E_b/No in dB. Graph 500 also includes a y-axis 504 illustrating levels of word error rate (WER) graduated in units of a ratio. Graph 500 shows respective traces 506, 508, 510, and 512 for hard decision decoding (HDD), the J-N method and Method 2 in accordance with an embodiment of the present invention with q=l and Method 2 in accordance with an embodiment of the present invention with q=2.

[0046] In the simulations, (204, 188) R-S code is used and the modulation employed is 16-State Quadrature Amplitude Modulation (16QAM) because they are widely applied in several standards such as Data Over Cable Service Interface Specifications (DOCSIS), DVB-Sl , DVB-S2, and others. Word error rate (WER) is drawn as a function of E_h/No in Figure 4. For each E_b/No, either 100 word errors are recorded or a total number of 1 ,000,160 information words arc reached. The decoded word is selected according to minimizing the summation of log likelihood ratios of the different decoded bits during each iteration compared with the hard-decision of the received vector. It can be seen that about 0.1 dB performance gain over the J-N method is achieved through using Method 1 at moderate E_b/No between 5.25 and 6.25 dB when q is one, and 0.25dB is achieved when q is two. More importantly, methods 1 and 2 do not show an error floor as that for the J-N method, which is about 5* 10^"6 when E_b/No is between about seven dB to eight dB. In addition, the difference between the performances of Method 1 and Method 2 is relatively small when q is one and the same when q is two. This means that similar performances are achieved with less computational complexity. For the Rayleigh channel, similar results are observed. Only Method 2 is shown due to its good performance and reduced computational complexity. It can be seen from Figure 5 that an approximate 7dB performance improvement is achieved compared with the BM algorithm and an approximate 0.1-0.5 performance improvement is achieved by the second method with q=l and q=2 compared with the J-N algorithm. More importantly, there are no error-floors for Method 2, which appears between approximately nine and ten dB for the J-N algorithm. [0047J Embodiments of the present invention describe a computationally efficient iterative soft-decision decoding algorithm for decoding R-S code. It is based on adapting the parity check matrix in each iteration. Compared with the existing adaptive parity check matrix based J-N algorithm, the embodiments of the present invention remove loops not only between the bits with low absolute values of LLR, but also between the suspicious incorrect bits with high absolute values of LLR. As a result, the performance in terms of WER is improved and the eiTor floor at high E_b/No is reduced.

[0048] Figure 6 is a schematic block diagram of an electronic device 600 for extracting Reed Solomon encoded data from, for example, a storage device 602. Electronic device 600 includes a reading device 604 for reading Reed Solomon encoded data from storage device 602 and a decoder 606 communicatively coupled to an output 508 of reading device 604 for decoding the Reed Solomon encoded data read by reading device 604. An output 610 for converting the decoded data to, for example, audio and/or video signals is communicatively coupled to decoder 606. The operation of reading device 604, Reed Solomon decoder 506, and output 610 is controlled by a processor 612 which also controls a user interface 614.

[0049] The term processor, as used herein, refers to central processing units, microprocessors, microcontrollers, reduced instruction set circuits (RISC), application specific integrated circuits (ASIC), logic circuits, and any other circuit or processor capable of executing the functions described herein.

[0050] As used herein, the terms "software" and "firmware" are interchangeable, and include any computer program stored in memory for execution by processor 612, including RAM memory, ROM memory, EPROM memory, EEPROM memory, and non-volatile RAM (NVRAM) memory. The above memory types are exemplary only, and are thus not limiting as to the types of memory usable for storage of a computer program.

[0051] As will be appreciated based on the foregoing specification, the above-described embodiments of the disclosure may be implemented using computer programming or engineering techniques including computer software, firmware, hardware or any combination or subset thereof, wherein the technical effect is for soft decision decoding of Reed-Solomon codes using an adaptive parity check matrix. Any such resulting program, having computer-readable code means, may be embodied or provided within one or more computer-readable media, thereby making a computer program product, i.e., an article of manufacture, according to the discussed embodiments of the disclosure. The computer readable media may be, for example, but is not limited to, a fixed (hard) drive, diskette, optical disk, magnetic tape, semiconductor memory such as read-only memory (ROM), and/or any transmitting/receiving medium such as the Internet or other communication network or link. The article of manufacture containing the computer code may be made and/or used by executing the code directly from one medium, by copying the code from one medium to another medium, or by transmitting the code over a network.

[0052] Figure 7 is a flow chart of a method 700 of itcratively decoding error correcting encoded data in accordance with an exemplary embodiment of the present invention. In the exemplary embodiment, method 700 includes receiving 702 the data in the form of a stream of a plurality of bits, dividing 704 the bits into at least two groups, and determining a set of suspicious error bits from the two groups using LLR and syndrome patterns. Method 700 also includes determining a pscudo random permutation in each iteration using the suspicious error bits selected from the determined set, generating a parity check matrix H_b having n columns and n- k rows with augmented cycle-free subgraphs using the determined permutation, and iteratively decoding the received data using generated parity check matrix H_b.

[0053] The above-described embodiments of a method and system for soft decision decoding of Reed-Solomon codes using an adaptive parity check matrix provides a cost-effective and reliable means for determining correct data from data containing errors and error-checking codewords. More specifically, the methods and systems described herein facilitate determining a correct codeword when incorrect bits are associated with high reliabilities. In addition, the above-described methods and systems facilitate a decoding algorithm that avoids loops between all the suspicious incorrect bits regardless of their reliabilities. Furthermore, a simplified method, which removes the steps of reordering log likelihood ratio (LLR) and systematization for the sub-matrix from each iteration achieves similar performance improvement with reduced computational complexity. As a result, the methods and apparatus described herein facilitate decoding Reed-Solomon codes in a cost-effective and reliable manner.

[0054] While the disclosure has been described in tcπns of various specific embodiments, it will be recognized that the disclosure can be practiced with modification within the spirit and scope of the claims.

Claims

WHAT IS CLAIMED IS:

1. A data decoder for iteratively decoding data received from a communication channel, said decoder is configured to:

receive the data in the form of a stream of a plurality of bits;

divide the bits into two groups;

select a suspicious error bits set from the two groups using LLR and syndrome patterns in each iteration;

determine a pseudo random permutation using the selected suspicious error bits set in each iteration;

generate a parity check matrix H_b having n columns and n-k rows with augmented cycle-free subgraphs using the determined permutation; and

iteratively decode the received data using generated parity check matrix Hi,.

2. A decoder in accordance with Claim 1 further configured to reorder the bits in an ascending order of LLR.

3. A decoder in accordance with Claim 1 further configured to divide the bits into at least one of a first group of (n-k) bits, which have relatively low absolute values of LLR and a second group of k bits, which have relatively high absolute values of LLR.

4. A decoder in accordance with Claim 1 further configured to select (n-k) bits in a first of the two groups based on the (n-k) bits yielding lower reliabilities having greater probabilities of being incorrect bits,

5. A decoder in accordance with Claim 1 further configured to select a maximum of q bits which have the highest probabilities of being the incorrect bits from a second of the two groups, the q bits being selected based on maximizing a correlation between a modulus-2 summation of corresponding columns of H_b and a syndrome vector.

6. A decoder in accordance with Claim 1 further configured to determine the pscudo random permutation such that loops between the groups of suspicious error bits are facilitated being avoided.

7. A decoder in accordance with Claim 1 further configured to select one bit from a second of the two groups in accordance with:

J-- argmaxj ((HVjy)'-Λ,), where y represents the hard-decision of the LLR vector in each iteration, and h, is the fth column of Hi,.

8. A decoder in accordance with Claim 1 further configured to add each row of the parity check matrix H_b to a previous row of the parity check matrix Hb to form a new parity check matrix.

9. A decoder in accordance with Claim 1 further configured to:

order the rows of the parity check matrix H_b such that the values of h, are in a descending order, which defines a permutation ti, t₂,..., t_n__k;

randomly select a number r₀ from 2 to r-1 and another number ri from r to n-k-2;

switch rows from t,o to t,_i with rows from t_ro to t,i, which defines a second permutation ρ_u ρ₂, ..., p_n__k; and

add pi₊i th row to pith row, for i =1 to n-k-1.

10. A decoder in accordance with Claim 1 further configured to select two bits from a second of the two groups in accordance with: K /o . <hh ) = a^rs ^maχ, *.„„ _*, ((#* ^• y) ^• (M , ) © 0*Λ )))^{■ whcre}

^o and ^a\ are both either 1 or 0 determining whether /o and h are selected respectively wherein 1 indicates selected.

1 1 . Λ decoder in accordance with Claim 1 further configured to add each row of the parity check matrix H_h to a previous row of the parity check matrix H_b to form a new parity check matrix.

12. A decoder in accordance with Claim 1 further configured to:

reorder the rows of the parity check matrix H_h following the rules that the values of h_J0 is in a descending order, which defines a first permutation tj . I₂ ,..., t_n-_k wherein the first row of h_jo being zero is the t,^lh row.

reorder the rows ti. X₂ ,..., t,_] of the parity check matrix H_b following the rules that the values of h_ji for the reordered rows are in a descending order, which defines a second permutation tV t'₂ ,..., t\ and wherein the first row of h,i being 0 is

reorder rows t,. t,₊₁ ,. . ., t_n__k of the parity check matrix H_b following the rules that the values of h_ji for these rows are in an ascending order, which defines a third permutation and wherein the first row of h,i being 1 is the kith row.

randomly select a number r₀ from max (2, ko) to r-1 and another number η from r to n-k-max (2, n-k- ko);

switch rows from ro to r-1 with rows from r to η, which defines a fourth permutation pi, ρ₂, ..., p_n._k", and

add pi₊ith row to p,th row, for i =1 to n-k-1.

13. A method of iteratively decoding error correcting encoded data, said method comprising:

receiving the data in the form of a stream of a plurality of bits dividing the bits into at least two groups;

determining a set of suspicious error bits from the two groups using an LLR and syndrome patterns in each iteration;

determining a pseudo random permutation using the suspicious error bits selected from the determined set in each iteration;

generating a parity check matrix H^ having n columns and n-k rows with augmented cycle-free subgraphs using the determined permutation; and

itcratively decoding the received data using generated parity check matrix H_b.

14. A method in accordance with Claim 13 wherein determining a set of suspicious error bits comprises determining a set of bits whose reliabilities yields hard-decision errors.

15. A method in accordance with Claim 13 wherein dividing the bits into at least two groups comprises dividing the bits into at least a first group in which the bits have relatively low absolute values of log likelihood ratio LLR and a second group in which the bits have relatively high absolute values of LLR.

16. A method in accordance with Claim 15 wherein dividing the bits into at least two groups comprises selecting q bits from the second group wherein the q bits are selected to have the highest probabilities of being the incorrect bits, where q represents the number of bits selected from the second group.

17. A method in accordance with Claim 16 wherein selecting q bits from the second group comprises selecting q bits based on maximizing a correlation between a modulus-2 summation of the corresponding columns of the binary parity check matrix and syndrome vector.

18. A method in accordance with Claim 15 wherein dividing the bits into at least two groups comprises selecting one bit from the second group in accordance with: j- argmax, ((H^-v)'-/?,), where y ^presents the hard-decision of the LLR vector in each iteration, and

It₁ is the 7th column of///,.

19. A method in accordance with Claim 13 wherein determining a pseudo random permutation comprises adding each row of the parity check matrix Hb to a previous row of the parity check matrix H_b to form a new parity check matrix.

20. A method in accordance with Claim 13 wherein determining a pseudo random permutation comprises:

ordering the rows of the parity check matrix H_b such that the values of h, are in a descending order, which defines a permutation ti, t₂,..., t_π-k;

randomly selecting a number ro from 2 to r-1 and another number ri from r to n-k-2;

switching rows from t,o to V₁ with rows from t,o to t, i, which defines a second permutation pi, p₂, ..., ρ_n-k; and

adding p,₊ith row to p,th row, for i =1 to n-k-1.

21. A method in accordance with Claim 13 further comprising selecting two bits from a second of the two groups in accordance with:

K /o '

) = ^ars ^maχ, A „„ „, i(H_b ^• y) ^■ (K^Λ , ) ® ("J¹I, )))• ^whcre ^ai) and ^u\ arc both either 1 or 0 determining whether Jo and Ji are selected respectively wherein 1 indicates selected.

22. A method in accordance with Claim 13 further comprising adding each row of the parity check matrix Hb to a previous row of the parity check matrix H_b to form a new parity check matrix.

23. A method in accordance with Claim 13 further comprising: reordering the rows of the parity check matrix Hb following the rules that the values of h_JO is in a descending order, which defines a first permutation ti . I₂ ,..., t_n-_k wherein the first row of h_jo being zero is the t,^lh row.

reordering the rows tj . t₂ ,..., t,-i of the parity check matrix Hb following the rules that the values of h_ji for the reordered rows are in a descending order, which defines a second permutation t'i. V₂ ,..., t'_r and wherein the first row of h_j] being 0 is the t\_oth row.

reordering rows t,. t_r+ι ,..., t_n-_k of the parity check matrix H_b following the rules that the values of h,i for these rows are in an ascending order, which defines a third permutation and wherein the first row of h_ji being 1 is the kith row,

randomly selecting a number v_{) from max (2, ko) to r-1 and another number η from r to n-k-max (2, n-k- ko);

switching rows from ro to r-1 with rows from r to ij, which defines a fourth permutation p_{l 5} p₂, ..., p_π-_k; and

adding ρ₁₊₁ th row to p,th row, for i =1 to n-k-1.

24. A communication system for soft decision decoding of error correcting encoded data using an adaptive parity check matrix with augmented cycle- free subgraphs, said system comprising:

a communication channel providing a source of error correcting encoded data; and

a decoder that is configured to:

receive the data in the form of a stream of a plurality of bits;

divide the bits into two groups;

select a suspicious error bits set from the two groups using LLR and syndrome patterns in each iteration; determine a pseudo random permutation using the selected suspicious error bits set in each iteration;

decode the received data using generated parity check matrix

25. A system in accordance with Claim 24 wherein said decoder is further configured to reorder the bits in an ascending order of LLR.

26. Λ system in accordance with Claim 24 wherein said decoder is further configured to divide the bits into at least one of a first group of (n-k) bits, which have relatively low absolute values of LLR and a second group of k bits, which have relatively high absolute values of LLR.

27. A system in accordance with Claim 24 wherein said decoder is further configured to select (n-k) bits in a first of the two groups based on the (n-k) bits yielding lower reliabilities having greater probabilities of being incorrect bits.

28. A system in accordance with Claim 24 wherein said decoder is further configured to select a maximum of q bits which have the highest probabilities of being the incorrect bits from a second of the two groups, the q bits being selected based on maximizing a correlation between a modulus-2 summation of corresponding columns of H_b and a syndrome vector.

29. A system in accordance with Claim 24 wherein said decoder is further configured to determine the pseudo random permutation such that loops between the groups of suspicious error bits are facilitated being avoided.

30. A system in accordance with Claim 24 wherein said decoder is further configured to select one bit from a second of the two groups in accordance with:

J= argmax, ((H_/,-yy-h,), where y represents the hard-decision of the LLR vector in each iteration, and h, is the /th column of///,.

31 . A system in accordance with Claim 24 wherein said decoder is further configured to add each row of the parity check matrix H_b to a previous row of the parity check matrix H_b to form a new parity check matrix.

32. A system in accordance with Claim 24 wherein said decoder is further configured to:

order the rows of the parity check matrix H_b such that the values of h, are in a descending order, which defines a permutation ti, t₂,..., W;

randomly select a number ro from 2 to r-1 and another number η from r to n-k-2;

switch rows from t,o to t_r.| with rows from t,o to t_ri, which defines a second permutation pi, p2, ..., p_η-_k; and

add p, ι jth row to p,th row, for i ^■ -1 to n-k-1.

33. A system in accordance with Claim 24 wherein said decoder is further configured to select two bits from a second of the two groups in accordance with:

KAp αji) = ^arg^maχ ₁,t_Λ,«₁ ((^ 7)^' '((VO® (^fliy))' ^where ^ao and ^a] are both either 1 or 0 determining whether Λ and

are selected respectively wherein 1 indicates selected.

34. A system in accordance with Claim 24 wherein said decoder is further configured add each row of the parity check matrix H_b to a previous row of the parity check matrix H_b to form a new parity check matrix.

35. A system in accordance with Claim 24 wherein said decoder is further configured to: reorder the rows of the parity check matrix H_b following the rules that the values of h_J0 is in a descending order, which defines a first permutation t_\. t₂ ,..., t_n_i, wherein the first row of h_j0 being zero is the t,^th row.

reorder the rows ti . t₂ ,..., t_r-i of the parity check matrix H_b following the rules that the values of IT₁ ] for the reordered rows arc in a descending order, which defines a second permutation t' i . t'₂ ,..., t'_r and wherein the first row of h_ji being 0 is the t'_kuth row.

reorder rows t_r. t_r-u ,..., t_n-κ of the parity check matrix H_b following the rules that the values of h_ji for these rows are in an ascending order, which defines a third permutation and wherein the first row of h_ji being 1 is the kith row.

randomly select a number r₀ from max (2, ko) to r-1 and another number r₁ from r to n-k-max (2, n-k- k₀);

switch rows from ro to r-1 with rows from r to η , which defines a fourth permutation pi, p₂, ..., p_n-k; and

add p^ ith row to p,th row, for i =1 to n-k- 1 .