JP2011109228A - Decoding device and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a decoding device and a method for preventing an increase in circuit scale due to an increase in column weight of a parity check matrix, as well as a decrease in error correction capability due to padding or puncture. <P>SOLUTION: An LDPC code decoding device includes: a reception LLR operation unit 520 which computes a reception LLR from a reception signal; a row operation unit 530 which performs row operation for each of a plurality of rows generated by dividing rows of the parity check matrix, by dividing a row operation into a plurality of operations, in the row operation to compute a row LLR from the reception LLR or a column LLR; a column operation unit 540 which computes a column LLR and an estimated bit string from the row LLR; and a repeated operation end determination circuit 550 which alternately repeats the row operation unit and the column operation unit, and ends the repeat when the repeat count reaches a predetermined value or the estimated bit string becomes a code word. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a decoding apparatus and method capable of switching a plurality of low-density parity check codes (hereinafter referred to as LDPC codes) having the same code length and different coding rates.

  When the code length of the error correction code is n and the information sequence length is k, the coding rate is a value represented by k / n. If the coding rate is large, the communication efficiency is high and the error correction capability is low. Conversely, if the coding rate is small, the communication efficiency is low and the error correction capability is high. That is, it is important to set the coding rate to an appropriate value according to the communication system using the error correction code. In some communication systems, error correction codes with different coding rates are provided in communication devices, and error correction codes with appropriate coding rates can be obtained by switching them according to the conditions of the communication channel. I use it.

  The LDPC code is an error correction code defined by a parity check matrix in which one element is sparse (exists at a small ratio with respect to the total number of elements). The number of columns n of the parity check matrix corresponds to the code length, and the number of rows m corresponds to the number of check bits (parity bits). The number of 1s included in a column of the parity check matrix is called the column weight of the column, and the column weight distribution for all the columns is called the column weight distribution. Although the column weight distribution greatly affects the error correction capability of the LDPC code, the optimum column weight distribution can be calculated by a density evolution method or the like. Similarly, the number of 1 included in a row is called a row weight. Further, when the parity check matrix is expressed by a bipartite graph called a Tanner graph, the error correction capability of the LDPC code is higher as the length (girth) of the shortest loop included in the Tanner graph is larger.

  When a communication apparatus with a variable coding rate is configured using an LDPC code, a parity check matrix is required for each variable coding rate. In the LDPC code, the parity check matrix must be different when the coding rate is different, and the encoding operation and the decoding operation depend on the parity check matrix. That is, when LDPC codes having a plurality of coding rates are mounted on one communication apparatus, it is necessary to prepare encoders and decoders that differ by the number of mounted coding rates.

  As a method for solving the above problem, a rate-compatible LDPC code (hereinafter referred to as RC-LDPC code) has been developed (see, for example, Patent Document 1). In the RC-LDPC code, the parity check matrix of the LDPC code having a smaller coding rate among the coding rates to be varied is configured to be a partial matrix of the parity check matrix of the LDPC code having a larger coding rate. ing. That is, the parity check matrix has a common part between different coding rates that are variable, and the decoding apparatus can be efficiently configured. However, it is difficult to configure the RC-LDPC code so that the column weight distribution is close to the optimum value at all variable coding rates and the shortest loop length of the Tanner graph is increased. Since the column weight increases as the rate increases, the problem is that the amount of decoding operation at a high coding rate is large. Furthermore, in order to configure an efficient encoder, it is necessary to design the code length of the LDPC code to be longer as the coding rate is larger, and the code length cannot be made constant between different coding rates. was there.

  Other methods for changing the coding rate include padding and puncturing. In the padding, a part of information bits is fixed to a predetermined value (for example, 0) and encoded at the time of transmission, and the information side is decoded as a known value on the receiving side. Only the information sequence length can be reduced, and the coding rate can be reduced. Puncturing is a technique for reducing the parity bit length by not transmitting a part of the parity bits at the time of transmission, and the parity bit that has not been transmitted on the receiving side is treated as an unknown bit and decoded. Since only the parity bit length is reduced in puncturing, the code rate is increased. In the communication system, a variable coding rate can be realized with a relatively small increase in circuit scale by installing a switching function for applying or not applying these methods. However, LDPC codes configured by these methods have a smaller error correction capability than LDPC codes having the same coding rate. In addition, due to the nature of the method, the code length varies depending on the coding rate.

  By applying padding or puncture to the RC-LDPC code, it is possible to configure a variable coding rate LDPC code having a constant code length. However, as described above, the RC-LDPC code The problem was the large amount of computation itself and a decrease in error correction capability due to padding and puncturing.

  Next, an LDPC code decoding method will be described. A widely used message passing decoding method is composed of two operations called a column operation and a row operation, and an estimated bit is calculated by alternately repeating these operations. Among such decoding methods, the representative is the Sum-product decoding method, but the calculation amount of row calculation is large. Therefore, a decoding method that simplifies the row operation has been proposed, for example, a Min-sum decoding method.

  The column operation and row operation of the decoding method described above are operations corresponding to the columns and rows of the parity check matrix, respectively. The row operation outputs a row LLR with a received log-likelihood ratio (Log-Likelihood Ratio; hereinafter referred to as LLR) representing the reliability of each bit as an input. The column operation receives a row LLR and outputs a column LLR. As described above, the column operation and the row operation are alternately repeated. However, in the second and subsequent row operations, the column LLR output by the column operation is input and the row LLR is output.

Next, the row operation of the Sum-product decoding method will be described in detail. First, in the r-th row of the parity check matrix, a set of column numbers having a matrix element of 1 is set as N (r). Expression (1) shown below is a row operation corresponding to the r-th row, and represents that the column LLRε _{r, c} is calculated from the row LLR (repeated first reception LLR) Z _{r, c} . In equation (1), c represents a column number included in N (r), and N (r) \ {c} is a set obtained by removing c from N (r). In the row arithmetic operation, it is necessary to calculate the epsilon _{r, c} for each c, the number of elements N (r), ie column LLRipushiron _r the number of row degree of r-th _row, to calculate the _c Become.

  In addition, the definition of the operation symbol and function of Formula (1) is as follows.

International Publication No. 07/088870

  A conventional decoding device that can switch between a plurality of LDPC codes having the same code length and different coding rates has a problem of an increase in circuit scale due to an increase in the column weight of the parity check matrix and a decrease in error correction capability due to padding and puncturing. there were.

  The present invention has been made in view of the above points, and an object thereof is to obtain a decoding apparatus and method in which an increase in circuit scale due to an increase in column weight of a parity check matrix and a reduction in error correction capability due to padding or puncturing do not occur. To do.

  The decoding apparatus and method according to the present invention are an LDPC code decoding apparatus and method, and a reception LLR calculation means (step) for calculating a reception LLR from a reception signal, and a row LLR from the reception LLR or column LLR. In the row operation, by dividing the row operation into a plurality of operations, the row operation is performed for each of the plurality of rows generated by dividing the row of the parity check matrix (or the plurality of rows of the parity check matrix are A row operation means (step) for performing a row operation on a row generated by row joining by combining a plurality of row operations on the row before row joining, and a column for calculating a column LLR and an estimated bit string from the row LLR The calculation means (step), the row calculation means and the column calculation means are alternately repeated, and when the prescribed number of times is reached or the estimated bit string becomes a code word Repeat is that a termination repeatedly calculating termination determining means (step) to the case.

  According to the present invention, by performing row division or row combination on the parity check matrix, it is possible to generate a plurality of LDPC codes having the same code length and different coding rates without increasing the column weight, A row operation corresponding to a row before row division or a row before row combination can be performed using a row operation result corresponding to a row after or after row combination, and decoding of each LDPC code is performed with a small circuit scale. In addition, since padding and puncturing are not performed, there is no reduction in error correction capability due to padding or puncturing.

It is based on Embodiment 1 of this invention, and is a figure explaining the row division | segmentation of a parity check matrix. It is a figure which shows the change of the parity check matrix before and behind the row division operation performed in Embodiment 1 of this invention. It is a block diagram which shows an example of the communication system which can be applied to Embodiment 1 of this invention. FIG. 4 is a block diagram showing an internal configuration of a decoder 500 shown in FIG. 3. FIG. 5 is a block diagram showing an internal configuration of a row calculator 530 shown in FIG. 4. It is a block diagram which shows the internal structure of the row calculating part a531 shown in FIG. It is a block diagram which shows the internal structure of the row calculating part b532 shown in FIG. FIG. 10 is a block diagram illustrating an internal configuration in a case where the row operation unit a531 illustrated in FIG. 5 is a row operation unit a531 of the Min-sum decoding method according to the second embodiment of the present invention.

Embodiment 1 FIG.
In the present invention, an LDPC code is handled as an error correction code. The parity check matrix is an m × n matrix having elements 0 and 1. In the first embodiment, the number of rows of the parity check matrix is changed without changing the number of columns by an operation called row division. That is, the coding rate of the LDPC code is varied by changing the number of parity bits while keeping the code length constant.

  As shown in FIG. 1, the row division operation is a method of increasing the number of rows by dividing and arranging 1 included in one row of the parity check matrix into two or more new rows. The coding rate can be varied by preparing one original parity check matrix and switching whether to perform row division. When more than two types of coding rates are variable, a plurality of line divisions are performed, the number of lines increased in each line division is different, and which of these line divisions is used. By switching, the coding rate can be made variable.

  The characteristics of the row division are that the code length is the same before and after the row division, the column weight of each column is the same, and the shortest loop length of the Tanner graph of the parity check matrix is not reduced. One characteristic shows that error correction capability is high even if line division is performed.

  FIG. 2 illustrates changes in the parity check matrix before and after the row division operation performed in the first embodiment. A parity check matrix H2 shown in the lower part of FIG. 2 is an (m + r) × n matrix in which r rows are increased by performing row division on the parity check matrix H1. As shown in FIG. 2, the code length is the same before and after the row division, and the column weights of the columns are also the same. In Embodiment 1, there is no restriction that one line must be divided into two lines, and one line may be divided into any number of lines. Therefore, not only the number of rows to which row division is applied, but also the number of rows r (number of parity bits to be increased) can be set depending on how many rows are divided in each row division. In FIG. 2, the column corresponding to the parity bit among the columns of the parity check matrix is the rightmost m column or m + r column, but this is an example, and the corresponding column of the parity bit common to H1 and H2 Are the same, the configuration of the first embodiment is possible no matter which column the parity bit is associated with.

  In the present invention, a parity check matrix is prepared in advance, and it is determined how to perform row division, and then an LDPC code decoding apparatus capable of changing the coding rate is configured.

  FIG. 3 is an example of a configuration diagram of a communication system to which the present invention can be applied. The transmission-side apparatus includes an encoder 100 that generates a codeword of an error correction code from a transmission bit string, and a modulator 200 that generates a modulation signal based on the codeword. The transmitted signal is received via the communication path 300. The apparatus on the receiving side includes a demodulator 400 that demodulates a received signal, and a decoder 500 that decodes an error correction code based on the demodulated signal.

  In FIG. 3, an encoder 100 generates a parity bit based on a transmission bit string, performs encoding, and calculates a code word. The modulator 200 performs modulation based on the code word, generates a modulated signal using radio waves, light, or an electrical signal by a communication method, and transmits the modulated signal. The transmitted signal is added with noise when passing through the communication path 300 and is received by the receiving device. Demodulator 400 demodulates the received signal and outputs a received signal value for each bit. Decoder 500 performs decoding based on the input received signal value, and outputs an estimated bit string of transmission information calculated as a result.

  FIG. 4 is a block diagram showing an internal configuration of the decoder 500 shown in FIG. The decoder 500 includes an input circuit 510 that controls input, a reception LLR calculator 520 that calculates a reception LLR based on a reception signal value that is an input value, and a row calculation that outputs a row LLR with the reception LLR or column LLR as an input. A calculator 530, a column calculator 540 that calculates a column LLR from the row LLR, a repeat calculation end determination circuit 550 that determines the end of repetition of the row calculation and the column calculation, an output circuit 560 that controls the output of the estimated bit string, And a memory 570 installed inside or outside.

  Next, the operation of the decoder 500 shown in FIG. 4 will be described. The input circuit 510 controls the input of the received signal value, which is an input value, and outputs the received signal value to the reception LLR calculator 520 at an appropriate timing. Since the decoding operation is performed in units of codewords of the LDPC code, n reception signal values having the same number as the code length are output as appropriate at one time or in several times. The unit reception LLR calculator 520 performs different calculations depending on the modulation method or the like, and calculates and outputs a reception LLR from each received signal value.

  The row calculator 530 calculates the row LLR by using the reception LLR input from the reception LLR calculator 520 or the column LLR input from the repeated calculation end determination circuit 7 as an input. The input reception LLR is a value corresponding to each of n columns of the parity check matrix, and is composed of n values. In addition, the column LLR input from the iterative calculation end determination circuit 7 is a value that exists for each column of the parity check matrix by the number of column weights, and is the same as the number of 1 included in the parity check matrix in total. It consists of a value of type. Similarly, there are as many row LLRs as the number of row weights for each row, and the total number of values is the same as the number of 1 included in the parity check matrix.

  The column calculator 540 calculates a column LLR from the row LLR and also calculates an estimated bit string. The repetition calculation end determination circuit 7 determines whether the row calculation and the column calculation have been repeated a predetermined number of times, and outputs the column LLR to the row calculator 530 if the repetition is continued, and outputs the estimated bit string if the repetition is ended. Output to circuit 560. The determination of whether to end the repetition may be performed by performing a parity check on the estimated bit string and determining whether the estimated bit string is a code word. In this embodiment, any repetition end determination criterion can be configured. is there.

  The output circuit 560 outputs the estimated bit string at an appropriate timing. The memory 570 is a storage area used by the arithmetic unit or the circuit. For example, the memory 570 is used for storing the progress of the operation when the row arithmetic unit 530 performs the row operation. Regardless of which arithmetic unit and circuit are used, the first embodiment can be configured, and for the purpose of storing, the first embodiment can be configured in any manner.

  The configuration in FIG. 4 is an example. For example, the column LLR input from the repetition calculation end determination circuit 7 to the row calculation unit may be directly input from the column calculation unit 540, and the estimated bit string is set at the end of the repetition calculation. What is necessary is just to output to the output circuit 560.

  The first embodiment is an invention related to the decoder 500, but portions other than the row arithmetic unit 530 shown in FIG. 4 before and after the row division can be used in common. For example, the column calculator 540 originally needs to have a different configuration according to the parity check matrix, but does not need to be changed when the parity check matrix changes due to row division. This is because the number of columns does not change before and after row division, and the column weight of each column does not change.

  FIG. 5 shows an internal configuration of row arithmetic unit 530 shown in FIG. 4 in the first embodiment. The row computing unit 530 includes a row computing unit a531 and a row computing unit b532. A plurality of row calculation units are provided, and the total number of both is the same as the number of rows of the parity check matrix H1 before row division.

  Each row operation unit performs a row operation corresponding to each row of the parity check matrix H1, calculates a row LLR from the column LLR, and outputs it. There are two types of row operation units in the first embodiment, the row operation unit a531 and the row operation unit b532, and the row operation corresponding to the row subjected to the row division when generating the parity check matrix H2 after the row division is performed. There are a row calculation unit a531 (FIG. 6) to perform, and a row calculation unit b532 (FIG. 7) to perform a row calculation corresponding to a row that has not been subjected to row division, and the corresponding number of rows is installed.

  Next, the row calculation unit a531 corresponding to the row subjected to row division will be described. The row calculation unit a531 in FIG. 6 is installed corresponding to the row (rth row) in the parity check matrix H1 before row division. In this row operation unit a531, the row operation corresponding to the r-th row of the parity check matrix H1 before row division and the row operation corresponding to each of a plurality of rows generated by dividing the r-th row (after row division) The parity check matrix H2) can be switched and output.

  As illustrated in FIG. 6, the row calculation unit a531 includes the input circuit 1, the row LLR calculator a2, the row LLR calculator b3, the row LLR calculator x4 corresponding to the row calculation of each row after row division, and these The row LLR calculator 5 before row division that performs the row calculation of the r-th row before row division using the output of the row LLR calculator, the coding rate switcher 6 that switches the coding rate of the LDPC code, and the row LLR And an output circuit 7 for outputting In FIG. 6, as indicated by the Sleed's 8, the row LLR calculators are installed by the number of rows generated by dividing the row r into rows, and are not limited to the three explicitly shown in the drawing. Specifically, if the r-th row is divided into q rows, q row LLR calculators are installed.

  The input circuit 1 performs input control of the column LLR, etc., and selects the column LLR to be input to the row arithmetic unit a531 in FIG. 6 from among the column LLRs configured by the number of 1 included in the parity check matrix. Output. However, if only the column LLR necessary for the calculation of the row calculation unit a531 is input by the wiring in the decoder or the like, it is necessary to select the column LLR by the input circuit 1 Absent.

  Next, the row LLR calculator will be described. Here, rows a, b,... Are divided by dividing the r-th row of the parity check matrix. . . , X are newly generated, and a set of column numbers of 1 included in each row is represented by Na (r), Nb (r),. . . , Nx (r). Due to the nature of row partitioning, none of these two sets have a common element, and the union of all these sets is N (r) (a set of one column number contained in r rows before row division). ).

Next, the row LLR calculator will be described. Here, the r-th row of the parity check matrix is divided into the row LLR calculator a2, the row LLR calculator b3, and the row LLR calculator x4 in FIG. b, row LLR calculators corresponding to row x. Of these, the formula for calculating the row LLRε _{x, c} calculated by the row LLR computing unit x4 is shown in Equation (6). The right side of equation (6) has a form in which N (r) in equation (1) described in the background art is replaced with Nx (r), where c is a column number included in Nx (r).

  The same applies to the row LLR calculation formulas for the row LLR calculator a2 and the row LLR calculator b3.

  As described above, row operations in the rows a, b, and x of the parity check matrix H2 after the row division can be performed by the row LLR calculator a2, the row LLR calculator b3, and the row LLR calculator x4.

However, in the first embodiment, in order that the row operation before the row division can also be performed by the row operation unit a531, in the row LLR calculator a2, the row LLR calculator b3, and the row LLR calculator x4, the expression (7 Ε _a , ε _b , and ε _x as shown in FIG. However, in equation (7), a calculation formula of ε _x performed by the row LLR calculator x4 is representatively shown.

Expression (7) is obtained by replacing Nx (r) \ {c} in Expression (6) with Nx (r), and the calculation expressions of ε _a and ε _b are the same.

  Note that when performing a row operation corresponding to the parity check matrix H2 after row division, the operation of Equation (7) is not necessary. Therefore, for example, in the coding rate switcher 6 described later, when the parity check matrix H2 after row division is set to be used, the row LLR calculator a2 and the row LLR calculation are performed so as not to perform the calculation of Expression (7). Unit b3 and row LLR calculator x4 may be configured.

  In addition, the product of the function sgn in the first parentheses in the equations (6) and (7) takes only a value of +1 or -1. In addition, the parenthesis operations in the second half never become negative numbers.

  Next, the operation of the row division pre-row LLR calculator 5 will be described. The row LLR calculator 5 before row division performs a row operation corresponding to the row r before the row division, using the calculation results of the equations (6) and (7). The row operation of the row r can be performed by the equation (1), but the set N (r) of the column numbers of 1 included in the row r is converted into the sets Na (r), Nb (r), Nb (r), . . . , Nx (r), the following equation (8) is obtained by substituting N (r) = Na (r) ∪Nb (r) ∪... ∪Nx (r) into equation (1). can get.

  The operation in parentheses in the latter half of the right side of Equation (8) has a property as in Equation (9) below, and the operation order may be arbitrarily changed. Therefore, the Na (r) ｒNb (r) ∪... ∪Nx (r) portion of the formula (8) can be divided as shown in the following formula (10).

  Further, the first parenthesis on the right side of the equation (8) can be divided because it simply calculates the product of the function sgn, and eventually the equation (8) is transformed into the following equation (10). it can. Here, it is assumed that c is included in Na (r) (in this case, as described above, other Nb (r),..., Nx (r) do not include c). .

The expression in each parenthesis on the right side of Expression (10) is the same as the expression in the parentheses on the right side of Expression (6) and Expression (7). Therefore, by substituting ε _{x, c} , εx and the like calculated in Equation (6) and Equation (7) into Equation (10), the following equation (11) can be obtained.

According to Equation (11), the row LLR calculator 5 before row division uses the calculation results of the row LLR calculator a2, the row LLR calculator b3, and the row LLR calculator x4 to perform the row for the row r before row division. This means that the row LLRε _{r, c} to be calculated by calculation can be calculated. However, the case where the column number c is included in Na (r) is shown above. When calculating ε _r, c for each c, N (b),. . . , Nx (r) changes equation (11) depending on which c contains.

  An example of a specific calculation method in the row LLR calculator 5 before row division will be described. First, input values from the row LLR calculator a2, the row LLR calculator b3, and the row LLR calculator x4 are converted into positive and negative signs and absolute values. Divide. Next, if the sign is positive, +1 is assigned, and if it is negative, -1 is assigned to the sgn function of Expression (11), and the absolute value is assigned to the expression in the braces in the latter half of the expression. At this time, the product of the sgn function can be calculated by performing an exclusive OR. For each input value from the row LLR calculator, all exclusive logics are calculated as 0 if positive, 1 if negative, and +1 if the calculation result is 0. Moreover, what is necessary is just to calculate the latter half part of Formula (11) according to the definition formula (4) demonstrated by background art.

  In the above, the value input to the row LLR calculator 5 before row division is first divided into positive and negative signs and absolute values, but the row LLR calculator a2 and the like are configured so as to be input in a divided state. May be.

  It should be noted that the calculation amount of the row calculation for the row r described above (including the calculation amounts of the row LLR calculator a2, the row LLR calculator b3, and the row LLR calculator x4) is the calculation amount of the normal row calculation for the row r. Is equivalent to

  Next, the coding rate switcher 6 will be described. The coding rate switch 6 determines the coding rate of the LDPC code used in the communication system and outputs the information to the output circuit 7. That is, it is determined whether to use the parity check matrix H1 before row division or the parity check matrix H2 after row division. The coding rate is determined in advance, automatically determined according to the state of communication channel noise or the like while synchronizing with the transmission device, or by a changeover switch installed outside the decoder 500, etc. Switch manually or by other means. In addition, as described above, coding rate information is also output to the row LLR computing unit a2, the row LLR computing unit b3, and the row LLR computing unit x4, which may not be necessary depending on the coding rate used in the communication system. These row LLR calculators may not perform this calculation.

  The output circuit 7 receives the row LLR computed by the row LLR computing unit a2, the row LLR computing unit b3 and the row LLR computing unit x4, or the row LLR computing unit 5 before row division, and is determined by the coding rate switching unit 6. In accordance with the coded rate, a row LLR corresponding to either before or after the row division is output.

  Next, the row calculation unit b532 illustrated in FIG. 7 will be described. As described above, the row calculation unit b532 in FIG. 7 corresponds to the row that has not been subjected to row division, and is installed in the row calculator 530 in FIG. 5 by the number of rows that have not been subjected to row division. The row calculation unit b532 includes an input circuit 9, a row LLR calculator 10, and an output circuit 11. The input circuit 9 performs the same operation as that of the row calculation unit a531 in FIG. 6, and the output circuit 11 does not select the output row LLR by switching the coding rate unlike the output circuit 7 in FIG. Other operations are the same. Moreover, the row LLR computing unit 10 in FIG. 7 is a normal row computing unit that computes the row LLR by the equation (1).

  In the above configuration, the two coding rates can be switched according to whether or not row division is performed, but switching of three or more coding rates is also possible with the same approach. For this purpose, row division is further performed on the parity check matrix H2 obtained by dividing the original parity check matrix H1 into rows. Let the parity check matrix generated in this way be H3.

  In order to configure a row computing unit corresponding to H3, a row computing unit other than the row computing units a and b described above is required. This is because it is necessary to cope with the case where the line divided when generating H2 from H1 is further divided when generating H3 from H2. For this purpose, for example, if row x is further divided into rows in FIG. 6, the internal configuration of row LLR calculator x is the same as the portion enclosed by the broken line in FIG. What is necessary is just to comprise the row calculating part which increased the bit width of the output line appropriately. If this new row calculation unit, row calculation unit a531, and row calculation unit b532 are installed in the row calculation unit 530 of FIG. 5 corresponding to the number of corresponding rows, the row calculation unit 530 capable of switching three coding rates. Can be configured.

  As described above, a decoder that can switch between three types of coding rates can be configured. Further, in the same manner that the row operation unit corresponding to three types is configured from the row operation unit corresponding to two types of coding rates, more encoding is performed from the row operation unit corresponding to three types of encoding rates. It is also possible to configure a row arithmetic unit corresponding to the rate. That is, as a row arithmetic unit, by performing a row operation on each parity check matrix that has been subjected to row division a plurality of times, and performing a row operation on the previous row based on the row operation result on the more divided rows It is only necessary to switch the row calculation for each of the plurality of row divisions.

  In the above, the configuration of the decoder in which the coding rate is variable by row division is shown, but a decoder in the case where the coding rate is variable by row combination can be configured by the same configuration. The row combination is an operation opposite to the row division, and is an operation of reducing the number of rows by combining two rows of the parity check matrix into one row. To join two rows, add elements for each column. That is, when the elements of a certain column of the two rows to be joined are 0 and 1, respectively, the element of that column in the joined row is set to 1, and the elements of a certain column are 0, 0, 1 and 1, respectively. In the case of 1, the element of the column in the combined row is set to 0.

  In the row arithmetic unit 530 described above, the parity check matrix not subjected to row combination is regarded as the parity check matrix H2 after row division, and the parity check matrix after row combination is not subjected to row division. If it is configured as the parity check matrix H1, the corresponding row arithmetic unit 530 and decoder 500 can be configured before and after the row combination. The decoder 500 corresponding to three or more coding rates can be configured in the same manner.

  That is, as the row calculator 530, in the row calculation for calculating the row LLR from the received LLR or the column LLR, the row calculation for the row generated by combining the plurality of rows of the parity check matrix is performed. Multiple row operations for rows may be combined, and before and after row combination by performing row operations on the rows after row combination based on the row operation results for the rows before row combination of the parity check matrix. The row operation for each row can be switched, and the row operation for each parity check matrix in which the row combination is performed multiple times is performed on the basis of the row operation result for the row before the row combination. By performing a row operation on, it is possible to switch and perform a row operation on each of a plurality of row combinations.

  However, if the element in the same column in two rows to be combined is 1, the element in that column is 0 after combining, and thus the same configuration as described above is impossible. In this case, a circuit that switches so as not to perform an operation that has become unnecessary due to the row combination is necessary. For example, in the case of the column computing unit 540, it may be invalidated by fixing the input of the row LLR corresponding to the element that becomes 0 by row combination to 0 or the like. Further, the row calculator 530 may calculate the row LLR while ignoring the input of the column LLR corresponding to the element that becomes 0 by the row combination. For example, there is a method of fixing the value of the corresponding column LLR to the maximum value. The increase in circuit scale by adding these functions is small.

  In the above, a decoder capable of switching between an original parity check matrix and a parity check matrix obtained by performing row division or row combination on the parity check matrix has been described. However, the original parity check matrix is not necessarily used in a communication system. There is no need. That is, one of the plurality of parity check matrices generated by performing row division or row combination on the original parity check matrix may be used by switching from one other than the original parity check matrix.

  In addition, if the method of selecting the row to be subjected to row division or row combination is selected so that the deviation of the row weight of the parity check matrix after the row division or after the row combination is reduced, the error correction capability can be increased as compared with the case where the deviation is large . As an example of how to select such a line in the line division, there is a method of preferentially dividing a line having the largest or relatively large line weight and dividing the line into two lines. Further, as an example of how to select a row to be combined, combining rows with small row weights can be mentioned.

  Further, if a row to be divided or combined is selected so that the maximum row weight of the parity check matrix becomes small, a value that depends on the maximum row weight (for example, the bit width of the address indicating the position of 1 included in the row). And the circuit scale such as a memory can be reduced.

  According to the configuration as described above, the row operation before row division can be efficiently performed using the row operation result after row division, and the amount of calculation of the decoder configured according to the parity check matrix before row division and A decoder capable of switching between decoding operations before and after row division can be configured with a calculation amount and circuit scale equivalent to the circuit scale, and an increase in calculation amount and circuit scale can be suppressed. A similar configuration is possible even when row division is performed multiple times, and a plurality of encodings are performed with the same amount of computation and circuit scale as that of a decoder configured according to the parity check matrix before row division. A decoder corresponding to the variable rate can be configured.

  Further, according to the configuration as described above, the row operation after the row combination can be efficiently calculated using the row operation result before the row combination, and the decoder operation configured according to the parity check matrix after the row combination is performed. A decoder capable of switching between decoding operations before and after row combination can be configured with an amount of computation and circuit scale equivalent to the amount and circuit scale, and an increase in the amount of computation and circuit scale can be suppressed. A similar configuration is possible even when row combination is performed multiple times, and a plurality of encodings are performed with an operation amount and circuit scale equivalent to the operation amount and circuit scale of the decoder configured according to the parity check matrix after row combination. A decoder corresponding to the variable rate can be configured.

  The decoder having this configuration has the highest coding rate among LDPC codes having variable coding rates, and has a circuit scale equivalent to that of the decoder corresponding to the parity check matrix having the minimum number of rows. On the other hand, the conventional method for performing variable coding rate by adding a new row to the original parity check matrix requires at least a circuit scale corresponding to the parity check matrix having the largest number of rows in the variable coding rate. It becomes. That is, according to this configuration, the circuit scale can be reduced as compared with the conventional method.

  Also, since LDPC codes having different coding rates are generated by row division or row combination, the column weights of the parity check matrix are constant between different coding rates, and the column weights accompanying the increase in the number of rows of the parity check matrix There is no increase. Therefore, the circuit scale can be reduced. In addition, since the coding rate is kept constant even when line division and line combination are performed, it is not necessary to perform padding or puncturing, and it is possible to avoid a decrease in error correction capability due to performing these.

  Furthermore, according to the above configuration, the coding rate can be changed while keeping the column weight distribution constant, and the LDPC code at each coding rate has a large error correction capability. In addition, since the shortest loop length of the Tanner graph is not reduced by this configuration based on row division, it is possible to easily configure a parity check matrix corresponding to a variable coding rate and extracting high error correction capability. is there.

  The above configuration is not intended to change the coding rate, but to adjust the coding rate of the LDPC code while keeping the code length constant, that is, to adjust the information sequence length and the number of parity bits. Can do. The number of parity bits can be adjusted in 1-bit units without changing the circuit configuration of the decoding device. For example, when the frame format of the communication system is changed or desired to be changed, the number of parity bits and the information sequence length can be used for the purpose of matching the frame format while keeping the code length constant.

Embodiment 2. FIG.
In Embodiment 1, the row operation of Sum-product decoding has been described, but the same possibility is possible even with other decoding methods. For example, this configuration can be applied to a decoding method in which the amount of calculation is reduced by approximating the row operation of the Sum-product decoding method. Among these decoding methods, there is a Min-sum decoding method. This decoding method is obtained by replacing the row operation expression (1) of the Sum-product decoding method shown in the background art with the following expression (12).

If the smallest column number of c ′ is p ′, Equation (12) is

Can be calculated by obtaining the minimum value, the second smallest value, and the value p of the column number c ′ that is the minimum value, and adding the sign of the product of the sgn function. That is, ε _{r, c} is a value obtained by adding a sign to the second minimum value for c = p, and a value obtained by adding a sign to the minimum value for c ≠ p.

  FIG. 8 shows a row calculation unit a531 based on the above calculation method. The row calculation unit a in FIG. 8 has a configuration in which each row LLR calculator in the row calculation unit a in FIG. 6 is replaced with a minimum binary calculation unit. The minimum binary value refers to the minimum value and the second smallest value.

The operation of FIG. 8 will be described. Each of the minimum binary calculators calculates the sign of ε _{r, c} for each column c from the positive and negative signs of the input column LLR, and the column which becomes the minimum binary value and the minimum value of the absolute value of the column LLR The number value p is calculated and output.

  The row LLR calculator 5 before row division performs a row operation corresponding to the row r before row division based on the minimum binary value, p, and sign input from each of the minimum binary calculators. The sign can be calculated in the same manner as in the first embodiment. The minimum binary value in the entire column number of 1 included in the row r can be obtained by calculating the minimum binary value among the minimum binary values input from the minimum binary calculators. In addition, the column number that is the minimum value can also be calculated from among each input p.

  The output circuit 7 selects either the input value from the minimum binary computing unit or the input value from the row LLR computing unit 5 before row division according to the coding rate by the coding rate switching unit, Each row LLR may be output according to p.

  In the above configuration, switching between two coding rates before and after row division has been described. However, a decoder capable of switching between three or more coding rates can be configured in the same manner as in the first embodiment.

  In addition to the Min-sum decoding method, the configuration of the row calculation unit a in FIG. 8 can be configured by a decoding method that obtains the minimum binary value of the column LLR. For example, in the case of Offset BP-based decoding, it is only necessary to add a calculation unit that calculates an offset value from each of the minimum two values. In the case of Normalized BP-based decoding, each of the minimum two values and the normalization factor What is necessary is just to add the arithmetic unit which calculates the product of.

  Further, a similar configuration can be applied to a decoding method that similarly calculates the minimum three values (minimum value, the second smallest value, and the third smallest value). For example, in the cyclic approximation δ-min decoding method, If there is, a minimum ternary calculator is installed instead of the minimum binary calculator of FIG. 8, and the row LLR calculator 5 before row division calculates the minimum ternary value in the input from each of the minimum ternary calculators. What should I do? In this case, it is necessary to add a delta arithmetic unit that calculates a value called a D value and an arithmetic unit that subtracts the D value from each of the minimum three values to the row arithmetic unit in FIG. Furthermore, a configuration similar to that of the present embodiment is possible as long as the decoding method calculates at least four absolute values of the column LLR in a row operation.

  In this way, the row LLR before row division can be calculated efficiently using the calculation result of the row LLR after row division, and the coding rate can be efficiently increased while suppressing the increase in the circuit scale of the row operator. A decoder corresponding to the switching can be configured.

  In addition, if row division is performed so that as many rows as possible with a power of 2 are generated among the rows after the row division, the row LLR arithmetic circuit for a row with a power of 2 is efficiently used. Can be configured. For the calculation of the minimum binary value, the binary comparison is performed the number of times corresponding to the value of the row weight. However, in the case of a configuration like a binary tree (a configuration like a tournament), all values are obtained in all stages. This is because binary comparison is possible (the case where there is no partner for binary comparison does not occur).

  1, 9 input circuit, 2 row LLR computing unit a, 3 row LLR computing unit b, 4 row LLR computing unit x, 5 row previous row LLR computing unit, 6 coding rate switching unit, 7, 11 output circuit, 10 Row arithmetic unit, 12 Minimum binary arithmetic unit a, 13 Minimum binary arithmetic unit b, 14 Minimum binary arithmetic unit x, 100 Encoder, 200 Modulator, 300 Communication path, 400 Demodulator, 500 Decoder, 510 Input circuit, 520 reception LLR arithmetic unit, 530 row arithmetic unit, 531 row arithmetic unit a, 532 row arithmetic unit b, 540 column arithmetic unit, 550 repetition arithmetic end determination circuit, 560 output circuit, 570 memory.

Claims (16)

An LDPC code decoding device comprising:
Received LLR calculating means for calculating received LLR from the received signal;
A row operation for each of a plurality of rows generated by dividing a row of the parity check matrix by dividing the row operation into a plurality of operations in a row operation for calculating a row LLR from the received LLR or the column LLR. A line operation means for performing
Column operation means for calculating a column LLR and an estimated bit string from the row LLR;
A decoding apparatus comprising: an iterative calculation end determining unit that repeats the row calculating unit and the column calculating unit alternately and ends the repetition when a predetermined number of times is reached or an estimated bit string becomes a code word. The decoding device according to claim 1, wherein
As the row operation means, a row operation for each row before and after the row division is performed by performing a row operation on the row before the row division based on a row operation result for the row after the row division of the parity check matrix. A decoding apparatus comprising an arithmetic means. The decoding device according to claim 1, wherein
As the row calculation means, row calculation for each parity check matrix that has been subjected to row division multiple times, based on the row calculation result for the more divided rows, by performing row calculation on the row before being further divided, A decoding apparatus comprising: a row calculation means for switching a row calculation for each of a plurality of row divisions. The decoding device according to claim 2 or 3,
The decoding apparatus according to claim 1, wherein the row calculation means performs a row calculation on each row before and after row division using a minimum binary calculator. An LDPC code decoding device comprising:
Received LLR calculating means for calculating received LLR from the received signal;
In the row operation for calculating the row LLR from the received LLR or the column LLR, the row operation for the row generated by combining the plurality of rows of the parity check matrix is performed, and the plurality of row operations for the row before the row combination are performed. Row arithmetic means to be combined,
Column operation means for calculating a column LLR and an estimated bit string from the row LLR;
The row calculation means and the column calculation means are alternately and repeatedly provided with a repetition calculation end determination means for ending the repetition when a prescribed number of times is reached or an estimated bit string becomes a code word. A decoding device. The decoding device according to claim 5, wherein
As the row operation means, a row operation for each row before and after the row combination is performed by performing a row operation on the row after the row combination based on a row operation result for the row before the row combination of the parity check matrix. A decoding apparatus comprising an arithmetic means. The decoding device according to claim 5, wherein
As the row operation means, by performing a row operation on each of the parity check matrices that have been subjected to row combination a plurality of times, based on a row operation result on the row before the row combination, by performing a row operation on the row that has been combined. A decoding apparatus comprising: row operation means for performing row operation for each of a plurality of row combinations. The decoding device according to claim 6 or 7,
The decoding apparatus according to claim 1, wherein the row calculation means performs a row calculation on each row before and after row combination using a minimum binary calculator. An LDPC code decoding method comprising:
A reception LLR calculation step of calculating a reception LLR from the reception signal;
A row operation for each of a plurality of rows generated by dividing a row of the parity check matrix by dividing the row operation into a plurality of operations in a row operation for calculating a row LLR from the received LLR or the column LLR. A row calculation step for performing
A column operation step of calculating a column LLR and an estimated bit string from the row LLR;
A decoding method comprising: an iterative calculation end determination step for repeating the row calculation means and the column calculation means alternately and ending the repetition when a prescribed number of times is reached or the estimated bit string becomes a code word. The decoding method according to claim 9, wherein
The row operation step is performed by switching the row operation for each row before and after the row division by performing the row operation on the row before the row division based on the row operation result on the row after the row division of the parity check matrix. A decoding method comprising: The decoding method according to claim 9, wherein
The row calculation step performs row calculation for each parity check matrix that has been subjected to row division a plurality of times, based on the row calculation results for the more divided rows, by performing row operations on the previous row. A decoding method characterized by switching row operations for each of a plurality of row divisions. The decoding method according to claim 10 or 11,
In the decoding method, the row calculation step performs a row calculation on each row before and after the row division by using a minimum binary calculator. An LDPC code decoding method comprising:
A reception LLR calculation step of calculating a reception LLR from the reception signal;
In the row operation for calculating the row LLR from the received LLR or the column LLR, the row operation for the row generated by combining the plurality of rows of the parity check matrix is performed, and the plurality of row operations for the row before the row combination are performed. Line operation process to be performed by combining,
A column operation step of calculating a column LLR and an estimated bit string from the row LLR;
A decoding method comprising: an iterative calculation end determination step for repeating the row calculation means and the column calculation means alternately and ending the repetition when a prescribed number of times is reached or the estimated bit string becomes a code word. The decoding method according to claim 13,
The row operation step performs the row operation for each row before and after the row combination by performing the row operation for the row after the row combination based on the row operation result for the row before the row combination of the parity check matrix. A decoding method characterized by the above. The decoding method according to claim 13,
The row operation step performs a row operation on each parity check matrix obtained by performing row combination a plurality of times, based on a row operation result on the row before the row combination, by performing a row operation on a row that has been further combined. A decoding method characterized by switching row operations for each of a plurality of row joins. The decoding method according to claim 14 or 15,
The decoding method according to claim 1, wherein the row operation step performs a row operation on each row before and after row combination using a minimum binary calculator.

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