KR101267654B1 - Method for encoding and decoding irregular repeat multiple-state accumulate codes supportig variable length codeword and apparatuses using the same - Google Patents

Abstract

PURPOSE: An irregular repetition multiphase accumulation coding and decoding method and a device for the same are provided to remarkably reduce a requirement of memory capacity. CONSTITUTION: A coding device(1200) includes a data bit string input unit(1210), a pattern matrix storage unit(1220), a coding matrix decision unit(1230) and a coding unit(1240). The data bit string input unit receives data bit string being a decoding subject. The pattern matrix storage unit includes a fundamental pattern coding matrix corresponding to a fundamental code word length. A coding matrix decision unit generates an extension coding matrix by extending the pattern coding matrix stored in the pattern matrix storage unit according to the ratio of the required code word length to the fundamental code word length. The coding unit outputs an irregular repetition multiphase accumulation code word by irregular repetition multiphase accumulation coding the input data bit string in the data bit string input unit using the extension coding matrix decided in the coding matrix decision unit. [Reference numerals] (1210) Data bit string input unit; (1220) Pattern matrix storage unit; (1230) Coding matrix decision unit; (1240) Coding unit; (AA) Data bit string; (BB) Selected data bits; (CC) Extension coding matrix; (DD) Required length of code word; (EE) Code word

Description

A method for irregularly repeating polyphase accumulation and decoding that supports variable codeword lengths and a device therefor

The present invention relates to channel coding, and more particularly, to Irregular Repeat Multiple-State Accumulate Codes (IRmA) coding, which can support variable codeword lengths. An accumulation code encoding / decoding method and an encoding / decoding apparatus therefor.

In communication, channel coding is used to recover original data in spite of errors caused by distortion, loss, etc. of the data signal transmitted from the transmitting side through the communication channel. This refers to a process of processing data at the sender in order to do so. It is a technology that is distinguished from source coding that reduces the size of original data to facilitate transmission and storage.

On the other hand, decoding is a process of restoring the encoded and transmitted signal to the original data at the receiving side. In this case, the encoding is to make an information sequence (information bits) of length K into a codeword of length N in general. In wireless LAN or mobile communication where the signal transmission path is unstable, the length N of the codeword is made significantly larger than the information sequence length K. That is, the data to be transmitted is considerably redundant in the coded codeword. In two-way communication, if a receiving side fails to recover data in transmitting data including an information sequence, the transmitting side transmits the data again. Since retransmission of such data causes a drop in transmission speed, channel coding techniques for reducing such repetitive transmission have been studied.

Channel coding techniques are largely divided into block coding and convolutional coding.

Block coding produces K-bit data sequences as N-bit output codes. Convolutional coding is a method in which some signals from the past are used together with the current input signal when coding.

In addition, turbo codes further improve performance through parallel encoding and interleaving based on convolution codes, and are based on the idea of keeping bit error probabilities of communication channels to a minimum. One of error correction codes (ECC). The turbo code, proposed by Berrou et al. In 1993, has a relatively simple structure and provides excellent error correction performance, and thus is widely applied to a communication system requiring a high performance error correction code method.

On the other hand, low-density parity-check (LDPC) codes have recently been applied to communication systems. The LDPC code makes an information sequence of length K into a codeword of length N. In this case, a parity bit having a length of (N-K) excluding an information sequence among codewords may be generated using a parity-check matrix H. The parity check matrix H is (N-K) x N in size, and has a low density property with more zeros than one.

In the encoding method using the LDPC code, how to make the parity check matrix H is the most important factor. Typically, irregular LDPC codes provide better performance than regular LDPC codes. Regular here means that all rows of parity check matrix H used for LDPC code have the same number of 1s and all columns of H have the same number of 1s, otherwise LDPC code Is considered to be irregular. The number of ones in a row or column is referred to herein as the weight of the row or column. Irregular low-density parity-check (LDPC) codes with block lengths greater than 10 ⁴ have been shown to perform better than turbo codes.

However, since the parity check matrix H has a size of about 1000 × 2000 or more, many operations are required in the encoding and decoding process, implementation is very complicated, and requires a lot of storage space. In other words, as the size of the data block increases, the error correction capability of the LDPC becomes stronger, but there is a problem that the amount of computation and processing space required by the processor also increases.

Irregular Repeat Accumulate Code (IRA) exists as a new channel coding technique for improving the problems of the LDPC codes described above. Irregularly repeated accumulating codes are classified as turbo codes or LDPC codes and have a relatively simple form and have a capacity approaching capacity limits. Irregular Repeated Accumulation (IRA) codes are somewhat inferior to irregular LDPC codes, but have the advantage of simple coding. An Accumulate Code, an error correction code used in an IRA code, enables simple encoding using an accumulator. However, even when the accumulation code is used, there is still a problem that the operation is complicated when the block size is very large. Accordingly, there is a need for an improvement of an irregular iterative accumulating code that can improve computation speed and error correction performance as compared to conventional coding methods.

As part of this, the applicant has already filed Korean Patent Application No. 2011-0107780 and Korean Patent Application No. 2011-0122204 regarding Irregular Repeat Multiple-State Accumulate Codes (IRmA).

On the other hand, in the channel encoding technique, the length of a codeword required according to the characteristics of the system or the characteristics of the channel changes, so that the encoding apparatus and the decoding apparatus should be able to support various codeword lengths. However, in order to support various codeword lengths, there is a problem in that a size of hardware for storing encoding and decoding matrices for the codeword is increased or complexity increases.

SUMMARY OF THE INVENTION An object of the present invention for solving the above problems is to provide an irregular repetitive polyphase accumulating code encoding method capable of supporting a variable codeword length while reducing a required memory capacity in an irregular repetitive polyphase accumulating code encoding method. .

Another object of the present invention for solving the above problems is to provide an irregular repetitive polyphase accumulating code encoding apparatus capable of supporting a variable codeword length while reducing a required memory capacity in an irregular repetitive polyphase accumulating code encoding apparatus. will be.

Another object of the present invention for solving the above problems is an irregular repetitive polyphase accumulating code decoding method for receiving an encoded signal encoded using an irregular repetitive polyphase accumulating code encoding method having a variable codeword length and decoding the same. The present invention provides a method capable of supporting variable codeword lengths while reducing required memory capacity.

Another object of the present invention for solving the above problems is an irregular repetitive polyphase accumulating code decoding apparatus for receiving and decoding encoded signals encoded using an irregular repetitive polyphase accumulating code encoding method having a variable codeword length. To provide a device capable of supporting a variable codeword length while reducing the required memory capacity.

One aspect of the present invention for achieving the above object is an irregular repetitive polyphase accumulating code encoding method for generating a codeword having a variable length, which corresponds to a basic codeword length and is a basic pattern coding matrix for realizing the coding method. (B) generating an extended coding matrix extending the basic pattern coding matrix according to a ratio of the length of the basic codeword to the length of the required codeword, and generating the extended coding matrix. And performing step (c) of irregular iterative multiphase accumulation code encoding.

Here, the step (b) includes the step (b-1) of generating a partial matrix having a row and a column equal to the ratio of the basic codeword length and the required codeword length, and '1 of the basic pattern coding matrix. Assigns the partial matrix to a position of an element having a value, and a row equal to the ratio of the basic codeword length to the required codeword length at a position of an element having a value of '0' of the basic pattern coding matrix. The base pattern coding matrix may be configured to generate an extended coding matrix by allocating a zero matrix having over columns.

In this case, the partial matrix may be a combining matrix in which at least one identity matrix and / or at least one rotated identity matrix are combined.

Here, the step (c) is based on the step (c-1) of receiving an information bit string to be encoded, i row of the extended coding matrix (i starting from a value indicating the first row of the matrix). Selecting input bits among information bits constituting the information bit string, determining an encoding state according to the selected input bits (c-2), and parity bits of the i-rows based on the determined encoding state (C-3), repeating the steps (c-2) to (c-3) until the last row of the extended coding matrix by increasing i, and generating the information bit stream And combining the parity bits to generate a codeword (c-4).

In this case, the step (c-2) receives any one of the selected input bits that have not been previously input, transitions a current encoding state according to the received bits, The process of receiving a bit and the process of transitioning from a current encoding state may be repeated by the number of the input bits to determine the encoding state transitioned at the last iteration as the encoding state.

In this case, the step (c-3) determines the bits having a value for converging the encoding state to a preset state as the parity bits, preferably, the preset state is a zero state. Can be.

One aspect of the present invention for achieving the above object is an irregular repetitive polyphase accumulating code encoding apparatus for generating a codeword having a variable length, an information bit string input unit for receiving an information bit string to be encoded, basic codeword A pattern matrix storage section corresponding to a length and having a basic pattern coding matrix for realizing the coding, the pattern coding matrix stored in the pattern matrix storage section in accordance with a ratio of a length of a basic codeword to a required codeword By using a coding matrix determination unit for generating an extended coding matrix and an extended coding matrix determined by the coding matrix determination unit, irregularly repeating polyphase accumulating code encoding of the information bit string input from the information bit string input unit And an encoding unit for outputting a repeating polyphase accumulated code codeword. .

Here, the coding matrix determiner generates a partial matrix having rows and columns equal to the ratio of the basic codeword length and the required codeword length, and positions the elements having a value of '1' of the basic pattern coding matrix. The partial matrix may be assigned to, and a zero matrix may be assigned to a position of an element having a value of '0' of the basic pattern coding matrix to generate an extended coding matrix in which the basic pattern coding matrix is extended.

In this case, the partial matrix may be a combining matrix in which at least one identity matrix and / or at least one rotated identity matrix are combined.

Here, the encoding unit configures an information bit string input from the information bit string input unit by using the i (i starting from a value indicating a first row of the matrix) row of the extended encoding matrix determined by the encoding matrix determiner. An encoding state determiner which selects input bits from among information bits, and determines an encoding state according to the selected input bits, a parity bit determiner that determines parity bits of the i row based on the determined encoding state; a code that increases i to control to repeat the operation of the encoding state determiner and the parity bit determiner until the last row of the extended encoding matrix, and generates a codeword by combining the information bit stream and the generated parity bits It can be configured to include a generator.

In this case, the encoding state determiner performs an exclusive logical sum (XOR) operation between a register storing bits representing the encoding state and at least one bit among the input bits among the selected input bits and bits representing the encoding state. And a register, wherein the register shifts the stored bits one bit into the lower bit position whenever a bit is input to the encoding state determining unit, and the result of the operation performed by the calculating unit is input to the most significant bit position so as to encode the encoding state. It may be a recursive shift register for updating the bits indicating.

Herein, the parity bit determiner determines the bits having values for converging the final encoding state determined by the encoding state determiner to a preset state, preferably, the preset state is a zero state. (zero state).

One aspect of the present invention for achieving the above object is an irregular repetitive polyphase accumulating code decoding method for decoding an irregular repetitive polyphase accumulating code coded signal having a variable length, which corresponds to a basic codeword length and realizes the decoding. (A) receiving an irregular repetitive polyphase accumulated code coded signal in which information bits are combined with parity bits, and (b) a basic codeword length and a codeword applied to the coded signal. (C) generating an extended decoding matrix obtained by extending the basic pattern decoding matrix according to a ratio of lengths and performing (d) the irregular repeated polyphase accumulating code decoding using the generated extended decoding matrix. It can be configured.

In the generating of the extended decoding matrix, the generating of the extended decoding matrix may include generating the partial matrix having the number of rows and columns equal to the ratio of the basic codeword length and the required codeword length, and the basic. The sub-matrix is assigned to a position of an element having a value of '1' of a pattern decoding matrix, and the base codeword length and a required codeword at a position of an element having a value of '0' of the basic pattern decoding matrix. (C-2) generating an extended decoding matrix in which the basic pattern decoding matrix is extended by allocating a zero matrix having rows and columns corresponding to a ratio of lengths.

In this case, the partial matrix may be a combining matrix in which at least one identity matrix and / or at least one rotated identity matrix are combined.

In the performing of the irregular repetitive polyphase accumulating code decoding, the coded bits included in the coded signal may be grouped into G (G is an integer of 2 or more) groups according to the extended decoding matrix. Step (d-1), for each bit included in the coded signal, based on the likelihood of each bit provided from a plurality of groups containing each bit (the value of a first message hereinafter) Estimating the likelihood (hereinafter, the value of the second message) of each bit that each bit provides to a plurality of groups including each bit (d-2), and a bit representing an encoding state transition. By using a two-dimensional BCJR (Bahl, Cocke, Jelinek and Raviv) algorithm based on release, the values of the first message are updated based on the values of the second message provided by the G groups. Providing to D) repeating performing the step d-2 and the step d-3 using the newly calculated values of the first message and the values of the second message d And (d-5) determining the value of each bit according to the likelihood of each bit estimated based on the values of the first message calculated in the last iteration.

At this time, the step (d-3) is based on the values of the second message for the bits included in the i-th group (where i is 1≤i≤G) to the bits included in the i-th group. Calculating values of the first message for each group, wherein the calculating includes calculating forward state metrics and backward state metrics based on the values of the second message, and k-th forward. And calculating a value of a first message for a k th bit of the i th group of bits based on the product of the state metric and the k + 1 th backward state metric.

One aspect of the present invention for achieving the above object is an irregular repeating polyphase accumulating code decoding apparatus for decoding an irregular repeating polyphase accumulating coded signal having a variable length, wherein information bits and parity bits to be decoded are combined. A coded signal receiver for receiving a randomly repeated polyphase accumulated code coded signal, a pattern matrix storage unit corresponding to a basic codeword length, and having a basic pattern decoding matrix for realizing the decoding, a basic codeword length and the coded signal According to the ratio of the length of the codeword applied, by using the decoding matrix determiner for generating an extended decoding matrix extending the basic pattern decoding matrix stored in the pattern matrix storage unit and the extended decoding matrix determined by the decoding matrix determiner, Coded signal received by the coded signal receiver And a decoder configured to output an information bit string included in the coded signal by irregularly repeating multiphase accumulated code decoding.

Here, the decoding matrix determiner generates a partial matrix having rows and columns equal to the ratio of the basic codeword length and the required codeword length, and has an element having a value of '1' of the basic pattern decoding matrix. Assigns the sub-matrix at position), and a zero matrix having rows and columns equal to the ratio of the basic codeword length to the required codeword length at the position of the element having a value of '0' of the basic pattern decoding matrix. By assigning, the basic pattern decoding matrix may be configured to generate an extended decoding matrix.

In this case, the partial matrix may be a combining matrix in which at least one identity matrix and / or at least one rotated identity matrix are combined.

Here, the decoding unit groups the coded bits included in the coded signal into groups of G (the G is an integer of 2 or more) according to the extended decoding matrix, and for each bit included in the coded signal, Based on the likelihood of each bit (hereinafter, the value of the first message) provided from the plurality of groups containing each bit, the respective bits are provided to the plurality of groups containing each bit. The second message provided by the G groups by using a two-dimensional BCJR algorithm based on a trellis representing an encoding state transition and a process of estimating the likelihood (hereinafter, the value of the second message) of each bit Based on the values of, repeating the process of updating the values of the first message and providing them to the respective bits, and repeats the values of the first message calculated in the last iteration. Depending on the available bits of each even second which is estimated it may be configured to determine the value of the respective bits.

In this case, updating the values of the first message and providing the bits to the respective bits based on the values of the second message may be performed on bits included in the i th group (where i is 1≤i≤G). Computing the values of the first message for the bits included in the i-th group for each group based on the values of the second message for the group, the calculating process, the values of the second message Calculate forward state metrics and backward state metrics based on the product of the first message for the k th bit of the i th group based on the product of the k th forward state metric and the k + 1 th forward state metric; Can be configured to yield a value.

When the encoding method, the device, the decoding method, and the device according to the present invention are used as described above, performance can be improved while lowering a required level of memory capacity, and a codeword having a variable length can be supported.

That is, by generating the encoding and decoding matrix for supporting the required length of the codeword by using the basic pattern encoding and decoding matrix, the required level of the memory capacity for storing the encoding matrix and the decoding matrix can be significantly reduced.

1 is a flowchart illustrating a method for encoding an irregular repetitive polyphase accumulated code of the present invention.
2 is a trellis diagram for explaining a process of changing an encoding state and a process of determining parity bits according to an embodiment of the disclosed technology.
3 is a conceptual diagram illustrating a concept of a coding matrix in an irregular repetitive polyphase accumulating code encoding method according to the present invention.
4 is a flowchart illustrating a decoding method of an irregular repetitive polyphase accumulated code coded signal according to the present invention.
FIG. 5 is a flowchart illustrating a two-dimensional BCJR algorithm for updating a first message value in an irregular repetitive polyphase accumulated code decoding method according to the present invention.
FIG. 6 is a conceptual diagram illustrating a two-dimensional BCJR algorithm for updating a first message value in an irregular iterative multiphase accumulated code decoding method according to the present invention.
7 is a flowchart illustrating a method for encoding an irregular repetitive polyphase accumulating code supporting a variable codeword length according to the present invention.
8 is a flowchart illustrating an embodiment of a method of generating an extended coding matrix in an irregular repetitive polyphase accumulating code encoding method supporting variable codeword lengths according to the present invention.
FIG. 9 is a conceptual diagram illustrating a unit matrix I ₀ and a 1-right rotated unit matrix I ₁ and a 1-left rotated unit matrix I ₁ .
10 is a conceptual diagram illustrating a coupling matrix in which a unit matrix and a rotation unit matrix are combined.
FIG. 11 is a conceptual diagram illustrating a concept of generating an extended coding matrix using a basic pattern coding matrix.
12 is a block diagram illustrating a configuration of an irregular repetitive polyphase accumulating code encoding apparatus supporting a variable codeword length according to the present invention.
13 is a block diagram illustrating an example of a configuration of an encoding unit of an encoding apparatus according to the present invention.
14 is a circuit diagram for explaining a configuration of an encoding state determination unit applied to an encoding apparatus according to the present invention.
FIG. 15 is a circuit diagram illustrating a configuration of an encoding state determiner when the encoding state number is 4, according to an embodiment of the disclosed technology.
16 is a flowchart illustrating a method of decoding an irregular repetitive polyphase accumulating code supporting a variable codeword length according to the present invention.
17 is a flowchart illustrating an embodiment of a method of generating an extended decoding matrix in an irregular repetitive polyphase accumulating code decoding method supporting variable codeword lengths according to the present invention.
18 is a block diagram illustrating a configuration of an irregular repetitive polyphase accumulator code decoding apparatus supporting a variable codeword length according to the present invention.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

The terms first, second, A, B, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

Irregular repetition Polyphase - Accumulation  Code coding method

The LDPC code shows better performance than the turbo code when the block length is 10 ⁴ or more, but there are various problems such as the implementation is very complicated and requires a lot of storage space.

An irregular iterative polyphase accumulating code encoding method, which is the basis of the present invention, is an encoding method that exhibits improved error correction performance compared to a conventional LDPC code, and has a fast operation speed and easy parallel processing. It is a new coding scheme that introduces the concept of check. Irregular Repeat Multiple-State Accumulate Code (IRmA) encoding and decoding methods of the present invention described below are described in Korean Patent Application Nos. 2011-0107780 and 2011-0122219 of the applicant. It is included in the content of the present invention. Hereinafter, a method for irregularly repeating multiphase accumulated code encoding and decoding will be described with reference to the accompanying drawings.

1 is a flowchart illustrating a method for encoding an irregular repetitive polyphase accumulated code of the present invention.

The encoder generates an information bit block from the information bit string b _k using an Irregular Repetition (IR) code, and then uses a polyphase accumulation code from the generated information bit block to parity bits in the information bit string b _k . s and _p b is created the added codewords (codeword). This is called "irregular repeat multiple-state accumulate code" (IRmA) in the present invention.

The encoder can correct transmission errors of the information bits by transmitting the input information bits together with the parity bits generated cumulatively. The use of such a polyphase-accumulated code has the advantage of being able to encode efficiently. That is, according to the disclosed technology, coding speed can be improved and error correction performance can be improved as compared with the conventional coding method. The number of parity bits (N _P ) determined at one time is an integer of 2 or more, and may be determined as an appropriate number in consideration of error correction performance, encoding speed, arithmetic speed, required storage space, and the like. Hereinafter, a description will be given of a four-phase accumulation code in which the number of N _P is 2 and the state number N _S is 4, but the present invention is not limited thereto, and N _P may be an integer such as 3 or 4, in which case N _S can be an integer such as 8 or 16.

Hereinafter, a method of encoding one information bit string b _k will be described as an example with reference to FIG. 1.

이다. 여기서, K는 정보 비트열 b_k의 길이이다. 다음에 부호화기는 정보 비트 블록의 정보 비트들의 순서를 섞는다.In step S110, the encoder repeats each information bit included in the information bit string a plurality of times and interleaving the order of the information bits repeated a plurality of times. The number of times q (j) of repeating each information bit b _j included in the information bit string may vary randomly for each bit. The information bits repeated a plurality of times constitute one information bit block. In this case, the length L of the information bit block is

to be. Here, K is the length of the information bit string b _k . The encoder then shuffles the information bits of the information bit block.

In step S120, the encoder initializes the encoding state. According to an embodiment, the encoder may initialize the encoding state every time one information bit block, that is, one information bit string is encoded. In one example, the encoder may initialize the coding state to zero state.

In step S130, the encoder selects some information bits of the interleaved information bits. The encoder repeats steps S130 to S150 a predetermined number of times (hereinafter, referred to as G times), and for each iteration, selects previously unselected information bits among the mixed information bits of the information bit block. The number of information bits selected in the i th iteration of the G iterations is called K _i . According to an embodiment, the encoder may divide the L information bits constituting the information bit group into G groups, and then select information bits included in any one of the divided groups as the some information bits. . The number of information bits included in the i th group G _i becomes K _i . In one example, at each iteration, the encoder may select some information bits in a manner that sequentially selects one of the G groups.

In step S140, the encoder changes the encoding state according to the selected plurality of information bits. The encoder changes the encoding state every time the selected information bits are input one by one. According to an embodiment, the encoder may change an encoding state while repeating steps S142 and S144.

In step S142, the encoder receives one of the selected plurality of information bits that has not been previously input. The encoding state is changed from the current state to the next state according to the bit received in step S144. The encoder repeats steps S142 and S144 until all selected bits are input. That is, in step S140 performed at the i th time, the encoder repeats steps S142 and S144 K _i times.

The number of states that an encoding state can have is N _S. The current state is determined as one of the N _S states based on the previously input bits. The current state is initialized, for example, to state 0 on the first iteration of the first group, and on subsequent iterations the state changed from the previous iteration becomes the current state. The next state is determined by the current state and the currently input bit. The next state becomes one of the two states corresponding to the current state, which is determined according to the currently input bit. According to an embodiment, a process of changing an encoding state according to input bits when N _S is 4 is illustrated in FIG. 2. In the embodiment of FIG. 2, when the current state is state 0 (S = 0), the next state may be state 0 or state 2 (S = 0 or S = 2). If state 0 and the input bit is 1, the next state is state 2. That is, according to the current state, there are two states that can be the next state, and the coder transitions to one state determined according to the input bit among two states corresponding to the current state.

When the current state (S _k ) and the next state (state at k + 1 iteration, S _{k +1} ) of the k iterations of K _i iterations are expressed as in Equation 1, between the current state and the next state According to an embodiment, a relationship such as Equation 2 or Equation 3 may be established.

When the value of S _k is represented by N bits, d _{N -1, k} represents the most significant bit of the N bits, and d _{0, k} represents the least significant bit of the N bits. Similarly, when the value of S _{k +1} is represented by N bits, d _{N −1, k + 1} represents the most significant bit of the N bits, and d _{0 , k + 1} represents the least significant bit of the N bits.

는 배타적 논리합(exclusive OR, XOR) 연산을 의미하고, d_k 는 d_{0 ,k} 내지 d_{N -1,k}중 선택되는 적어도 하나의 비트를 XOR 연산한 결과 값을 나타낸다. 일례로, d_k 는 d_{0 ,k} 내지 d_{N -1,k} 비트들을 모두 XOR 연산한 결과일 수 있으며, 다른 일례로, d_k 는 d_{0 ,k} 내지 d_{N -1,k} 비트들 중 d_{0 ,k}, d_{2 ,k} 등 홀수 번째 비트들을 XOR 연산한 결과일 수 있다.
i _k is the information bit received in the k th iteration,

Denotes an exclusive OR (XOR) operation, and d _k represents a result of performing an XOR operation on at least one bit selected from d _{0 , k} to d _{N −1, k} . For example, d _k may be the result of performing an XOR operation on all of the bits d _{0 , k} to d _{N −1, k} , and as another example, d _k is d of d _{0 , k} to d _{N −1, k} bits. _This may be a result of performing an XOR operation on odd bits such as _{0 , k} , d _{2 , and k} .

At this time, a ₁ to a _{N -1} have a value of 0 or 1 _{, and} the coefficient of d _{0 , k} is always 1. a ₁ The values a to _{N −1} may all have a value of 1, and some (eg, odd-numbered values) may have a value of 1 in the remainder (eg, even-numbered values).

More specifically, the case where the state transitions as in the embodiment of FIG. 2 among the case where the state number N _S is 4 will be described with an example. When the current state at the k th iteration is represented by two bits [d _{1 , k} d _{0 , k} ], and the next state is represented by [d _{1 , k + 1} d _{0 , k + 1} ], each state The relationship between the bits representing may be represented by Equation 4.

At this time, if the current state value is 0 [00], the next state value is 0 [00] when the input bit is 0 and 2 [10] when the input bit is 1. If the current state value is 1 [01], the next state value is 2 [10] when the input bit is 0, and 0 [00] when the input bit is 1. If the current state value is 2 [10], the next state value is 3 [11] when the input bit is 0 and 1 [01] when the input bit is 1. Finally, if the current state value is 3 [11], the next state value is 1 [01] when the input bit is 0 and 3 [11] when the input bit is 1.

Among the cases where the state number N _S is 4, the state transition rule according to another embodiment may be represented by Equation 5.

After step S142 and step S144 are repeated a predetermined number of times, in step S150 the encoder determines the parity bits based on the coding state changed by the last iteration. For example, in the case of the i-th iteration, an encoder, based on the K _i second modified coding state by the K _i-th input bit determines the i th parity bit.

According to one embodiment, the encoder determines the values of the input bits as parity bits that cause the changed encoding state to converge to a preset state (eg, an initialization state). For example, in the i-th iteration, the value of the input bits for causing the K _i -th changed coding state to converge to an initialization state (eg, state 0) may be the i-th parity bits. More specifically, in FIG. 2 in which the state number N _S is 4, the number N _P of parity bits is 2, and the state transitions as shown in Equation 4, the parity bits in the i th iteration are determined as follows. When the value of the K _i th changed encoding state is state 0 [00], when the value of the K _i th changed encoding state is State 1 [10], and the value of the K _i th changed encoding state is State 2 [11] When the value of the K _i -th changed encoding state is state 3, the parity bits become [01]. 2, a predetermined i-th parity bits can see that time, the convergence state of state 0 is K _i second modified coding state after all previously set by the state transition is completed, assuming the input bits deuleogandago after K _i th iteration 220. In FIG. 2 and the above-described example, the case of convergence to state 0 has been described, but the converged state is not limited thereto and may be determined to converge to another state. On the other hand, when the number of states is N _S , the number of bits N _P of the parity bits is log ₂ N _S. The number of parity bits N _P determined at one time is an integer of 2 or more, and may be determined in an appropriate number in consideration of error correction performance, encoding speed, arithmetic speed, required storage space, and the like. Hereinafter, a description will be given of a four-phase accumulation code in which the number of N _P is 2 and the state number N _S is 4, but the present invention is not limited thereto, and N _P may be an integer such as 3 or 4, and N _S Can be an integer such as 8 or 16.

The encoder selects a plurality of previously unselected information bits among the mixed information bits (that is, bits of the information bit block), and repeats steps S130 to S150 at least once. For example, when the encoder divides the information bit block into G groups, the encoder may sequentially perform steps S130 to S150 for each group G times. Since the initialization of the encoding state is not performed when the steps S130 to S150 are repeated, the initial encoding state in the i + 1 th iteration is the same as the last encoding state (K _i th changed encoding state) in the i th iteration. When the steps S130 to S150 step G-repeated, the N _P parity bit group G is generated more.

In step S160, the encoder generates a codeword based on the information bit string and the parity bits determined in step S150. For example, the codeword may be generated by combining the information bit string b _k and the bit string b _p in which G parity bits are combined, such as c = [b _k b _p ]. According to one embodiment, b _p is [b _{K +1} , b _{K +2} , ..., b _{K + Np (i-1) +1} , ..., b _{K + Np (G-1) + Np} ], and b _{K + Np (i-1) + 1} means the first bit of the parity bits generated in the i-th iteration. When the parity bits are generated by repeating G times, the code rate is K / (K + N _P × G).

2 is a trellis diagram for explaining a process of changing an encoding state and a process of determining parity bits according to an embodiment of the disclosed technology. FIG. 2 is a trellis diagram when N _S is 4, N _P is 2, and a state transitions as shown in Equation 4 as described above.

In FIG. 2, an iterative process of transitioning states as information bits are input is unfolded over time. Trellis diagrams include branches and states. The branches represent a coded signal or a state transition in accordance with the coded signal. The states represent encoding states that transition with time in correspondence with the encoded signal. In FIG. 2, the encoding states according to the input of the information bits are displayed in a circle, and a solid line arrow indicates a case where bit 0 is input and a dotted line arrow indicates a case where bit 1 is input. Each time the encoding for one block starts, the encoding state is initialized to state zero. Then, when the information bit is input, it is transitioned to the next state according to the current state and the value of the input bit.

t = (i, l) indicates the time at which the first information bit of the i th selected information bits (hereinafter referred to as the i th group) is input. At t = (1,1), the current state value is state 0, which is an initialization value. Thereafter, when 0 is inputted, the state transitions to 0, and when 1 is inputted, state 2 is entered. Assuming 1 is entered, the current state value at t = (1,2) is state 2. Thereafter, the state transitions to state 3 when 0 is input, and to state 1 when 1 is input. If 0 is entered, the current state value at t = (1,3) is state 3. As the information bits are input as described above, the state transition is repeated. When information bits are input as many as a preset number for one group, for example, K _{1 for} the first group, N according to the encoding state S _t (where t = (1, K ₁ +1)) changed in the K _1st iteration. Determine the parity bits of the _P bit. For example, if the state value at t = (1, K ₁ +1) is 2, the parity bits are [11]. The parity bits are determined by the values of the input bits that make the state value of the encoded state S _t (where t = (1, K ₁ +1)) changed at the K ₁ iteration to converge to a particular state, for example state 0.

Referring to FIG. 2, when the coding state changed in the K ₁ iteration is state 2, it can be confirmed that when bit 1 is inputted, state 1 is input, and when bit 1 is inputted again from state 1, it becomes state 0 (zero state). have. When the parity bits for the first group are determined, the above-described process is repeated while sequentially receiving the information bits of the second group. At this time, the encoding state changed by the input of the last information bit of the first group becomes the initial encoding state of the second group. Once the second parity bits are determined, the above process is repeated for all subsequent groups as well. As described above, since a parity bit value is determined based on an encoding state changed as one information bit of each group is input, the receiving side can determine whether there is an error of transmitted data by using the parity bits.

On the other hand, the above-described irregular iterative multi-phase accumulation code encoding method is a matrix of G rows N columns (where N is the length of the codeword and the sum of the length of the information bit string b _k and the parity bit length G × N _P ) (hereinafter, referred to as “encoding”). Matrix ").

The above-described coding matrix is a concept necessary to describe a method of encoding an irregular repetitive polyphase accumulating code supporting a variable codeword length according to the present invention. The coding matrix can also be described as a decoding matrix on the decoding side. That is, the same matrix as the coding matrix used in the encoding process is used as the decoding matrix in the decoding process.

3 is a conceptual diagram illustrating a concept of a coding matrix in an irregular repetitive polyphase accumulating code encoding method according to the present invention.

3 shows an irregular repeating polyphase accumulating code encoding matrix A of G rows N columns, and matrix A may structurally represent a process of encoding an information bit string using an irregular repeating polyphase accumulating code encoding method. That is, the characteristic that the information bit string is repeated by irregular repetition of the irregular repetitive polyphase accumulation code encoding method can also be expressed through the coding matrix A. FIG.

The matrix A may serve as a generator matrix in the LDPC code.

The number of bits selected from the information bit string b _k in the i iterations of the G repetitions is m (i), and the number of repeatedly selected jth bits of the K bits constituting the information bit string b _k is q. It is called (j). The matrix A is a binary matrix, and the values of the components a _{i and j} of the matrix have all zero values except a _{i and pi (l)} . π (l) means the column index j of the l-th selected bit among the m (i) bits selected in the i-th iteration. The value of a _{i, j} (ie, a _{i , π (l)} ) with j = π (l) is 1.

In FIG. 3, a 10 by 40 matrix A is illustrated. The matrix A shown in FIG. 3 repeats the steps S130 to S150 ten times with G = 10. With K = 20, the _number of bits in the information bit string b _k is 20. The number of bits N _P of the parity bits is two. Since the process of determining the parity bits is repeated 10 times, the total length of the parity bit block determined is 20.

On the other hand, the gray shaded portions of the matrix A all have zero values. In the first row, the 3rd, 4th, 9th, 14th, 16th, 17th column has a value of 1, so in the first iteration, the 3rd, 4th, 9th, 14th, 16th, 17th bits of the information bits of the information bit string bk. Are selected, and step S140 is performed. The remaining columns can be interpreted as well.

On the other hand, the coding matrix here is only a means for structurally explaining the method of encoding the irregular repetitive polyphase accumulating code according to the present invention, the operations of the matrix described below are understood as a technical idea of controlling the coding process by matrix operations. It should be understood that this idea is not necessarily made by full matrix operations. For example, a memory efficient storage method may be used by using elements of a matrix having only values of 0 and 1, and having a low density of an element having a value of 1. In addition, when a memory efficient storage method is used, matrix manipulation for irregular repetitive polyphase accumulating code encoding supporting variable codeword lengths described below may also be performed in a memory efficient manner.

irregular Polyphase Accumulation  Code decryption method

The coded signal received through the wired / wireless channel with the codeword encoded by the above-described irregular polyphase accumulation code encoding method may be decoded by various decoding algorithms. For example, instead of the conventional LDPC code using the tanh rule for parity check, a two-dimensional BCJR (Bahl, Cocke, Jelinek, Raviv) algorithm can be used to decode a randomly iterative multiphase accumulated code encoded coded signal.

Hereinafter, for the sake of understanding, a process of decoding received data by using the two-dimensional BCJR algorithm based on the trellis of FIG. 2 by the decoding method according to the present invention will be described. In the context of the present embodiment, parts to which the LDPC decoding scheme is equally applicable may be simply mentioned or omitted.

The encoding matrix A described with reference to FIG. 3 may be used in the encoding process and may also be used in the decoding process. Therefore, the matrix A serves as a generator matrix in the encoding process but serves as a parity check matrix in the decoding process. That is, in the decoding process, the matrix A plays the same role as the parity check matrix in decoding using the LDPC code.

The IRmA code may be represented by a Tanner Graph, that is, nodes divided into two sides and edges connected from one node to another node. Nodes on either side of the nodes on both sides are variable nodes meaning each bit of the codeword, and nodes on the other side are group nodes meaning each group.

The decoding process can be described by repeating a process of transmitting a message from one node to another node along the branch and updating a message to be delivered based on the received message. As the message delivery and update process is repeated, the accuracy of decryption becomes higher. Typically, the maximum number of iterations is determined in advance, and if the decoding succeeds within the maximum number of iterations, the iteration is stopped.

In this case, the message includes information on the likelihood of the corresponding bit in the coded signal. Likelihood refers to the degree of likelihood that a bit has a value of 1 or 0. As an index representing the likelihood, a case in which a log likelihood ratio (LLR) is used will be described as an example, but is not limited thereto. Group nodes update the message delivered to each variable node using the two-dimensional BCJR algorithm.

4 is a flowchart illustrating a decoding method of an irregular repetitive polyphase accumulated code coded signal according to the present invention.

In operation S410, the decoder receives an encoded signal including information bits and parity bits. In step S420, the decoder groups the coded bits included in the coded signal into G (G is an integer of 2 or more) groups. For example, the decoder may match the encoded bits with at least one of the G groups. One group may include a plurality of encoded bits, and any one encoded bit may be included in the plurality of groups. The number of bits included in the i th group is called m (i). The m (i) coding bits may be composed of K _i information bits and N _P parity bits. The encoding bits may represent a repetition and interleaving process in the encoding process using a decoding matrix, similarly to using the parity check matrix H in the LDPC code, and the decoder uses the decoding matrix to encode You can group bits. The variable nodes representing each encoding bit are connected with at least one group node corresponding to itself among the group nodes representing each group.

The variable nodes may have as many as N lengths of codewords, and the group nodes may have as many as G groups. Here, the order of the N variable nodes is denoted by j, and the order of the G group nodes is denoted by i. The number of variable nodes (the number of coding bits included in the i-th group) connected to the i-th group node among the G group nodes is m (i). That is, the l th node among the m (i) variable nodes corresponds to the j = π (l) th node among the N variable nodes. Similarly, the number of group nodes connected to the j th variable node among the N variable nodes, that is, the number of groups including the j th encoding bit is referred to as q (j). When the order of q (j) group nodes is expressed as k, the relationship between k and i is represented by i = σ (k). That is, the k th node among the q (j) group nodes corresponds to the i = σ (k) th node among the G group nodes.

When the coded bits are grouped, the decoder may initialize the likelihood L and the first message U of each bit of the coded signal based on the received coded signal. L _j means the LLR of the j th bit (b _j ) of the N-bit encoded signal. The first message U is a message provided by the group node to the variable node. U _{i , j} is a message provided by the i-th group node to the j-th variable node and has a value of LLR of b _j estimated by the i-th group node. U _{0 , j} is an observed LLR value of b _j estimated based on the received coded signal value. U _0, U _{i, j} except for _j is initialized to 0, the value L _j is initialized to U _{0, j} values.

In operation S430, the decoder determines each variable node based on likelihood of each bit provided from a plurality of groups including each bit, for each bit among encoded bits. Estimates the likelihood (hereinafter, the value of the second message) of each bit provided to the plurality of group nodes. According to an embodiment, in the j th variable node, q (j) first messages U _{σ (k), j} provided from q (j) group nodes connected with the j th variable node, where k is from 1 q (j) second messages V are calculated based on the integers between q (j). The calculated second messages V _{j , σ (k)} , where k is an integer between 1 and q (j), are LLR values of b _j that the j th variable node provides to each of q (j) group nodes. Indicates. Among them, the second message Vj, σ (n) = Vj, i provided to σ (n) = i-th group node may be calculated as shown in Equation 6 according to an embodiment. At this time, it is defined as σ (0) = 0.

The second message provided by the jth variable node is the sum of the LLR values (U _{σ (k), j} ) of b _j and U _{0 , j} provided by the group nodes connected to the jth variable node to the jth variable node. In this case, the second message V _{j , i} provided to the i-th group node is determined as a sum value except for the value of the first message U _{i , j} provided from the i-th group node.

개의 제2 메시지의 값들을 기초로, 제1 메시지의 값들을 갱신하여 각 변수 노드에 제공한다. 제1 메시지의 값은 각 그룹 노드들이 각 그룹 노드와 연결된 비트들에 대하여 추정하는 각 비트들의 가능도로서, 각 비트의 주변 비트들의 가능도에 기반하여 추정된다. 예컨대, U_{i ,j}는 i번째 그룹 노드가 j번째 변수 노드에 제공하는 제1 메시지의 값으로, G개의 그룹들이 제공받은 개의 제2 메시지의 값들 중 j번째 변수 노드가 i번째 그룹 노드에 제공한 제2 메시지 V_{j ,i}를 제외한 제2 메시지들을 기초로 추정되는 값이다. 이때, 복호화기는 2차원 BCJR 알고리즘을 이용하여 제1 메시지 값을 갱신할 수 있다. 복호화기가 제1 메시지 값을 갱신하는 과정은 도 5를 참조하여 후술한다.In step S440, the decoder updates the values of the first message based on the values of the second message. According to an embodiment, the decoder uses a two-dimensional BCJR algorithm based on trellis representing the encoding state transition, so that the G group nodes are provided.

Based on the values of the two second messages, the values of the first message are updated and provided to each variable node. The value of the first message is the likelihood of each bit that each group node estimates for the bits associated with each group node and is estimated based on the likelihood of the surrounding bits of each bit. For example, U _{i , j} is the value of the first message provided by the i-th group node to the j-th variable node, and the j-th variable node among the values of the second message provided by the G groups is provided to the i-th group node. A value estimated based on the second messages except for the second message V _{j , i} . In this case, the decoder may update the first message value by using the 2D BCJR algorithm. The process of updating the first message value by the decoder will be described later with reference to FIG. 5.

In step S450, the decoder repeats the operations of steps S430 and S440. The decoder calculates a second message by using the first message calculated in the previous iteration, and repeats the process of updating the first message by using the newly calculated second message by a preset number of times.

In step S460, the decoder determines the value of each bit b _j according to the likelihood of each bit b _j estimated based on the first message values updated in the last iteration. According to an embodiment, L _{j, which} is an LLR value of b _j , may be calculated as shown in Equation 7 below.

The decoder determines whether the value of b _j is 1 or 0 depending on whether the value of L _j is less than 1 or greater than 1.

FIG. 5 is a flowchart illustrating a two-dimensional BCJR algorithm for updating a first message value in an irregular repetitive polyphase accumulated code decoding method according to the present invention.

According to the decoding method using the two-dimensional BCJR algorithm described in FIG. 5, the decoder calculates an forward state metric based on the second messages, and then calculates a forward state metric and a backward state metric based on the second message. Finally, calculate the outward status metric. Once the status metrics are calculated, the decoder can update the first message using the forward, forward, backward, and outward status metrics. Meanwhile, for convenience of description, the time t corresponding to Vπ (l), i, which is the l-th second message, of the m (i) second messages provided by the i-th group node of the coded signals is a two-dimensional time index. T = (i, l). Further, time t = (i, l) is a time corresponding to the lth bit of the i th group. In this case, for each i t = (i, 1), ..., t = (i, K _i ) is the time corresponding to the information bits, t = (i, K _i + 1), ..., t = (i, m (i)) is the time corresponding to the parity bit.

The coded signal is assumed to be a signal generated by combining parity bits generated according to state transition and parity bit generation rules as shown in the trellis diagram of FIG. 2 with information bits. Since the transition rule of FIG. 2 is information that the transmitting side and the receiving side have in common, the receiving side can have the same trellis as shown in FIG.

개의 제2 메시지들에 2차원 BCJR 알고리즘을 적용하여

개의 제1 메시지들을 갱신한다. 도 2의 트렐리스는 일반적인 트렐리스와 달리, 정보 비트들이 입력됨에 따른 부호화 상태 천이를 나타내는 메인 가지들(210)과 패리티 비트들이 입력됨에 따른 부호화 상태 천이를 나타내는 보조 가지들(220)을 포함한다. 보조 가지들(220)은 시간 t=(i, K_i+1)인 때마다 메인 가지들(210)로부터 분기된다. 즉, 도 2에서, i번째 보조 가지가 메인 가지와 분기되는 분기 상태의 시점은 t=(i, K_i+1)로 나타낼 수 있으며, i번째 보조 가지의 최종 상태의 시점은 t=(i, m(i)+1)로 나타낼 수 있다. 경우에 따라, Ki는 m(i)-N_P로 표현될 수도 있다.Based on the trellis of FIG. 2, the decoder receives the G group nodes.

Two-dimensional BCJR algorithm to two second messages

First messages Unlike the general trellis, the trellis of FIG. 2 includes main branches 210 indicating the encoding state transition as information bits are input and auxiliary branches 220 indicating the encoding state transition as parity bits are input. . The auxiliary branches 220 branch off from the main branches 210 whenever time t = (i, K _i +1). That is, in FIG. 2, the time point of the branched state where the i-th auxiliary branch branches from the main branch may be represented by t = (i, K _i +1), and the time point of the final state of the i-th auxiliary branch may be t = (i , m (i) +1). In some cases, Ki may be represented by m (i) -N _P.

According to the conventional BCJR algorithm, a soft decision value of a transmission bit may be obtained by calculating a post probability based on a received bit string. The posterior probability at time t may be calculated as the sum of the posterior transition probabilities at time t. The posterior probability at time t is expressed by Equation 8.

Here, the posterior probability P (d _t = d) is a probability that the transmission bit value at time t is d (d is 0 or 1). σ (s _t , s _{t +1} ) is the probability of post-transition at time t, σ (s _t = a, s _{t +1} = b) is that state at time t (s _t ) is state a, and It means the probability that the state s _{t +1} at t + 1 is the state b. At this time, state b is a state value transitioned at time t + 1 when the state at time t is state a and the transmission bit value at time t is d. s _t has a value of any one of coding states given by the state number N _S. In the present embodiment, S _t has a value of any one of state 0, state 1, state 2, and state 3.

According to the two-dimensional BCJR decoding algorithm proposed in the disclosed technique, the post-transition probability in the main branch and the post-transition probability in the auxiliary branch are calculated based on different values. The post-transition probability of the west and the post-transition probability of the secondary branches are calculated based on different values.

Here, α (s _t) is the state at time t-forward state metric of s _t, in the β _{(t +1} s) of time t + 1 is the backward state metric of the state s _t at _+1, γ _(t s, s _{t +1} ) is the branch metric that links between s _t and s _{t +1} . The forward state metric and the backward state metric are defined only in the branch representing the information bits, ie in the state associated with the main branch. γ (s _t , s _{t + 1} ) is a branch metric at time t, a branch metric at time t in equation (9), and only a branch metric at main branch in equation (9). The value of the branch metric at time t may be determined based on the value of the second message corresponding to time t.

Here, μ (s _t ) and λ (s _{t +1} ) are state metrics relating to a state associated with a branch representing a parity bit, and are an out state state metric at time t and an inward state metric at time t + 1, respectively. do. The forward state metric and the forward state metric are defined only in a branch representing parity bits, i. γ (s _t , s _{t +1} ) is a branch metric at time t. In Equation 10, only the branch metric at the secondary branch is used. Further, the value of the branch metric at time t may be determined based on the value of the second message corresponding to time t. The outward state metric is calculated sequentially based on the outward state metric of the previous state from each time the secondary branch branches in the main branch. The initial outward state metric at the time of branching may be calculated based on the forward and backward state metrics. The forward status metric is calculated in reverse order based on the forward status metric of the next state, from the last state of each auxiliary branch.

When the post-transition probability is obtained for all the branches on the trellis as shown in Equations 9 and 10, the value of the first message corresponding to the time t is determined according to the post-probability calculated according to Equation 9.

FIG. 6 is a conceptual diagram illustrating a two-dimensional BCJR algorithm for updating a first message value in an irregular iterative multiphase accumulated code decoding method according to the present invention.

FIG. 6 is a simplified representation of the trellis of FIG. 2, and the diagram of FIG. 2 illustrates an encoding state at time t according to all cases of bits that may be input until each time t and bits input until time t. All the states you can have are shown.

In the diagram of FIG. 6, the bits input up to each time t and the coding state at time t are simply represented by one arrow and one circle, respectively. The arrows in FIG. 6 may have a value of 0 or 1, and each circle may have a value from state 0 to state 3. As shown in FIG. 6, in the two-dimensional BCJR algorithm according to the disclosed technique, inward recursion, forward recursion, backward recursion, and outward recursion are performed. Decoding proceeds in order. In this case, according to an embodiment, the order of the forward iteration and the backward iteration may be changed. Inward iteration is a process of calculating the inward state metric value in the reverse order from the final state of each auxiliary branch. In the forward iteration operation, the forward state metric is sequentially calculated from the first state of the main branch, but in the branch state, the forward state metric is calculated by reflecting the forward state metric. In the backward iteration operation, the backward state metric value is calculated in the reverse order of the forward iteration operation. Similar to the forward iteration operation, in the branched state, the backward state metric is calculated by reflecting the value of the inward state metric. The outward iteration operation is a process of sequentially calculating the outward state metric values in the reverse order of the inward iteration operation from the branch state at the time when the main branch and the auxiliary branch are branched. A method of calculating each state metric in this order will be described in detail.

Prior to calculating each state metric, the decoder calculates branch metrics corresponding to each branch from the second message, based on the trellis diagram of FIG. 2 or 6. Once the branch metrics are calculated, the decoder calculates each state metric in the order as described above. When each state metric value is calculated, the decoder may update the first message based on the state metric values. However, in the present embodiment, the above-described two-dimensional BCJR is applied, and since only the LLR values (extrinsic information) of bits other than the self are reflected in the process of estimating the LLR value thereof, in calculating the post-transition probability, the equation Unlike 10 and 11, do not multiply the values of the branches metric.

According to one embodiment, the decoder determines the value of the branch metric at t = (i, l) based on the second message V _{pi (l), i} value. The second message V _{π (l), i} is a message value provided from the l th variable node among m (i) variable nodes connected to the i th group node by the i th group node. At this time, the values of the second message are input values of the two-dimensional BCJR algorithm, and correspond to the prior LLR values of the respective transmission bits in the BCJR algorithm. For example, the branch metric corresponding to bit 0 of the branch metrics at time t = (i, l) is the probability that the bit value at time t = (i, l) is 0 from the value of V _{π (l), i.} The metric of the branch corresponding to bit 1 is also determined by the probability that the bit value at time t = (i, l) is 1 from the value of V _{pi (l), i} .

If this is expressed as an equation, Equation 11 is obtained.

When the branch metric is calculated, the decoder sequentially calculates each state metric as follows.

In operation S510, the decoder calculates inward state metrics based on values of a branch metric corresponding to parity bits among all encoded bits included in the G groups. The forward status metric is a status metric for the state associated with the auxiliary branch, which is calculated in the reverse order based on the forward status metric of the next state. The inward status metric is calculated for each secondary branch representing parity bits. The inward status metric is the branch state s (i, l) at the point where the main branch and the secondary branch branch from the state s _(il) (where l = m (i)) just before the final convergence state of each secondary branch. In this case, l = K _i +1 or l = m (i) -N _P +1 is calculated in the reverse order as in Equation 12.

Assuming that each auxiliary branch converges to a specific state, for example state 0, s _{(i, m (i) +1)} has a state 0 value. Thus, λ (s _{(i, m (i) +1)} ) is a value of 1 when s _{(i, m (i) +1)} is state 0, and s _{(i, m (i) +1)} is In the other state, it has a value of zero.

After calculating the forward state metric for all the auxiliary branches, in step S520, the decoder forwards the values based on the branch metric values and the forward state metrics corresponding to the information bits among the coded bits included in the G groups. Calculate state metrics and backward state metrics. The forward state metric is a state metric for the state connected to the main branch 210 and is sequentially calculated based on the forward state metric of the previous state. The backward state metric is a state metric for the state connected to the main branch 210 and is calculated in the reverse order based on the backward state metric of the next state. The forward state metric is computed sequentially for each state from t = (i, 1) to t = (i, K _i +1) by a forward iteration operation. Further, i is incremented one by one until the i value is 1 and the i value is G, and the calculation is repeated. The forward state metric of s _{(i, 1),} which is a state corresponding to the first bit of each information bit group _, may be calculated using a condition as shown in Equation 13.

이다.In this case, S _init is an initial value of the encoding state. Assuming that S _init is state 0, α (s _(1,1) ) has a value of 1 when s _(1,1) is state 0 and a value of 0 when s _(1,1) is the other state. Also, since the state at t = (i, 1) is the same as the state at t = (i-1, K _{i -1} +1),

to be.

Subsequent to the branch state in each group of information bits, the forward state metric is calculated as shown in Equation 14. That is, α (s _t = a) is a s _{t -1,} which for all the branches leading to the state s _t s _{t -1} a from the value of having a random state value, and the branch metric for each of It is calculated as the sum of the products of the forward state metric. In this case, t may have a value of (i, 2), ..., (i, K _i ) for every i.

Finally, the forward state metric of the branch state in each information bit group is calculated by reflecting the value of the forward state metric as shown in Equation 15. That is, since the branch state is a point where the auxiliary branch and the main branch cross each other, the forward state metric is calculated by multiplying the forward state metric value calculated from the auxiliary branch and the forward state metric value calculated from the main branch.

At this time, t, which is the branching time point, is t = (i, K _i +1) or, since K _i = m (i) -N _P , t = (i, m (i) -N _P +1). Similarly, t-1 = (i, K _i ) or (i, m (i) -N _P ).

The backward state metric is calculated in reverse order for each state from t = (i, K _i +1) to t = (i, 1) by a backward iteration operation. Further, i decreases one by one from the value of i to G until the value of i is 1 and the calculation is repeated. The backward state metric for the state at t = (i, K _i +1), which is changed according to the last bit of each information bit group, may be calculated using a condition as in Equation 16 below.

이다. 각 정보 비트 그룹에서 분기 상태를 제외한, 나머지 백워드 상태 메트릭은 수학식 17과 같이 산출된다. 즉, β(s_t=a)는 임의의 상태 값을 가지는 s_{t +1}로부터 상태 값이 a인 s_t로 향하는 모든 역방향 가지에 대하여, 각 가지에 해당하는 가지 메트릭과 해당하는 s_{t +1}의 백워드 상태 메트릭의 곱들의 합으로 산출된다. 이때, t는 매 i에 대하여 (i,K_i),...,(i,2) 값을 가질 수 있다.
Therefore, the state at t = (i, Ki + 1) is the same as the state at t = (i + 1,1),

to be. Except for the branch state in each group of information bits, the remaining backward state metrics are calculated as shown in Equation 17. That is, β (s _t = a) is s _{t +1} that for all of the reverse leading to the state s _t a value of from s _{t +1} having an arbitrary state value, and the branch metric for each of Is computed as the sum of the products of the backward state metric. In this case, t may have a value of (i, K _i ), ..., (i, 2) for every i.

Finally, the forward state metric of the branch state in each group of information bits is calculated by reflecting the value of the forward state metric as shown in Equation 18. That is, since the branch state is the point where the secondary branch and the main branch cross each other, the backward state metric in the branch state is calculated by multiplying the inward state metric value calculated from the secondary branch and the backward state metric value calculated from the main branch. do.

In operation S530, the decoder calculates outward state metrics based on values of branch metrics corresponding to the parity bits among encoding bits included in the G groups. The outward state metric is a state metric for a state connected with the auxiliary branch 220 and is sequentially calculated based on the branch state corresponding to the outward state metric and parity bits of the previous state.

Like the inward status metric, the outward status metric is calculated for each auxiliary branch representing parity bits, but is performed in the opposite direction to the inward status metric. The outward status metric is _calculated from the branch status s _{(i, l)} at each time the main and secondary branches branch, where l = K _i +1 or l = m (i) -N _P +1. It is calculated sequentially up to the state s _(il) , where l = m (i), just before the final state of the auxiliary branch.

The forward state metric in each branch state is equal to the product of the forward state metric and the backward state metric in each branch state. This may be expressed as an equation (19).

The outward state metrics from the state following the branch state are sequentially calculated as shown in Equation 20.

Once the state metrics are calculated, the decoder can update the values of the first message directed to the variable node corresponding to the information bits or parity bits (S540). The decoder updates the values of the first message directed to the variable node corresponding to the information bits based on the values of the forward state metrics and the backward state metrics, and based on the values of the forward state metrics and outward state metrics. Update the values of the first message directed to the variable node corresponding to the parity bits.

However, as mentioned above, since values of the first message for each bit are updated to reflect only LLR values (extrinsic information) of bits other than itself, in calculating a post-transition probability, Equations 9 and 10 Unlike multiply the values of the branches metric. That is, the post-transition probability used to update the first message values is calculated as in Equations 21 and 22. According to an embodiment, the first message U _{i , π (n)} of the i-th group node provides to the j = π (n) -th variable node, where n is an integer of 1 ≦ n ≦ m (i ₎ . The value is calculated as shown in Equation 21 when the j = π (n) th variable node corresponds to the information bit, and is calculated as shown in Equation 22 when the j = π (n) th variable node corresponds to the parity bit. It can be calculated as the sum of the transition probabilities. The value of the first message U _{i , π (n} ) is LLR after the posterior probability P (dt) of the bit corresponding to t = (i, n) calculated according to Equations 11 and 7 in the two-dimensional BCJR algorithm. It can be determined by the value converted into.

As such, the values of the first message are output values of the two-dimensional BCJR algorithm, and are determined based on post-transition probabilities calculated as Equations 21 and 22. Equation 23 is shown.

Variable according to the invention Codeword  Supporting length IRmA  Code coding method

7 is a flowchart illustrating a method for encoding an irregular repetitive polyphase accumulating code supporting a variable codeword length according to the present invention.

Referring to FIG. 7, the encoding method according to the present invention is an irregular repetitive polyphase accumulating code encoding method for generating a codeword having a variable length, which corresponds to a basic codeword length, and performs basic pattern encoding for realizing the encoding method. Comprising: a matrix (S710), generating an extended coding matrix extending the basic pattern coding matrix according to the ratio of the length of the basic codeword and the length of the required codeword (S720) and the generated extended coding matrix It may be configured to include a step (S730) to perform irregular iterative multi-phase accumulated code encoding using.

First, in step S710, the basic pattern coding matrix refers to a coding matrix supporting the length of a basic codeword as the coding matrix described above with reference to FIG. 3, and serves as a generation matrix in LDPC coding. In this case, the basic codeword length may generally correspond to the shortest codeword length selectable in the encoding method according to the present invention.

The term 'basic pattern coding matrix' is used here because, when the length of a codeword to be coded and output is the length of the basic codeword, the basic pattern coding matrix itself is used as a coding matrix. If the length of the codeword to be output is larger than the length of the basic codeword, the basic pattern coding matrix plays a role of only a basic pattern for generating the extended coding matrix.

However, the encoding matrix and the decoding matrix described below refer to a matrix from which a parity bit portion (N-K portion of FIG. 3) is removed from the encoding matrix described in FIG. 3. Since the parity bit portions of the coding matrix are arranged with a certain regularity (see FIG. 3) in the randomly iterative multiphase accumulation code encoding method, the process of generating the extended coding matrix may be omitted. Also, since the parity bit portions of the decoding matrix are arranged with a regularity even in the decoding process of the irregular repetitive polyphase accumulation code encoding method, the parity bit portions of the decoding matrix may be omitted while generating the extended coding matrix. That is, the basic pattern coding matrix and the decoding matrix described below remove the parity bit portions of the coding and decoding matrix described in FIG. 3, thereby generating an extended coding matrix and a decoding matrix. However, the actual decoding process may be configured to add a parity bit portion arranged with a certain regularity to the generated extended decoding matrix to perform the actual decoding process.

Next, step S720 is a step of generating an extended coding matrix extending the basic pattern coding matrix according to a ratio of the length of the basic codeword and the length of the required codeword.

8 is a flowchart illustrating an embodiment of a method of generating an extended coding matrix in an irregular repetitive polyphase accumulating code encoding method supporting variable codeword lengths according to the present invention.

Referring to FIG. 8, an example of operation S720 may include generating a partial matrix having a row and a column corresponding to a ratio of the basic codeword length and the required codeword length (S721) and the basic pattern coding matrix. Assigning the partial matrix to a position of an element having a value of '1', and adding a row equal to the ratio of the basic codeword length to a required codeword length at a position of an element having a value of '0' of the basic pattern coding matrix; A step S722 may be generated by assigning a zero matrix having columns to generate an extended coding matrix from which the basic pattern coding matrix is extended. Here, '1' and '0' are only binary meanings for distinguishing the values of the matrix elements, and pre-defined values that can be used to distinguish the positions where the partial and zero matrices are assigned are used. It may be. For example, it is also possible to assign a partial matrix to the position of an element with a value of '0' and to assign a zero matrix to the position of an element with a value of '1'.

In step S721, the partial matrix may be generated to have as many rows and columns as the ratio of the basic codeword length to the required codeword length. For example, if the length of the basic codeword is 20 and the length of the required codeword is 100, the partial matrix is a 5x5 matrix with rows and columns of 100/20 = 5. Therefore, step S722 may be described as a process of extending the basic pattern coding matrix by a desired size by assigning each element position of the basic pattern coding matrix to a partial matrix or a zero matrix having a size of 5 × 5. Can be.

In this case, as an example of the partial matrix, a combining matrix in which at least one identity matrix and / or at least one rotated identity matrix are combined may be used. On the other hand, a zero matrix refers to a matrix of which the values of all matrix elements are zero. Hereinafter, an example of a coupling matrix that can be used as a partial matrix will be described.

FIG. 9 is a conceptual diagram illustrating a unit matrix I ₀ and a 1-right rotated unit matrix I ₁ and a 1-left rotated unit matrix I ₁ .

That is, the rotation unit matrix replaces the j th column of the n × n unit matrix I ₀ for a given k (0 = k = n-1) with mod (j + k, n) (mod (jk, n)) of I _k . In the first column. Where mod (a, b) is the remainder of a divided by b.

10 is a conceptual diagram illustrating a coupling matrix in which a unit matrix and a rotation unit matrix are combined.

The coupling matrix V _ijkl means a 2n × 2n matrix in which four unit matrices and rotation unit matrices I _i , I _j , I _k , and I _l are combined in order.

As an example of the coupling matrix, FIG. 10 illustrates a coupling matrix including both the unit matrix and the rotation unit matrix, but the coupling matrix may be configured only with the unit matrix, and the coupling matrix may be configured only with the rotation unit matrices.

FIG. 11 is a conceptual diagram illustrating a concept of generating an extended coding matrix using a basic pattern coding matrix.

Referring to FIG. 11, the generated partial matrix (eg, a coupling matrix in which a unit matrix and a rotation unit matrix are combined by a desired size) is allocated to positions of elements having a value of '1' of the basic pattern coding matrix 1100. The process of generating an extended coding matrix 1110 in which the basic pattern coding matrix is extended by assigning a zero matrix to positions of elements having a value of '0' of the basic pattern coding matrix is described.

That is, according to the method of extending the extended coding matrix, a desired code is maintained while maintaining the irregularity of the basic pattern coding matrix by allocating a partial matrix or a zero matrix having a desired size for each position of the elements of the basic pattern coding matrix according to the values of the elements. An extended coding matrix corresponding to the length may be generated.

Finally, in step S730, irregular repeated polyphase accumulating code encoding is performed using the extension coding matrix generated in step S720.

In the irregular repeated polyphase accumulating code encoding in operation S730, the irregular repeated polyphase accumulating code encoding method described above with reference to FIG. 1 may be used.

That is, the irregular repetitive polyphase accumulation code encoding in step S730 is based on a step of receiving an information bit string to be encoded, and i rows (i starting from a value indicating a first row of the matrix) of the extension coding matrix. Selecting input bits among information bits constituting the information bit string, determining an encoding state according to the selected input bits, and determining parity bits of the i row based on the determined encoding state; And repeating the step of determining the encoding state and increasing the parity bits until the last row of the extended coding matrix by increasing i, and then combining the information bit stream and the generated parity bits to form a codeword. Can be configured to generate

Variable according to the invention Codeword  Supporting length IRmA  Code encoding device

12 is a block diagram illustrating a configuration of an irregular repetitive polyphase accumulating code encoding apparatus supporting a variable codeword length according to the present invention.

Referring to FIG. 12, the encoding apparatus 1200 according to the present invention may include an information bit string input unit 1210, a pattern matrix storage unit 1220, an encoding matrix determiner 1230, and an encoder 1240. Can be.

First, the information bit string input unit 1210 is configured to receive an information bit string b _k to be encoded. The information bit string input unit 1210 receives an information bit string to be transmitted from a higher layer.

Next, the pattern matrix storage unit 1220 is a component corresponding to a basic codeword length and having a basic pattern coding matrix for storing irregular repeated polyphase accumulated code coding. In this case, the basic codeword length may generally correspond to the shortest codeword length selectable in the encoding method according to the present invention.

As mentioned above, the basic pattern coding matrix is used as an encoding matrix itself when the length of the codeword to be output by the coding apparatus is the length of the basic codeword, but is a codeword to be encoded and output. If the length of P is greater than the length of the basic codeword, the basic pattern coding matrix serves as a basic pattern for generating the extended coding matrix.

Next, the encoding matrix determiner 1230 is a component that extends the basic pattern encoding matrix stored in the pattern matrix storage unit 1220 according to a required codeword length to generate an extended encoding matrix.

The method of generating the extended coding matrix by the coding matrix determiner 1230 is the same as the method described above with reference to FIG. 8.

That is, the encoding matrix determiner 1230 generates a partial matrix having rows and columns corresponding to the ratio of the basic codeword length to the required codeword length in order to obtain an extended coding matrix corresponding to the length of the codeword. And assigning the partial matrix to the position of the element having the value of '1' of the basic pattern coding matrix, and the basic codeword length and the required code to the position of the element having the value of '0' of the basic pattern coding matrix. The base pattern coding matrix may be configured to generate an extended coding matrix by allocating a zero matrix having rows and columns corresponding to a ratio of the lengths.

In this case, as an example of the partial matrix, a combination matrix of at least one identity matrix and / or at least one rotated identity matrix may be used. As described.

In addition, the concept of generating an extended coding matrix by allocating a partial matrix or a zero matrix at element positions of the basic pattern coding matrix is as described with reference to FIG. 11.

Next, the encoder 1240 is an element that irregularly repeats multiphase accumulative code encoding of the information bit strings input from the information bit string input unit by using the extension coding matrix generated by the encoding matrix determiner.

13 is a block diagram illustrating an example of a configuration of an encoding unit of an encoding apparatus according to the present invention.

Referring to FIG. 13, the encoder 1240 may include an encoding state determiner 1241, a parity bit determiner 1242, and a codeword generator 1243.

First, the encoding state determiner 1241 uses the i (i is a value starting from a value indicating the first row of the matrix) row of the extended encoding matrix determined by the encoding matrix determiner to input information input from the information bit string input unit. Among the information bits constituting the bit string, the input bits are selected and an encoding state is determined according to the selected input bits. That is, the encoding state determiner is a component that performs the steps from step S120 to step S140 described with reference to FIG. 1. An example of the configuration of the encoding state determination unit 1241 will be described later with reference to FIG. 14.

The parity bit determiner 1242 is a component that determines parity bits of the i row based on the encoding state determined by the encoding state determiner. That is, the parity bit determiner 1242 may be configured to determine, as parity bits, bits having a value that causes the encoding state determined by the encoding state determiner 1241 to converge to a preset state (eg, zero state). Can be.

Lastly, the codeword generator 1243 controls the operations of the encoding state determiner and the parity bit determiner as described above, and generates a codeword by combining the information bit string and the generated parity bits.

That is, the codeword generator 1243 increases the i to control to repeat the operation of the encoding state determiner and the parity bit determiner until the last row of the extended coding matrix, and controls the information bit stream and the generated parity bits. Combine to generate codewords.

14 is a circuit diagram for explaining a configuration of an encoding state determination unit applied to an encoding apparatus according to the present invention.

The encoding state determiner 1241 may include a register 1410 and an operation unit 1420 to determine an encoding state. The register 1410 stores bits representing an encoding state. The calculating unit 1420 may include at least one of an input bit i input to the encoding state determining unit 1241 and bits representing an encoding state (that is, bits stored in a register, d ₀ , d ₁ ,...) Performs an XOR operation between one bit.

For example, an XOR operation may be performed between all bits stored in the register 1410 and an input bit. In another example, an XOR operation may be performed between an input bit and a bit stored in the D ₀ register. That is, each of the storage spaces D ₀ to D _{N -1} of the register 1410 is selectively connected to the operation unit 1420 to provide the stored bit value to the operation unit 1420. In this case, according to an embodiment of the present disclosure, each time an information bit is input to the encoding state determiner 1441, the register 1410 moves the stored bits to the lower bit positions by one bit, and the calculation result performed by the operation unit 1420. May be a recursive shift register for updating bits indicating an encoding state by being input to the most significant bit digit.

The operation of the register 1410 and the operation unit 1420 may be expressed as Equation 2 or Equation 3 below.

FIG. 15 is a diagram for describing an encoding state determiner when the encoding state number is 4 according to an embodiment of the disclosed technology. When the coded state number N _S is 4, the parity bit number N _P and the number of bits representing the coded state are 2, so the register 1410 has two storage spaces D ₁ and D ₀ . The operation unit 1420 may perform an XOR (exclusive OR) between at least one bit among the bits representing the input bit i and the encoding state, that is, bits d ₁ and d ₀ in which values are stored in registers D ₁ and D ₀ . Perform the operation.

For example, (a) of FIG. 15 performs an XOR operation of input bits i and three bits d ₁ and d ₀ which are bit values stored in a register. This is represented by Equation 4 below. As another example, FIG. 15B performs an XOR operation between input bit i and d ₀ , a bit value stored in a register. This is represented by Equation 5 below.

Variable according to the invention Codeword  Supporting length IRmA  Code decryption method

16 is a flowchart illustrating a method for decoding an irregular repetitive polyphase accumulating code supporting variable codeword lengths according to the present invention.

Referring to FIG. 16, in the IRmA code decoding method supporting variable codeword lengths according to the present invention, a step corresponding to a basic codeword length and including a basic pattern decoding matrix for realizing the decoding (S1610), information Receiving an irregular repetitive polyphase accumulating coded code signal in which bits are combined with parity bits (S1620), and extending the base pattern decoding matrix according to a ratio of a base codeword length and a length of a codeword applied to the coded signal. Generating a decoding matrix (S1630) and performing the irregular repetitive polyphase accumulating code decoding using the generated extended decoding matrix (S1640).

In operation S1610, the basic pattern decoding matrix means the decoding matrix described above with reference to FIG. 3, and the basic codeword length may generally correspond to the shortest codeword length selectable in the decoding method according to the present invention. have. Since the basic pattern decoding matrix is the same as the matrix described as the basic pattern coding matrix in the above-described encoding method and apparatus, further description thereof will be omitted.

In step S1620, an irregular repetitive polyphase accumulating coded signal having information bits combined with parity bits is received. That is, the coded signal refers to a signal in which a codeword coded by a coding method according to the present invention is transmitted from a transmitting side to a receiving side through a wired or wireless channel.

In operation S1630, an extended decoding matrix is generated by extending the basic pattern decoding matrix according to a ratio of the length of the basic codeword to the length of the codeword applied to the coded signal received in step S1620.

FIG. 17 is a flowchart illustrating an embodiment of a method for generating an extended decoding matrix in an irregular repetitive polyphase accumulating code decoding method supporting variable codeword lengths according to the present invention, and is similar to the process illustrated in FIG. 8.

Referring to FIG. 17, an example of operation S1630 includes generating a partial matrix having rows and columns corresponding to a ratio between the basic codeword length and a length of a codeword applied to a received coded signal in operation S1631. And assigning the partial matrix to a position of an element having a value of '1' of the basic pattern decoding matrix, and a codeword length and a required codeword at a position of an element having a value of '0' of the basic pattern decoding matrix. The method may further include generating an extended decoding matrix in which the basic pattern decoding matrix is extended by assigning a zero matrix having rows and columns corresponding to a ratio of lengths (S1632).

In operation S1631, the partial matrix may be generated to have a row and a column corresponding to a ratio of the length of the basic codeword and the length of the codeword applied to the received coded signal. For example, if the length of the basic codeword is 20 and the length of the required codeword is 100, the partial matrix is a 5x5 matrix with rows and columns of 100/20 = 5. Therefore, step S1632 may be described as a process of extending the basic pattern decoding matrix by a desired size by assigning each element position of the basic pattern decoding matrix to a partial matrix or a zero matrix having a size of 5 × 5. Can be.

In this case, as an example of the partial matrix, a combining matrix in which at least one identity matrix and / or at least one rotated identity matrix are combined may be used.

Accordingly, in the method of generating an extended decoding matrix according to the present invention, a desired code is maintained while maintaining the irregularity of the basic pattern decoding matrix by allocating a partial matrix or a zero matrix having a desired size for each position of elements of the basic pattern decoding matrix according to the values of the elements. An extended decoding matrix corresponding to the length may be generated.

The process of performing decryption in step S1640 has already been described above with reference to FIG. 4, and a detailed description thereof will be omitted. That is, step S1640 includes grouping the coded bits included in the coded signal into groups of G (the G is an integer of 2 or more) according to the extended decoding matrix (d-1). For bits, based on the likelihood of each bit provided from a plurality of groups in which each bit is included (the value of a first message hereinafter), each bit is a plurality of bits in which each bit is included. Estimating the likelihood (hereinafter, the value of the second message) of each bit provided to the groups (d-2), a two-dimensional BCJR based on trellis representing the encoding state transition (Bahl, Cocke, Jelinek and (D-3) updating and providing values of the first message to each bit based on values of the second message provided by the G groups using a Raviv algorithm; Values of a first message and the second message Repeating performing the step (d-2) and the step (d-3) using the values of the message (d-4) and the estimated value based on the values of the first message calculated in the last iteration. And determining the value of each bit according to the likelihood of each bit (d-5).

At this time, as the message transfer and update processes of steps (d-2) and (d-3) are repeated, the accuracy of decryption increases.

Accordingly, the update and delivery processes of the first and second messages are repeated as many times as a predetermined number of repetitions, and the respective bits according to the likelihood of the respective bits estimated based on the values of the first message calculated in the last repetition. It can be configured to determine the value of.

In addition, while repeating the update and transfer process of the first and second messages within a preset threshold number of repetitions, the probability of each bit estimated based on the values of the first message calculated for each repetition. The value of each bit may be determined, and the repetition may be stopped when the decoding is determined to be successful.

Step (d-3) may be described as a two-dimensional BCJR algorithm, where the i-th is based on the values of the second message for the bits included in the i-th group, where i is 1≤i≤G. The process of calculating the values of the first message for the bits included in the group may be described as performing for each group, the calculating of the forward state metrics and the back based on the values of the second message. Calculating word status metrics and calculating a value of a first message for a kth bit of the i-th group of bits based on the product of the kth forward state metric and the k + 1th backward state metric; Can be configured.

Variable according to the invention Codeword  Supporting length IRmA  Decryption device

18 is a block diagram illustrating a configuration of an irregular repetitive polyphase accumulator code decoding apparatus supporting a variable codeword length according to the present invention.

Referring to FIG. 18, an irregular repetitive polyphase accumulating code decoding apparatus 1800 supporting a variable codeword length according to the present invention includes an encoding receiver 1810, a pattern matrix storage 1820, a decoding matrix determiner 1830, and the like. The decoder 1840 may be configured to be included.

The decoding apparatus 1800 according to the present invention is generally located in a data receiving apparatus, decodes a received coded signal, extracts an information bit string from the coded signal, and delivers the information to a higher layer. In general, a data receiving apparatus receives and recognizes information about a codeword length applied to an encoded signal from a data transmitting side explicitly or implicitly.

First, the coded signal receiver 1810 receives an irregular repetitive polyphase accumulating coded coded signal having a combination of information bits and parity bits, which are to be decoded. The term coded signal is used here instead of codeword because it is a received signal before a decision is made with a bit value (0 or 1).

Next, the pattern matrix storage unit 1820 is a component corresponding to the basic codeword length and having a basic pattern decoding matrix for storing the decoding. The basic pattern decoding matrix is a decoding matrix corresponding to the basic codeword length, and in the encoding method and apparatus, the matrix is described as the basic pattern coding matrix.

Next, the decoding matrix determiner 1830 generates an extended decoding matrix extending the basic pattern decoding matrix stored in the pattern matrix storage unit according to a ratio of a length of a basic codeword to a length of a codeword applied to the coded signal. It is a component.

In an embodiment, the decoding matrix determiner 1830 generates a partial matrix having a row and a column corresponding to a ratio of the length of the basic codeword and the length of the codeword applied to the received coded signal, and then Assigning the partial matrix to a position of an element having a value of '1', and a row equal to the ratio of the basic codeword length to a required codeword length at a position of an element having a value of '0' of the basic pattern decoding matrix; By assigning a zero matrix with columns, the basic pattern decoding matrix can be configured to generate an extended decoding matrix.

In this case, the partial matrix may be generated to have a row and a column corresponding to the ratio of the length of the basic codeword and the length of the codeword applied to the received coded signal. For example, if the length of the basic codeword is 20 and the length of the required codeword is 100, the partial matrix is a 5x5 matrix with rows and columns of 100/20 = 5. Accordingly, the operation of the decoding matrix determiner 1830 extends the basic pattern decoding matrix by a desired size by assigning each element position of the basic pattern decoding matrix to a partial matrix or a zero matrix having a size of 5 × 5. It can be described as a process.

In this case, as an example of the partial matrix, a combining matrix in which at least one identity matrix and / or at least one rotated identity matrix are combined may be used.

Finally, the decoder 1840 performs irregular repetitive polyphase accumulation code decoding on the coded signal received by the coded signal receiver 1810 using the extended decoding matrix determined by the decoding matrix determiner 1830. It is a component that outputs an information bit string included in an encoded signal.

A detailed operation of the decoder 1840 may be described as performing the decoding method described with reference to FIGS. 4 to 6, and since the above is already described above, only a brief description thereof will be provided.

That is, the decoder 1340 groups the coded bits included in the coded signal into groups of G (the G is an integer of 2 or more) according to the extended decoding matrix, and for each bit included in the coded signal. Based on the likelihood of each bit (hereinafter, the value of the first message) provided from the plurality of groups containing each bit, wherein each bit is assigned to a plurality of groups containing each bit. The second group provided by the G groups by using a two-dimensional BCJR algorithm based on a trellis representing an encoding state transition and a process of estimating the likelihood (hereinafter, the value of the second message) of each of the bits provided. Based on the values of the message, the process of updating the values of the first message and providing them to the respective bits is repeated, and based on the values of the first message calculated in the last iteration. It may be configured to determine the value of each bit according to the likelihood of each bit being determined.

At this time, as the message transfer and update process is repeated, the accuracy of decryption increases. Accordingly, the update and delivery processes of the first and second messages are repeated as many times as a predetermined number of repetitions, and the respective bits according to the likelihood of the respective bits estimated based on the values of the first message calculated in the last repetition. It can be configured to determine the value of.

In addition, while repeating the update and transfer process of the first and second messages within a preset threshold number of repetitions, the probability of each bit estimated based on the values of the first message calculated for each repetition. The value of each bit may be determined, and the repetition may be stopped when the decoding is determined to be successful.

In this case, based on the values of the second message provided by the G groups, updating the values of the first message and providing the bits to the respective bits may include the i th (where i is 1 ≦ i ≦ G). It may be described that performing a process for each group of calculating values of the first message for the bits included in the i-th group based on the values of the second message for the bits included in the group. The calculating process includes calculating forward state metrics and backward state metrics based on the values of the second message and the i th group based on the product of the k th forward state metric and the k + 1 th forward state metric. And calculate a value of the first message for the k th bit of the bits.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims It can be understood that

1200: encoding device
1210: information bit string input unit 1220: pattern matrix storage unit
1230: encoding matrix determiner 1240: encoder

Claims (22)

An irregular repetitive polyphase accumulating code encoding method for generating a codeword having a variable length,
(A) corresponding to a basic codeword length and including a basic pattern coding matrix for realizing the coding method;
Generating an extended coding matrix extending the basic pattern coding matrix according to a ratio of the length of the basic codeword to the length of the required codeword; And
(C) performing irregular iterative multiphase accumulation code encoding using the generated extended encoding matrix,
Step (c) is
Receiving an information bit string to be encoded (c-1);
An input bit is selected from among information bits constituting the information bit string based on row i of the extension coding matrix (i is a value starting from a value indicating a first row of the matrix), and an encoding state is selected according to the selected input bits. Determining (c-2); And
(C-3) determining parity bits of the i row based on the determined encoding state;
Repeating the steps (c-2) to (c-3) until the last row of the extended coding matrix by increasing i, and then combining the information bit stream and the generated parity bits to generate a codeword An irregular repetitive polyphase accumulation code encoding method comprising the step (c-4). The method according to claim 1,
The step (b)
(B-1) generating a partial matrix having rows and columns equal to the ratio of the basic codeword length to the required codeword length; And
The partial matrix is assigned to a position of an element having a value of '1' of the basic pattern coding matrix, and the length of the basic codeword is required to a position of an element having a value of '0' of the basic pattern coding matrix. And (b-2) assigning a zero matrix having rows and columns equal to a ratio of codeword lengths to generate an extended coding matrix from which the basic pattern coding matrix is extended. Claim 2
And the partial matrix is a combined matrix in which at least one of an identity matrix and at least one rotated identity matrix is combined. delete The method according to claim 1,
Step (c-2) is,
Receiving any one of the selected input bits that has not been previously input, transitions the current encoding state according to the received bits, and receives the one bit and the transition of the current encoding state And repeating the process by the number of input bits to determine the coding state transitioned at the last iteration as the coding state. The method according to claim 1,
In the step (c-3), the bits having a value for converging the encoding state to a preset state are determined as the parity bits, and preferably, the preset state is a zero state. An irregular repetitive polyphase accumulation code encoding method. An irregular repeating polyphase accumulating code encoding apparatus for generating a codeword having a variable length,
An information bit string input unit for receiving an information bit string to be encoded;
A pattern matrix storage section corresponding to a length of a basic codeword and having a basic pattern coding matrix for realizing the encoding;
An encoding matrix determiner for generating an extended encoding matrix by extending the pattern encoding matrix stored in the pattern matrix storage unit according to a ratio between a basic codeword length and a required codeword length; And
And an encoding unit configured to output an irregular repetitive polyphase accumulating code codeword by using an extended encoding matrix determined by the encoding matrix determiner, to output an irregular repetitive polyphase accumulating code codeword.
The encoder is
Among the information bits constituting the information bit string input from the information bit string input unit by using the i (i starting from a value indicating the first row of the matrix) row of the extended coding matrix determined by the coding matrix determination unit, An encoding state determiner which selects input bits and determines an encoding state according to the selected input bits;
A parity bit determiner that determines parity bits of the i row based on the determined encoding state; And
Increasing i to control to repeat the operation of the encoding state determiner and the parity bit determiner until the last row of the extended encoding matrix, and generate a codeword by combining the information bit stream and the generated parity bits. An irregular repetitive polyphase accumulating code encoding device including a codeword generator. The method of claim 7,
The coding matrix determination unit,
Generate a partial matrix having rows and columns equal to the ratio of the basic codeword length to the required codeword length, and assign the partial matrix to a position of an element having a value of '1' of the basic pattern coding matrix; And assigning a zero matrix to a position of an element having a value of '0' of a basic pattern coding matrix, thereby generating an extended coding matrix in which the basic pattern coding matrix is extended. The method according to claim 8,
And the partial matrix is a combined matrix of at least one of an identity matrix and at least one rotated identity matrix. delete The method of claim 7,
The encoding state determination unit
A register for storing bits representing the encoding state; And
An operation unit configured to perform an exclusive OR operation between an input bit among the selected input bits and at least one bit among the bits indicating the encoding state;
Whenever a bit is input to the encoding state determination unit, the register moves the stored bits to the lower bit position by one bit, and the operation result performed by the operation unit is input to the most significant bit position to update the bits indicating the encoding state. An irregular repetitive polyphase accumulating code encoding device, characterized in that a recursive shift register. The method of claim 7,
The parity bit determiner
The bits having a value for converging the final encoding state determined by the encoding state determiner to a preset state are determined as the parity bits, and preferably, the preset state is a zero state. An irregular repetition multiphase accumulation code encoding apparatus. An irregular repetitive polyphase accumulating code decoding method for decoding an irregular repetitive polyphase accumulating coded signal having a variable length,
(A) corresponding to a basic codeword length and including a basic pattern decoding matrix for realizing the decoding;
(B) receiving an irregular repeating polyphase accumulating coded signal having information bits combined with parity bits;
(C) generating an extended decoding matrix extending the basic pattern decoding matrix according to a ratio of a length of a basic codeword to a length of a codeword applied to the coded signal; And
(D) performing the irregular repetitive polyphase accumulating code decoding by using the generated extended decoding matrix,
(D) performing the irregular repetitive polyphase accumulating code decoding includes:
Grouping coded bits included in the coded signal into groups G (the G is an integer of 2 or more) according to the extended decoding matrix (d-1);
For each bit included in the coded signal, each bit is based on the likelihood (hereinafter, the value of the first message) of each bit provided from a plurality of groups containing each bit. Estimating a likelihood (hereinafter, the value of the second message) of each bit provided to the plurality of groups each bit is included in (d-2);
The value of the first message, based on the values of the second message provided by the G groups, using a 2D BCJR (Bahl, Cocke, Jelinek and Raviv) algorithm based on a trellis representing an encoding state transition. Updating and providing each bit to each bit (d-3);
(D-4) repeating performing the step (d-2) and the step (d-3) by using the newly calculated values of the first message and the values of the second message; And
And determining (d-5) the value of each bit according to the likelihood of each bit estimated based on the values of the first message calculated in the last iteration. The method according to claim 13,
Generating the extended decoding matrix (c)
Generating a partial matrix having rows and columns equal to the ratio of the basic codeword length to the required codeword length (c-1); And
The partial matrix is allocated to a position of an element having a value of '1' of the basic pattern decoding matrix, and the length of the basic codeword is required at a position of an element having a value of '0' of the basic pattern decoding matrix. And (c-2) generating an extended decoding matrix in which the basic pattern decoding matrix is extended by allocating a zero matrix having rows and columns corresponding to a ratio of codeword lengths. Claim 14
And the partial matrix is a combined matrix of at least one of an identity matrix and at least one rotated identity matrix. delete The method according to claim 13,
The step (d-3) is based on the values of the bits included in the i-th group based on the values of the second message for the bits included in the i-th group, where i is 1≤i≤G. 1 The process of calculating the values of the message is performed for each group, the process of calculating,
Calculating forward state metrics and backward state metrics based on the values of the second message; And
calculating a value of a first message for a k th bit of the i th group of bits based on a product of the k th forward state metric and the k + 1 th backward state metric; . An irregular repeating polyphase accumulating code decoding apparatus for decoding an irregular repeating polyphase accumulating coded signal having a variable length,
An encoded signal receiving unit configured to receive an irregular repetitive polyphase accumulating coded coded signal including information bits and parity bits, which are to be decoded;
A pattern matrix storage section corresponding to a basic codeword length and having a basic pattern decoding matrix for realizing the decoding;
A decoding matrix determining unit generating an extended decoding matrix extending the basic pattern decoding matrix stored in the pattern matrix storage unit according to a ratio of a length of a basic codeword to a length of a codeword applied to the coded signal; And
And a decoding unit configured to output an information bit string included in the encoded signal by irregularly repeating multiphase accumulation code decoding of the encoded signal received by the encoded signal receiver using the extended decoding matrix determined by the decoding matrix determiner. ,
Wherein the decoding unit comprises:
According to the extension decoding matrix, the coded bits included in the coded signal are grouped into G groups (G is an integer of 2 or more),
For each bit included in the coded signal, each bit is based on the likelihood (hereinafter, the value of the first message) of each bit provided from a plurality of groups containing each bit. Using a process of estimating the likelihood (hereinafter, the value of the second message) of each bit provided to a plurality of groups including each bit and a trellis based trellis representing the encoding state transition, Based on the values of the second message provided by the G groups, the process of updating the values of the first message and providing the bits to the respective bits is repeated.
And determining a value of each bit according to the likelihood of each bit estimated based on the values of the first message calculated in the last iteration. 19. The method of claim 18,
The decoding matrix determination unit,
Generate a partial matrix having rows and columns equal to the ratio of the basic codeword length to the required codeword length, and assign the partial matrix to a position of an element having a value of '1' of the basic pattern decoding matrix; And a zero matrix having a row and a column equal to the ratio of the basic codeword length and the required codeword length to a position of an element having a value of '0' of the basic pattern decoding matrix. An irregular repeat polyphase accumulating code decoding apparatus generating an extended extended decoding matrix. The method of claim 19,
And the partial matrix is a combined matrix of at least one of an identity matrix and at least one rotated identity matrix. delete 19. The method of claim 18,
Based on the values of the second message, updating and providing the values of the first message to each bit,
calculating values of the first message for the bits included in the i-th group based on values of the second message for the bits included in the i-th group (where i is 1≤i≤G) For each group,
The calculating includes calculating forward state metrics and backward state metrics based on the values of the second message, and based on the product of a k th forward state metric and a k + 1 th backward state metric. And calculating a value of a first message for a k-th bit among the bits of the.

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