WO2009012692A1

WO2009012692A1 - Turbo-code encoding device and its method

Info

Publication number: WO2009012692A1
Application number: PCT/CN2008/071650
Authority: WO
Inventors: Jun Chen; Shaohui Sun; Yingmin Wang
Original assignee: Da Tang Mobile Communications Equipment Co., Ltd
Priority date: 2007-07-20
Filing date: 2008-07-15
Publication date: 2009-01-29
Also published as: CN101350626B; CN101350626A

Abstract

A Turbo-code encoding device, a Turbo-code encoding method and a two-layer interleaver, wherein the Turbo-code encoding device comprises: a first component code encoder which receives original data A, B inputted in couples, outputs check bit sequence Y1 and tail bit sequence Z1 after encoding; an interleaver, which receives original data A, B inputted in couples, adopts inner layer and outer layer interleaving processing to the received data, and outputs the data adopted interleaving to a second component code encoder in couples; the second component code encoder, which receives the data adopted interleaving, outputs check bit sequence Y2 and tail bit sequence Z2 after encoding; the original data A, B inputted in couples is outputted as system bit in couples.

Description

Turbo code coding device and method

Embodiments of the present invention relate to channel coding techniques in communication, and in particular, to a new Turbo code coding apparatus and method. Background technique

The Turbo code is a codec scheme proposed by C. Berrou, A. Glavieux and Rishimifajshiwa in 1993. It is better than other coding performance in low SNR applications, so it is in the third generation (3G) mobile communication. Among various schemes of the system, the turbo code is used as one of the coding standards of the wireless channel. The Turbo code coding technical specification adopted by the 3G mobile communication system is described in detail by TS 25.212 in the 3rd Generation Partnership Project (3GPP). Generally, the Turbo encoder consists of two system recursive convolutional (RSC) encoders, interleaver and The deleter is composed.

With the continuous development of 3G mobile communication, Turbo code coding technology is widely used in various 3G mobile communication systems, but the specific coding methods and interleavers used in different mobile communication systems are different. For example: In 3GPP Release 6, Turbo code is a binary (Binary) coding method, using Prime Interleaver (PIL, Prime Interleaver), does not support parallel decoding; in 3GPP LTE, using quadratic replacement polynomial (QPP, Quadratic Permutation Polynomial) The interleaver replaces the PIL interleaver and supports parallel decoding. The Turbo codes in 3GPP all use the tail bits termination method. For example: In WiMAX, the Turbo code is a Duo-Binary coding method that uses an ARP (Almost regular permutation) interleaver to support parallel decoding. The Turbo code in WiMAX ends with tail-biting. (tail-biting termination) method, no tail bits.

Specifically, a component structure of the 3GPP Turbo code encoder is as shown in FIG. 1 , and includes two component code encoders: a component code encoder 1 and a component code encoder 2, And an internal interleaver, wherein each component code encoder is composed of three registers and four adders to complete the encoding function. One input data is divided into two paths, and the input component code 1 and the inner interleaver respectively perform processing, and after outputting by the component encoder 1 or by the inner interleaver and the component code encoder 2, the tail bits and Ζ' _κ are respectively output _; Moreover, the 3GPP Turbo code encoder further outputs the uninterleaved and interleaved system bits κ»κο in two ways. In Figure 1, the generator polynomial of the component code encoder is expressed as an octal number (13, 15), Corresponding feedback polynomials {1,0, 1, 1}, feedforward polynomials {1, 1,0, 1}. For 3GPP Release 6 Turbo codes, the inner interleaver uses a PIL interleaver; for 3GPP LTE Turbo codes, the inner interleaver uses a QPP interleaver. However, according to the actual application results of the 3GPP Turbo code encoder, the effect is not very good, and the original data input is only a single input.

A component structure of the WiMAX Turbo code encoder is shown in FIG. 2, which includes a CTC interleaver and a component code encoder, and outputs system bits and parity bits subjected to interleaving and encoding processing; ^^, Y ₂ W _2o , component The code encoder is composed of three registers and five adders to complete the coding process. In Figure 2, the component code encoder generates a polynomial expressed in octal numbers as (15, 13 or 11), corresponding to its feedback polynomial { 1, 1, 0, 1}, feedforward polynomial {1, 0, 1, 1} or {1, 0, 0, 1}, the Turbo code is Duo-Binary. The CTC interleaver employed in Figure 2 is a two-layer interleaving structure comprising two processing steps: first, an intra-coupled permutation, that is, an even-numbered bit swap; Inter-couple interleaving, that is, all pairs of data blocks are interleaved using an ARP interleaver. Here, the ARP interleaving can be expressed as:

Forj =0, ..., Ν-1

Switch (j mod 4 ) :

Case 0: i = (P ₀ · j +1 ) modN

Case 1: i= (P ₀ · j +1+N/2+P! ) mod N

Case 2: i = (P ₀ · j +1+P ₂ ) modN

Case 3: i= (P ₀ · j +l+N/2+P ₃ ) modN Where N is the length of the original data, ie, the couple size; j is the paired position number after the data is interleaved; i is the paired position number before the interleaving; parameters P _Q , Pi, P ₂ , ^ It is determined by design factors such as parallelism and random disturbance, which are obtained through computer search and optimization.

In the process of implementing the present invention, the inventors have found that the prior art has at least the following problems: Since the WiMAX Turbo code uses the tail-biting termination method, the coding complexity and the decoding complexity are relatively large, and according to practical applications, the effect is Not very good either. Summary of the invention

In view of this, the main purpose of the embodiments of the present invention is to provide a Turbo code encoding apparatus and method, which can achieve better coding and decoding performance while reducing the complexity of the encoding and decoding.

To achieve the above objective, the technical solution of the embodiment of the present invention is implemented as follows:

An embodiment of the present invention discloses a turbo code encoding apparatus, including: a first component code encoder, a second component code encoder, and an interleaver;

The first component code encoder receives the paired input original data A, B, and encodes the check bit sequence Y1 and the tail bit sequence Z1;

The interleaver receives the paired input original data A, B, performs outer layer and inner layer interleaving processing on the received data, and outputs the interleaved processed data in pairs to the second component code encoder;

a second component code encoder, receiving the interleaved data, and encoding the output bit bit sequence Y2 and the tail bit sequence Z2;

The paired input raw data A, B are output as a systematic bit pair.

Preferably, the first component code encoder and the second component code encoder use the same component code coding structure; the coding structure of the component code used includes a feedback polynomial and one or more feedforward polynomials, the one The above feedforward polynomials are different feedforward polynomials.

Preferably, when the component code code uses a feedforward polynomial and a feedback polynomial, the component codes used are (11, 13), (11, 15), (13, 11), (13, 15), (13, 17), (15, 13), (15, 13), (15, 17); when the component code encoding uses two feedforward For the term and a feedback polynomial, the component codes used are (11,13,15), (13,11,15),

Any one of (13,11,17), (13,15,17), (15,11,13), (15,11,17), (15, 13, 17); when the component code is encoded When using three feedforward polynomials and one feedback polynomial, the component code used is any one of (13, 11, 15, 17), (15, 11, 13, 17); where, the number in each bracket One parameter is a feedback polynomial of the component code expressed in octal numbers, and the remaining parameters are feedforward polynomials of the component codes expressed in octal numbers.

Preferably, each of the component code encoders includes three shift registers, five or more adders, and a pair of switch switches; each of the component code encoders is provided with two inputs, the one The switch switches are respectively disposed on one input; the three shift registers are sequentially arranged along the input to the output direction on one path.

The embodiment of the invention also discloses a Turbo code coding method, including:

The original data is divided into two groups as parallel inputs; the first component code is encoded by the two sets of original data bit streams input in pairs, and the corresponding check bit sequence Y1 and tail bit sequence Z1 are output after encoding; Interleaving the two sets of original data bit streams of the paired input, and performing second component code encoding on the two sets of data bit streams after interleaving, and outputting corresponding check bit sequence Y2 and tail bits after encoding Sequence Z2.

Preferably, the parity bit sequence Y1, Υ2 includes a parity bit of a systematic bit bit and a parity bit of a tail bit. The first component code is encoded and the second component code is encoded to output three tail bits and their corresponding check bit bits, respectively.

Preferably, the outer layer interleaving process is based on a quadratic permutation polynomial; the inner layer interleaving process is to perform positional exchange of two pairs of data bits in an even pair position of the original data block. The quadratic permutation polynomial used in the outer layer interleaving process is 1 = (fi.j + f^.j ² ) mod N; the inner layer interleaving process is: when the i value satisfies imod2 = 0, the original data is input. The i-th pair of two paths (Α, Β^ exchange position, becomes (BA), placed in the j-th pair position after the outer layer is interleaved; where i is the original data block pair position number, j Interleaving and inner layer for data blocks The number of paired position numbers after interleaving, N is the number of pairs of data blocks, and is a quadratic permutation polynomial coefficient.

Preferably, in the above scheme, each component code code uses one or more feedforward polynomials and a feedback polynomial, and the one or more feedforward polynomials are different feedforward polynomials.

The embodiment of the invention further discloses a Turbo code coding interleaver, which comprises an outer layer interleaving unit and an inner layer interleaving unit, respectively performing outer layer interleaving and inner layer interleaving on the original data block. The outer interleaving unit is configured to implement an interleaving process based on a secondary permutation polynomial; and the inner interleaving unit is configured to position two pairs of data bits in an even pair position of the original data block. exchange.

The apparatus and the method for encoding the turbo code provided by the embodiment of the present invention, the coding performance of the embodiment of the present invention is obviously superior to the existing 3GPP, because the double binary coding mode, the tail bit end method, and the QPP-based double layer interleaving structure are adopted. Rel.6 Turbo code, LTE Turbo code and WiMAX Turbo code.

Since the embodiment of the present invention adopts the tail bit end method, the coding complexity and the decoding complexity are greatly reduced. Moreover, the component code encoder of the embodiment of the present invention can use a plurality of variable encoder structures corresponding to different component codes, and is flexible, simple, and convenient to use. DRAWINGS

1 is a schematic structural diagram of a 3GPP Turbo code encoder;

2 is a schematic structural diagram of a WiMAX Turbo code encoder;

3 is a schematic structural diagram of a structure of a turbo code encoding apparatus according to an embodiment of the present invention;

4a is a schematic diagram showing the structure of the implementation scheme A of the embodiment 1 of the Turbo code coding apparatus; FIG. 4b is a schematic diagram showing the structure of the implementation scheme B of the embodiment 1 of the turbo code coding apparatus; Figure 5b is a schematic diagram showing the structure of the second embodiment of the Turbo code encoding device; Figure 6b is a schematic structural diagram of the third embodiment of the Turbo code encoding device; 6b is a schematic diagram showing the structure of the implementation scheme B of the third embodiment of the turbo code encoding apparatus; FIG. 7 is a schematic structural diagram of the implementation scheme A of the embodiment 4 of the turbo code encoding apparatus; FIG. 7b is a schematic diagram of the fourth embodiment of the Turbo code encoding apparatus. Figure 8a is a schematic diagram showing the structure of the implementation scheme A of the embodiment 5 of the Turbo code coding apparatus; Figure 8b is a schematic diagram showing the structure of the implementation scheme B of the embodiment 5 of the turbo code coding apparatus; Figure 9a is a sixth embodiment of the turbo coding apparatus FIG. 9b is a schematic diagram showing the structure of the implementation scheme B of the embodiment 6 of the turbo code encoding apparatus; FIG. 10a is a schematic diagram showing the structure of the scheme A of the seventh embodiment of the turbo code encoding apparatus; FIG. 10b is a turbo code encoding. Figure 7a is a schematic diagram showing the structure of the implementation scheme B of the embodiment 8 of the Turbo code coding apparatus; Figure 1b is a schematic diagram showing the structure of the implementation scheme B of the embodiment 8 of the turbo code coding apparatus; 12 is a schematic diagram of performance effects in a case of a Turbo code according to an embodiment of the present invention. detailed description

After studying the performance of 3GPP Turbo code and WiMAX Turbo code, it is found that: In general, the performance of Turbo code using double binary coding is better than that of binary coding; QPP interleaver is better than ARP interleaver; ending with tail-biting The performance of the method is the same as that of the tail end method, but the encoding and decoding complexity of the tail-biting end method is greater than the tail end method.

Based on this, the coding apparatus and method in the embodiments of the present invention consider a coding mode, an interleaver, and an end method with better comprehensive performance, that is, in the embodiment of the present invention, a double binary coding method, a tail bit termination method, and a Double layer interwoven structure of QPP.

The basic idea of the embodiment of the present invention is: The Turbo code encoding device is composed of a first component code encoder, a second component code encoder and a two-layer interleaver, and the original data is divided into two parallel groups and input in pairs. The turbo code encoding device, after processing, outputs a respective check bit sequence and tail bit sequence by the first component code encoder and the second component code encoder, respectively. FIG. 3 is a schematic structural diagram of a structure of a turbo code encoding apparatus according to an embodiment of the present invention. As shown in FIG. 3, a turbo code encoding apparatus according to an embodiment of the present invention includes a first component code encoder 31, a second component code encoder 32, and a two-layer structure. The interleaver 33, the black dot in Fig. 3, indicates the joint in which the line is connected. The first component code encoder 31 and the second component code encoder 32 are respectively used for encoding the paired input original data A, B and the interleaved data, and then outputting the check bit sequence Y1, Υ2 And the tail bit sequence Z1, Ζ2, the internal structure of the two component code encoders are exactly the same; the double-layer structure interleaver 33 is used for parallel concatenation of two identical component code encoders to implement the dual binary Turbo coding method Specifically, the two-layer interleaver 33 performs inner layer and outer layer interleaving processing on the paired input original data A and B, and then outputs the interleaved data in pairs to the second component code encoder 32. The Turbo code encoding device also outputs the paired input raw data A, B as system bits in pairs.

In Fig. 3, the data input terminal divides the original data into two parallel groups A and B, and is coupled in a pair to the first component code encoder 31 and the two-layer structure interleaver 33, where the pair is It is assumed that the A group data and the B group data respectively output one bit in order to form a pair relationship; the first component code encoder 31 outputs the corresponding parity bit sequence Y1 and the tail bit sequence Z1; the double layer structure interleaver 33 After the paired input raw data is received, the inner layer interleaving and the outer layer interleaving processing are performed, and then the interleaved processed data is paired and outputted to the second component code encoder 32; the second component code encoder 32 obtains the original data. The paired output after the interleaver outputs a corresponding parity bit sequence Y2 and a tail bit sequence Z2. It can be seen that all the encoded outputs of the Turbo code encoding apparatus of the embodiment of the present invention include: system bit bits, that is, original data A, B; tail bit sequences Zl, Z2 at the end of the grid map returning to zero; and check bit sequence Yl Υ2, wherein the check bit sequence Y1, Υ2 includes the check bit of the systematic bit and the check bit of the tail bit, and the check bit corresponding to the output when the tail bit is output is called the check of the tail bit Bit bit.

Specifically, all the encoding outputs of the encoding apparatus of the embodiment of the present invention include the following four parts: 1) Α. , oh. , ..., A _N - i, B _N - i are raw data bits; 2) Y1 _Q , ..., Yl _N -i and Y2 _Q , ..., Y2 _N -i are the parity bits of the data bits output by the first and second component code encoders, respectively;

3) Z1 _Q , Zl^ Zl ₂ and Y1 _N , Y1 _N+1 , Yl _N+2 are tail bits output by the first component code encoder and check bit bits corresponding to the tail bits;

4) Z2 _Q , Z2i , Z2 ₂ and Y2 _N , Y2 _N+1 , Y2 _N+2 are the tail bits of the second component code encoder output and the check bits corresponding to the tail bits.

Where N is the length of the original data, ie the couple size. The code output of the embodiment of the present invention includes 6 tail bits and 6 check bit bits corresponding to the tail bits, and each component code encoder has 3 tail bits and corresponding check bit bits, because each The component code encoder requires three tail bits to clear three registers in the encoder.

In the embodiment of the present invention, the first component code encoder and the second component code encoder use exactly the same component code coding structure, and the component structure of each component code encoder is related to the component code used. At present, there are more than a dozen basic component codes that can be used for one feedforward polynomial and one feedback polynomial. The inventors have realized that if the component code uses two or more feedforward polynomials at the same time, it can be further formed. More new component codes, in this way, can provide more parity bit output for better performance.

According to the actual simulation result, the embodiment of the present invention selects one of the eight basic component codes whose performance meets the requirements and the nine new component codes obtained by simultaneously using two or more feedforward polynomials thereof, specifically The generator polynomials of the 17 component codes are represented by octal numbers: (11, 13), (11, 15), (13, 11), (13, 15), (13, 17), (15, 11), (15, 13), (15, 17), (11, 13, 15), (13, 11, 15), (13,11, 17), (13, 15, 17), (13, 11, 15 , 17), (15,11,13), (15,11,17), (15,13,17), (15,11,13,17). The first parameter in each parenthesis is a feedback polynomial of the component code represented by an octal number, and the remaining parameters are feedforward polynomials of the component code expressed in octal numbers.

The following is an example of selecting the first eight component codes, and each component code encoder is specifically described with reference to the drawings. The composition of the structure. Figures 4 to 11 are component codes (11, 13), (11, 15), (13, 11), (13, 15), (13, 17), (15, 11), (15, 13 respectively). ), (15, 17) The two components of the component code encoder, wherein a diagram is that only the switch provided by the B road is provided with a grounding terminal, and b is a switch provided for both A and B. Ground terminal.

As can be seen from Figures 4 through 11, each component code encoder includes three shift registers D, five or more adders, denoted by Θ. Each adder performs a modulo 2 addition of a binary number (0, 1), equivalent to performing a multiplication of the bipolar signal (+1, -1). Each component code encoder is provided with two input inputs A and B, respectively receiving the input data after the original data input or the original data is interleaved, and the three shift registers are sequentially arranged in the output direction of the A channel in the output direction; There is a switch between the input end of the input terminal and the first shift register and the input end of the B channel. When the data starts to be input, the two switch switches are respectively closed to the original data input terminals of the A and B channels, completing all After the data is encoded, the two switches are switched to the other end; after the data input is completed, the two switches can be set to the ground terminal, or only the switch on the B road can be set to the ground terminal, so that the grounding terminal is set to zero. The output of each component code encoder includes not only the check bit corresponding to the data input, but also the tail bit and the check bit corresponding to the tail bit.

In practical applications, for each component code encoder, the positional relationship between the shift register and the adder and the switch can be arranged in a variety of ways, as long as the purpose of updating the register can be achieved, so-called peer update It means that the last data value stored in each register is added to the new data at the same time, and then stored in the next register in the order, and the stored contents in the register are updated. Each shift register is initialized to 0 and cleared to zero after each data encoding. Figure

4a and 4b to 11a and lib are the compositional structures of the first eight preferred component code encoder embodiments described above. Embodiment 1:

In this embodiment, the component code used is (11, 13), the feedback polynomial of the component code is represented as 11 in octal number, and the feedforward polynomial is represented as 13 in octal number. As shown in FIG. 4a, the component code encoder of this embodiment includes three shift registers, five adders, and a pair of switchers, and the component code encoder has two inputs A and B, at the input ends of the two channels. There is a separate switch. The adders are sequentially referred to as first to fifth adders in the direction of input to output, and the shift registers are sequentially referred to as first to third shift registers in the direction of input to output. The input of the B channel is simultaneously connected to the first, second, and fourth adders; on the A path, a first adder is disposed between the switch and the first shift register, and the first and second shift registers are disposed. There is a second adder, and a fourth adder is disposed between the second and third shift registers, the output of the first adder and the output of the second shift register are connected to the third adder, and the output of the third adder The output of the third shift register is coupled to the fifth adder; the output of the third shift register is also coupled to the first adder.

The switch on the A channel is switched between the original data input terminal and the output terminal of the third shift register, and the switch on the B switch is switched between the original data input terminal and the ground terminal.

When there is input data, the switch is respectively closed to the original data input terminals of the A and B channels, and the original input data A passes through the closed switch and the original input data B, and the output of the third shift register is in the first adder. The operation is performed, and the operation result is stored in the first shift register, and the operation result is input to the third adder; the output of the first shift register and the original input data B are operated in the second adder, and the operation result is stored in the second In the shift register; the output of the second shift register is input to the third adder, and the output of the first adder is operated in the third adder, and the operation result is output to the fifth adder; the second shift register is The output is simultaneously input to the fourth adder, and the original input data B is operated in the fourth adder, and the operation result is stored in the third shift register; the output of the third shift register and the output of the third adder are in the fifth The operation is performed in the adder, and the operation result is output as a check bit sequence; the output of the third shift register is fed back to the first adder.

After all the data is input and the code is completed, the switch of the A channel and the B channel are switched to the other end, and the switch of the A channel is connected with the output of the third shift register, and the switch of the B channel is connected and connected. The ground is connected. At this time, the output of the third shift register is output as the tail bit, and is simultaneously input to the first adder via the connected switch. The component code encoder clears the three registers by receiving three tail bits and performing the same processing as described above, thereby completing the grid image zeroing end operation. During the zeroing end operation, the output check bit is the check bit of the tail bit. Embodiment 2:

In this embodiment, the component code and the component device used are the same as those in the first embodiment, as shown in FIG. 4b, and the difference is: the position of the switch on the A road is different from that of the first adder, and the original input is different. The data A first enters the first adder, and the output of the first adder is input to the first shift register and the third adder through the closed switch; and the switch on the A channel is also provided with the ground terminal, at the switch Ground when switching.

The switch on the A channel is switched between the output of the first adder and the ground, and the switch on the B switch is switched between the original data input and the ground. Embodiment 3:

In this embodiment, the component code used is (11, 15), the feedback polynomial of the component code is represented by an octal number, and the feedforward polynomial is represented by an octal number of 15.

As shown in FIG. 5a, the component code encoder of this embodiment includes three shift registers, five adders, and a pair of switchers, and the component code encoder has two inputs A and B, at the input ends of the two channels. There is a separate switch. The adders are sequentially referred to as first to fifth adders in the direction of input to output, and the shift registers are sequentially referred to as first to third shift registers in the direction of input to output. The input of the B channel is simultaneously connected to the first, third, and fourth adders; on the A path, a first adder is disposed between the switch and the first shift register, and the first and second shift registers are disposed. There is a third adder, and a fourth adder is disposed between the second and third shift registers, the output of the first adder and the output of the first shift register are connected to the second adder, and the output of the second adder And an output of the third shift register is connected to the fifth adder; the third shift register The output of the device is also connected to the first adder.

When there is input data, the switch is respectively closed to the original data input terminals of the A and B channels, and the original input data A passes through the closed switch and the original input data B, and the output of the third shift register is in the first adder. The operation is performed, and the operation result is stored in the first shift register, and the operation result is input to the second adder; the output of the first shift register and the original input data B are operated in the third adder, and the operation result is stored in the second In the shift register; the output of the first shift register is input to the second adder, and the output of the first adder is operated in the second adder, and the operation result is output to the fifth adder; the second shift register is The output is input to the fourth adder, and the original input data B is operated in the fourth adder, and the operation result is stored in the third shift register; the output of the third shift register and the output of the second adder are in the fifth addition The operation is performed in the device, and the operation result is output as a check bit sequence; the output of the third shift register is fed back to the first adder.

When all the data is input and the code is completed, the switch of the A channel and the B channel are switched to the other end, the switch of the A channel is connected to the output of the third shift register, and the switch of the B channel is connected to the ground terminal. At this time, the output of the third shift register is output as the tail bit, and is simultaneously input to the first adder via the connected switch. The component code encoder clears the three registers by receiving three tail bits and performing the same processing as described above, thereby completing the grid image zeroing end operation. During the zeroing end operation, the output check bit is the check bit of the tail bit. Embodiment 4:

In this embodiment, the component code and the component device used are the same as those in the third embodiment, as shown in FIG. 5b, and the difference is: the position of the switch on the A road is different from that of the first adder, and the original input is different. Data A first enters the first adder, and the output of the first adder is switched again. The switch is input to the first shift register and the second adder; and, the switch on the A road is also provided with a ground terminal, and is grounded when the switch is switched.

The switch on the A channel is switched between the output of the first adder and the ground, and the switch on the B switch is switched between the original data input and the ground. Embodiment 5:

In this embodiment, the component code used is (13, 11), the feedback polynomial of the component code is represented by an octal number, and the feedforward polynomial is represented by an octal number of 11.

As shown in FIG. 6a, the component code encoder of this embodiment includes three shift registers, five adders, and a pair of switchers, and the component code encoder has two inputs A and B, at the input ends of the two channels. There is a separate switch. The adders are sequentially referred to as first to fifth adders in the direction of input to output, and the shift registers are sequentially referred to as first to third shift registers in the direction of input to output. The input of the B channel is simultaneously connected to the first, second, and fourth adders; on the A path, a first adder is disposed between the switch and the first shift register, and the first and second shift registers are disposed. There is a second adder, and a fourth adder is disposed between the second and third shift registers, the output of the first adder and the output of the third shift register are connected to the fifth adder, the second shift register and The output of the third shift register is coupled to a third adder; the output of the third adder is coupled to the first adder.

The switch on the A road switches between the original data input terminal and the output terminal of the third adder, and the switch on the B switch switches between the original data input terminal and the ground terminal.

When there is input data, the switch is respectively closed to the original data input terminals of the A and B channels, and the original input data A is passed through the closed switch and the original input data B, and the output of the third adder is made in the first adder. The operation result is stored in the first shift register, and the operation result is input to the fifth adder; the output of the first shift register and the original input data B are operated in the second adder, and the operation result is stored in the second shift In the bit register; the output of the second shift register is input to the fourth adder, and the original input data B is operated in the fourth adder, and the operation is performed The result is stored in the third shift register; the output of the second shift register is further input to the third adder, and the output of the third shift register is operated in the third adder, and the operation result is output to the first adder; The output of the third shift register and the output of the first adder are operated in a fifth adder, and the result of the operation is output as a check bit sequence.

When all the data is input and the code is completed, the switch of the A and B switches to the other end, the switch of the A is connected to the output of the third adder, and the switch of the B is connected to the ground. At this time, the output of the third shift register is output as the tail bit, and is simultaneously fed back to the first adder via the connected switching switch. The component code encoder clears the three registers by receiving three tail bits and performing the same processing as described above, thereby completing the grid image zeroing end operation. During the zeroing end operation, the output check bit is the check bit of the tail bit. Example 6:

In this embodiment, the component code and the component device used are the same as those in the fifth embodiment, as shown in FIG. 6b, the difference is: the position of the switch on the A road and the first adder are different from the fifth embodiment, the original input The data A first enters the first adder, and the output of the first adder is input to the first shift register and the fifth adder through the closed switch; and the switch on the A road is also provided with the ground terminal, at the switch Ground when switching.

The switch on the A channel is switched between the output of the first adder and the ground, and the switch on the B switch is switched between the original data input and the ground. Example 7:

In this embodiment, the component code used is (13, 15), the feedback polynomial of the component code is represented by an octal number, and the feedforward polynomial is represented by an octal number of 15. This component code is somewhat similar to the component code structure of the 3GPP Turbo code. The difference in this embodiment is: The component code is a Duo-binary coding mode, which adopts a dual-input structure; and uses a double-layer interleaver structure.

As shown in FIG. 7a, the component code encoder of this embodiment includes three shift registers, six adders, and a pair of switchers, and the component code encoder has two inputs of A and B, and inputs in two paths. The switch is provided with a switch. The adders are sequentially referred to as first to sixth adders in the direction of input to output, and the shift registers are sequentially referred to as first to third shift registers in the direction of input to output. The input of the B channel is simultaneously connected to the first, third, and fifth adders; on the A path, a first adder is disposed between the switch and the first shift register, and the first and second shift registers are set There is a third adder, and a fifth adder is disposed between the second and third shift registers, the output of the first adder and the output of the first shift register are connected to the second adder, and the output of the second adder The output of the third shift register is coupled to the sixth adder; the outputs of the second shift register and the third shift register are coupled to a fourth adder; the output of the fourth adder is coupled to the first adder.

The switch on the A channel switches between the original data input terminal and the output terminal of the fourth adder, and the switch on the B switch switches between the original data input terminal and the ground terminal.

When there is input data, the switch is closed to the original data input terminals of the A and B channels respectively, and the original input data A is passed through the closed switch and the original input data B, and the output of the fourth adder is made in the first adder. The operation result is stored in the first shift register, and the operation result is input to the second adder; the output of the first shift register and the original input data B are operated in the third adder, and the operation result is stored in the second shift In the bit register; the output of the first shift register is input to the second adder, and the output of the first adder is operated in the second adder, and the operation result is output to the sixth adder; the output of the second shift register Input to the fifth adder, and the original input data B is operated in the fifth adder, the operation result is stored in the third shift register; the output of the second shift register is input to the fourth adder, and the third shift The output of the register is operated in the fourth adder, and the result of the operation is sent to the first adder; the output of the third shift register and the output of the second adder A sixth adder operation done, the operation result as a parity bit output bit sequence.

After all the data is input and the code is completed, the switch of the A and B roads is switched to the other end, and the switch of the A channel is connected with the output of the fourth adder, and the switch of the B channel and the ground end are connected. Connected. At this time, the output of the fourth adder is output as the tail bit, and is simultaneously input to the first adder via the connected switch. The component code encoder clears the three registers by receiving three tail bits and performing the same processing as described above, thereby completing the grid image zeroing end operation. During the zeroing end operation, the output check bit is the check bit of the tail bit. Example 8:

In this embodiment, the component code and the component device used are the same as those in the seventh embodiment, as shown in FIG. 7b, and the difference is: the position of the switch on the A road is different from that of the first adder, and the original input is different. The data A first enters the first adder, and the output of the first adder is input to the first shift register and the second adder through the closed switch; and the switch on the A road is also provided with the ground terminal, at the switch Ground when switching.

The switch on the A channel is switched between the output of the first adder and the ground, and the switch on the B switch is switched between the original data input and the ground. Example 9:

In this embodiment, the component code used is (13, 17), the feedback polynomial of the component code is represented by an octal number, and the feedforward polynomial is represented by an octal number of 17.

As shown in FIG. 8a, the component code encoder of this embodiment includes three shift registers, seven adders, and a pair of switchers having two inputs A and B, at the input of the two channels. There is a separate switch. Wherein, the adder is sequentially referred to as the first to seventh adders in the direction of input to output, and the two adders in the same node are the adders with the preceding number in the upper direction, and the shift registers are sequentially input to the output direction. They are called first to third shift registers. The input of the B channel is simultaneously connected to the first, third, and sixth adders; on the A, a first adder is disposed between the switch and the first shift register, and the first and second shift registers are set There is a third adder, and a sixth adder is disposed between the second and third shift registers, the output of the first adder and the output of the first shift register are connected to the second adder, and the output of the second adder And an output of the second shift register is connected to the fourth adder; the output of the fourth adder and the third shift The output of the register is coupled to a seventh adder; the outputs of the second shift register and the third shift register are coupled to a fifth adder; the output of the fifth adder is coupled to the first adder.

The switch on the A channel switches between the original data input terminal and the output terminal of the fifth adder, and the switch on the B switch switches between the original data input terminal and the ground terminal.

When there is input data, the switch is closed to the original data input terminals of the A and B channels, and the original input data A is passed through the closed switch and the original input data B, and the output of the fifth adder is made in the first adder. The operation result is stored in the first shift register, and the operation result is input to the second adder; the output of the first shift register and the original input data B are operated in the third adder, and the operation result is stored in the second shift In the bit register; the output of the first shift register is input to the second adder, and the output of the first adder is operated in the second adder, and the operation result is output to the fourth adder; the output of the second shift register Input to the sixth adder, and the original input data B is operated in the sixth adder, the operation result is stored in the third shift register; the output of the second shift register is input to the fifth adder, and the third shift The output of the register is operated in the fifth adder, and the result of the operation is sent to the first adder; the output of the second shift register is also input to the fourth adder And the output of the second adder is operated in the fourth adder, and the operation result is sent to the seventh adder; the output of the third shift register and the output of the fourth adder are operated in the seventh adder, and the operation result Output as a check bit sequence.

When all the data is input and the code is completed, the switch of A and B switches to the other end, the switch of A is connected to the output of the fifth adder, and the switch of B is connected to the ground. At this time, the output of the fifth adder is output as the tail bit, and is simultaneously input to the first adder via the connected switching switch feedback. The component code encoder clears the three registers by receiving three tail bits and performing the same processing as described above, thereby completing the grid image zeroing end operation. During the return-to-zero operation, the output check bit is the check bit of the tail bit. Example 10:

In this embodiment, the component code and the component device used are the same as those in the embodiment 9, as shown in FIG. 8b. As shown, the difference is: the switch on the A path is different from the position of the first adder and the embodiment 9. The original input data A first enters the first adder, and the output of the first adder is input to the closed switch. The first shift register and the second adder; and, the switch on the A road is also provided with a ground terminal, and is grounded when the switch is switched.

The switch on the A channel is switched between the output of the first adder and the ground, and the switch on the B switch is switched between the original data input and the ground. Example 11:

In this embodiment, the component code used is (15, 11), the feedback polynomial of the component code is expressed as an octal number, and the feedforward polynomial is expressed as an octal number.

As shown in FIG. 9a, the component code encoder of this embodiment includes three shift registers, five adders, and a pair of switchers, and the component code encoder has two inputs A and B, at the input ends of the two channels. There is a separate switch. The adders are sequentially referred to as first to fifth adders in the direction of input to output, and the shift registers are sequentially referred to as first to third shift registers in the direction of input to output. The input of the B channel is simultaneously connected to the first, third, and fourth adders; on the A path, a first adder is disposed between the switch and the first shift register, and the first and second shift registers are disposed. There is a third adder, a fourth adder is disposed between the second and third shift registers, and an output of the first adder and an output of the third shift register are connected to the fifth adder; the first shift register and The output of the third shift register is coupled to a second adder; the output of the second adder is coupled to the first adder.

The switch on the A road switches between the original data input end and the output end of the second adder, and the switch on the B line switches between the original data input end and the ground end.

When there is input data, the switch is respectively closed to the original data input terminals of the A and B channels, and the original input data A is passed through the closed switch and the original input data B, and the output of the second adder is made in the first adder. The operation result is stored in the first shift register, and the operation result is input to the fifth adder; the output of the first shift register and the original input data B are in the third addition The operation is performed in the normalizer, and the operation result is stored in the second shift register; the output of the first shift register is input to the second adder, and the output of the third shift register is operated in the second adder, and the operation result Output to the first adder; the output of the second shift register is input to the fourth adder, and the original input data B is operated in the fourth adder, and the operation result is stored in the third shift register; the third shift register The output of the first adder is operated in the fifth adder, and the result of the operation is output as a check bit sequence.

When all the data is input and the code is completed, the switch of A and B switches to the other end, the switch of A is connected to the output of the second adder, and the switch of B is connected to the ground. At this time, the output of the second adder is output as the tail bit, and is simultaneously input to the first adder via the connected switching switch feedback. The component code encoder clears the three registers by receiving three tail bits and performing the same processing as described above, thereby completing the grid image zeroing end operation. During the return-to-zero operation, the output check bit is the check bit of the tail bit. Example 12:

In this embodiment, the component code and the component device used are the same as those in the eleventh embodiment, as shown in FIG. 9b, the difference is that the position of the switch on the A road and the first adder are different from the eleventh embodiment. The original input data A first enters the first adder, and the output of the first adder is input to the first shift register and the fifth adder through the closed switch; and the switch on the A road is also provided with the ground terminal, Ground when the switch is switched.

The switch on the A channel is switched between the output of the first adder and the ground, and the switch on the B switch is switched between the original data input and the ground. Example 13:

In this embodiment, the component code used is (15, 13), the feedback polynomial of the component code is represented by an octal number, and the feedforward polynomial is represented by an octal number of 13.

As shown in FIG. 10a, the component code encoder of this embodiment includes three shift registers, six adders, and a pair of switchers, and the component code encoder has two inputs of A and B, in two paths. A switch is provided at the input end. The adders are sequentially referred to as first to sixth adders in the direction of input to output, and the shift registers are sequentially referred to as first to third shift registers in the direction of input to output. The input of the B channel is simultaneously connected to the first, third, and fifth adders; on the A path, a first adder is disposed between the switch and the first shift register, and the first and second shift registers are set There is a third adder, a fifth adder is disposed between the second and third shift registers, and an output of the first adder and an output of the second shift register are connected to the fourth adder; an output of the fourth adder And an output of the third shift register is coupled to the sixth adder; the outputs of the first shift register and the third shift register are coupled to the second adder; the output of the second adder is coupled to the first adder.

When there is input data, the switch is respectively closed to the original data input terminals of the A and B channels, and the original input data A is passed through the closed switch and the original input data B, and the output of the second adder is made in the first adder. The operation result is stored in the first shift register, and the operation result is input to the fourth adder; the output of the first shift register and the original input data B are operated in the third adder, and the operation result is stored in the second shift In the bit register; the output of the first shift register is input to the second adder, and the output of the third shift register is operated in the second adder, and the operation result is output to the first adder; the second shift register is The output is input to the fifth adder, and the original input data B is operated in the fifth adder, and the operation result is stored in the third shift register; the output of the second shift register and the output of the first adder are in the fourth addition The operation is performed, and the operation result is output to the sixth adder; the output of the third shift register and the output of the fourth adder are operated in the sixth adder The result of the operation is output as a check bit sequence.

When all the data is input and the code is completed, the switches of the A and B switches are switched to the other end, the switch of the A channel is connected to the output of the second adder, and the switch of the B channel is connected to the ground. At this time, the output of the second adder is output as the tail bit, and is switched on and off at the same time. The feedback is input to the first adder. The component code encoder clears the three registers by receiving three tail bits and performing the same processing as described above, thereby completing the grid image zeroing end operation. During the zeroing end operation, the output check bit is the check bit of the tail bit. Embodiment 14:

In this embodiment, the component code and the component device used are the same as those in the thirteenth embodiment, as shown in the figure.

10b, the difference is: the switch on the A road is different from the position of the first adder and the thirteenth embodiment, the original input data A first enters the first adder, and the output of the first adder passes through the closed switch Input to the first shift register and the fourth adder; and, the switch on the A road is also provided with a ground terminal, and is grounded when the switch is switched.

The switch on the A channel is switched between the output of the first adder and the ground, and the switch on the B switch is switched between the original data input and the ground. Example 15:

In this embodiment, the component code used is (15, 17), the feedback polynomial of the component code is represented by an octal number, and the feedforward polynomial is represented by an octal number of 17.

As shown in FIG. 11a, the component code encoder of this embodiment includes three shift registers, seven adders, and a pair of switchers, and the component code encoder has two inputs A and B, at the input ends of the two channels. There is a separate switch. Wherein, the adder is sequentially referred to as the first to seventh adders in the direction of input to output, and the two adders in the same node are the adders with the preceding number in the upper direction, and the shift registers are sequentially input to the output direction. They are called first to third shift registers. The input of the B channel is simultaneously connected to the first, fourth, and sixth adders; on the A, a first adder is disposed between the switch and the first shift register, and the first and second shift registers are set There is a fourth adder, and a sixth adder is disposed between the second and third shift registers, the output of the first adder and the output of the first shift register are connected to the second adder, and the output of the second adder And an output of the second shift register is connected to the fifth adder; an output of the fifth adder and an output of the third shift register are connected to the seventh adder; the input of the first shift register and the third shift register The output is connected to the third adder; the output of the third adder is connected to the first adder.

When there is input data, the switch is respectively closed to the original data input terminals of the A and B channels, and the original input data A is passed through the closed switch and the original input data B, and the output of the third adder is made in the first adder. The operation result is stored in the first shift register, and the operation result is input to the second adder; the output of the first shift register and the original input data B are operated in the fourth adder, and the operation result is stored in the second shift In the bit register; the output of the first shift register is input to the second adder, and the output of the first adder is operated in the second adder, and the operation result is output to the fifth adder; the output of the second shift register Input to the sixth adder, and the original input data B is operated in the sixth adder, and the operation result is stored in the third shift register; the output of the first shift register is input to the third adder, and the third shifter The output of the register is operated in the third adder, and the result of the operation is sent to the first adder; the output of the third shift register and the output of the fifth adder A seventh adder operation done, the operation result as a parity bit output bit sequence.

When all the data is input and the code is completed, the switch of the A and B switches to the other end, the switch of the A is connected to the output of the third adder, and the switch of the B is connected to the ground. At this time, the output of the third adder is output as the tail bit, and is simultaneously input to the first adder via the connected switching switch feedback. The component code encoder clears the three registers by receiving three tail bits and performing the same processing as described above, thereby completing the grid image zeroing end operation. During the return-to-zero operation, the output check bit is the check bit of the tail bit. Example 16:

In this embodiment, the component code and the component device used are the same as those in the fifteenth embodiment, as shown in FIG. 1 ib, except that the position of the switch on the A road is different from that of the first adder and the fifteenth embodiment. The original input data A first enters the first adder, and the output of the first adder is closed again. The switch is input to the first shift register and the second adder; and the switch on the A road is also provided with a ground terminal, and is grounded when the switch is switched.

The switch on the A channel is switched between the output of the first adder and the ground, and the switch on the B switch is switched between the original data input and the ground.

The generator polynomial of each of the above component codes uses a feedforward polynomial. In practical applications, two or more different feedforward polynomials described above can also be used simultaneously to form other new component codes, which can provide more Check bit output for better performance. The following nine new component codes are also selected in the embodiment of the present invention:

1 component code is ( 11, 13, 15 )

The feedback of the component code ^ : is expressed as an octal number as 11, and the feedforward polynomial is represented by octal numbers as 13 and 15.

2 component code is (13, 11, 15)

The feedback of the component code ^ : is expressed as an octal number as 13, and the feedforward polynomial is expressed as octal numbers 11 and 15.

3 component code is (13, 11, 17)

The feedback of the component code ^ : is expressed as an octal number as 13, and the feedforward polynomial is expressed as octal numbers 11 and 17.

4 component code is (13, 15, 17)

The feedback of the component code ^ : is expressed as an octal number as 13, and the feedforward polynomial is expressed as octal numbers 15 and 17.

5 component code is (13, 11, 15, 17)

The feedback of the component code ^ is expressed as an octal number of 13, and the feedforward polynomial is represented by octal numbers as 11, 15, and 17. Expressed as 11 and 13.

7 component code is (15, 11, 17)

The feedback polynomial of the component code is expressed as an octal number, and the feedforward polynomial is represented by octal numbers as 11 and 17.

8 component code is (15, 13, 17)

The feedback polynomial of the component code is expressed as an octal number, and the feedforward polynomial is represented by octal numbers as 13 and 17.

9 component code is ( 15, 11, 13, 17 )

The feedback polynomial of the component code is expressed as an octal number, and the feedforward polynomial is expressed as octal numbers 11, 13, and 17.

These nine component codes all have 2 or more check digit outputs, which provide better performance and a wider selection of encoding rates. These nine component codes simultaneously use a plurality of feedforward polynomials of eight component codes in Figs. 4 to 11. Therefore, in the coding structures of the nine component codes, all of the feedforward polynomials are identical to the feedforward polynomials of the eight component codes in FIGS. 4 to 11; and, each of the nine component codes The component code encoders also have the two schemes a and b of FIGS. 4 to 11, respectively.

In the above component code encoder, the embodiment of the present invention uses a tail bit to perform a truncated binary termination method (tail bits termination), and eight preferred component codes as shown in FIG. 4 to FIG. The encoder's grid map zeroing end method, shown as a dashed line.

In the implementation scheme a shown in FIG. 4 to FIG. 11, after all the data blocks are input, the component code encoder uses a pair of switchers to disconnect the original data input terminal and connect with the other two ends, BP : The input of the A channel is connected to the feedback input of the tail bit, and the input of the B channel is connected to the ground terminal for zero setting. Thus, the component code encoder receives the feedback of the three tail bits, completes the grid map zeroing end operation, and simultaneously outputs three tail bits and three parity bits corresponding to the tail bits.

In the implementation scheme b of FIG. 4 to FIG. 11, after all the data blocks are input, the component code is compiled. The encoder uses a pair of diverter switches to disconnect the data input and connect the pair of diverters to the ground. At this time, the component code encoder does not need to receive the feedback of the tail bits, and can complete the grid image zeroing end operation, and simultaneously output three tail bits and three check bit bits corresponding to the tail bits.

The 17 component codes used in the embodiments of the present invention can adopt the two grid pattern zeroing end methods of the foregoing implementation schemes a and b.

The two-layer interleaver 33 of the embodiment of the present invention further includes an outer interleaving unit and an inner interleaving unit, respectively performing outer layer interleaving and inner layer interleaving on the original data block. Different from the WiMAX CTC code interleaver, the interleaver used in the embodiment of the present invention is based on a quadratic permutation polynomial (QPP), and the outer interleaving adopts the formula (1):

The inner layer interleaving adopts a process of performing inner layer interleaving processing according to the value of i. When i mod 2 = 0, the two paths of the original data input (Α, Β^ exchange position, become (Β^Α), Placed in the jth paired position after the outer layer is interwoven. The inner layer interlacing can be expressed as:

For i = 0, ..., Ν-1

If (i mod 2 == 0) , let (B _i5 Ai) = (A _i5 Bi) (ie, switch the couple ) where i=0, -, N-1 , i is the original data block pair position number ; j=0, -, N-1, j are the paired position numbers of the data block after outer layer interleaving and inner layer interleaving; N is the pairwise number of data blocks; and the coefficient of the quadratic permutation polynomial can be passed Computer search, optimized to get.

In the two-layer interleaving structure of the embodiment of the present invention, the j-th paired bits of the interleaved data block are taken from the i-th pair of bits of the original data block. The outer layer interleaving is inter-couple interleaving, and the original data block is interleaved in a pairwise manner using a quadratic permutation polynomial (QPP) to keep the relative positions of the paired bits (A, B) unchanged. The inner layer is interlaced as intra-couple permutation. When the paired position numbers of the original data block are even, the paired bits (A, B) are interchanged, and the paired bits at the odd positions ( A, B) The relative position is fixed. Compared with the 3GPP Turbo code and the WiMAX Turbo code, the performance of the embodiment of the present invention is better, and the coding complexity and the decoding complexity are relatively small. The performance effects of the embodiments of the present invention are illustrated by three simulation examples, and performance comparisons are performed with 3GPP Turbo codes and WiMAX Turbo codes.

In the first example, the original data block size is 1920 bits; the code rate R is 1/2 (the tail bit and its check bit are not counted); BPSK modulation is used; the decoding algorithm uses the Max-Log-MAP algorithm, the number of iterations 8 times; the channel model is the AWGN channel; the QPP polynomial coefficient and the QPP interleaver coefficient of the reference LTE. In this example, the eight component code encoders described in Embodiments 1 through 16 are used, and the generator polynomial is represented by octal numbers as (11, 13), (11, 15), (13, 11), (13, 15), (13,17), (15,11), (15,13), (15,17). In addition, the performance of 3GPP Rel.6 Turbo code, LTE Turbo code and WiMAX Turbo code under the same assumptions is also given, in which 3GPP Rel.6 Turbo code and LTE Turbo code need to be punctured to achieve The code rate is 1/2. The punching method is [11; 10; 01] uniform, symmetrical punching.

In Figure 12, the abscissa is the signal-to-noise ratio (Eb/No), in dB, the ordinate is the block error rate (BLER), and the 11 curves are 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209. , 1210, 1211 are sequentially given the use of component codes (11, 13), (11, 15), (13, 11), (13, 15), (13, 17), (15, 11), (15, 13), (15, 17) Turbo code performance curve, and performance curves of 3GPP Rel.6 Turbo code, LTE Turbo code and WiMAX Turbo code.

As can be seen from FIG. 12, the turbo coding apparatus and method of the embodiment of the present invention generally have better performance than the 3GPP Rel.6 Turbo code, the LTE Turbo code, and the WiMAX Turbo code. In addition, the obvious disadvantage of WiMAX Turbo codes is that the coding and decoding complexity is relatively large, and the coding and decoding complexity of the embodiments of the present invention are relatively small.

The second example and the third example are simulated with the original data block size of 96 bits and the original data block size of about 4800 bits. The other assumptions are the same as the first example. The results show that the performance of the Turbo code coding apparatus and method in the embodiment of the present invention is superior to the 3GPP Rel. 6 Turbo code, LTE Turbo code and WiMAX Turbo code in the prior art. The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention.

Claims

Claim

A turbo code encoding apparatus, the device comprising: a first component code encoder, a second component code encoder, and an interleaver;

a first component code encoder, which receives the paired input raw data A, B, and outputs a check bit sequence Y1 and a tail bit sequence Z1;

The paired input raw data A, B are output as a systematic bit pair.

2. The turbo code encoding apparatus according to claim 1, wherein the first component code encoder and the second component code encoder use the same component code encoding structure;

The coding structure of the component code used includes a feedback polynomial and one or more feedforward polynomials, the one or more feedforward polynomials being different feedforward polynomials.

3. The turbo code encoding apparatus according to claim 2, wherein:

When the component code code uses a feedforward polynomial and a feedback polynomial, the component codes used are (11, 13), (11, 15), (13, 11), (13, 15), (13, 17), (15, 11), (15, 13), (15, 17);

When the component code encoding uses two feedforward polynomials and one feedback polynomial, the component codes used are (11, 13, 15), (13, 11, 15), (13, 11, 17), (13 , 15, 17), (15, 11, 13), (15, 11, 17), (15, 13, 17);

When the component code encoding uses three feedforward polynomials and one feedback polynomial, the component code used is any one of (13, 11, 15, 17), (15, 11, 13, 17);

The first parameter in each parenthesis is a feedback polynomial of the component code represented by an octal number, and the remaining parameters are feedforward polynomials of the component code expressed in octal numbers.

4. The turbo code encoding apparatus according to claim 2, wherein each component code encoder comprises three shift registers, five or more adders, and a pair of switching switches; each of said components The code encoder is provided with two inputs, and the pair of switch switches are respectively disposed on one input; the three shift registers are sequentially arranged along the input to the output direction on one path.

The turbo code encoding apparatus according to claim 4, wherein the component code used by each component code encoder is (11, 13);

Each of the component code encoders includes three shift registers, five adders, and a pair of switchers, the component code encoders having two inputs A and B, each of which is provided with a switch; The input is simultaneously connected to the first, second, and fourth adders; on the A, a first adder is disposed between the switch and the first shift register, and a second is disposed between the first and second shift registers The adder, the fourth adder is disposed between the second and third shift registers, the output of the first adder and the output of the second shift register are connected to the third adder, and the output of the third adder and the third The output of the shift register is connected to the fifth adder; the output of the third shift register is also connected to the first adder;

The switch on the A channel switches between the original data input terminal and the output terminal of the third shift register, and the switch on the B switch switches between the original data input terminal and the ground terminal; when there is input data, the A channel and the B channel The switch of the road is closed to the original data input. When all the data is input and the code is completed, the switch is switched to the other end.

Each of the component code encoders includes three shift registers, five adders, and a pair of switchers, the component code encoders having two inputs A and B, each of which is provided with a switch; The input is simultaneously connected to the first, second, and fourth adders; on the A, a first adder is disposed between the original data input end and the switch, and the switch is connected to the first adder and the first shift register. Between; the first and second shift registers are provided with a second adder, second, A fourth adder is disposed between the third shift register, the output of the first adder and the output of the second shift register are connected to the third adder, and the output of the third adder is connected to the output of the third shift register Up to a fifth adder; the output of the third shift register is further connected to the first adder;

The switches on the A and B roads are switched between the original data input terminal and the ground terminal; when there is input data, the switch switches of the A and B channels are closed to the original data input terminal, and all the data is input and the code is completed. After that, the switch is switched to the ground.

The turbo code encoding apparatus according to claim 4, wherein the component code used by each component code encoder is (11, 15);

Each of the component code encoders includes three shift registers, five adders, and a pair of switchers, the component code encoders having two inputs A and B, each of which is provided with a switch; The input is simultaneously connected to the first, third, and fourth adders; on the A, a first adder is disposed between the switch and the first shift register, and a third is disposed between the first and second shift registers An adder, a fourth adder is disposed between the second and third shift registers, an output of the first adder and an output of the first shift register are connected to the second adder, and an output of the second adder and the third The output of the shift register is connected to the fifth adder; the output of the third shift register is also connected to the first adder;

Each of the component code encoders includes three shift registers, five adders, and a pair of switchers, the component code encoders having two inputs A and B, each of which is provided with a switch; Input is connected to the first, third, and fourth adders at the same time; on the A, the raw data is input a first adder is disposed between the end and the switch, the switch is connected between the first adder and the first shift register, and the third adder is disposed between the first and second shift registers, the second A fourth adder is disposed between the third shift register, the output of the first adder and the output of the first shift register are connected to the second adder, and the output of the second adder is connected to the output of the third shift register Up to a fifth adder; the output of the third shift register is further connected to the first adder;

The turbo code encoding apparatus according to claim 4, wherein the component code used by each component code encoder is (13, 11);

Each of the component code encoders includes three shift registers, five adders, and a pair of switchers, the component code encoders having two inputs A and B, each of which is provided with a switch; The input is simultaneously connected to the first, second, and fourth adders; on the A, a first adder is disposed between the switch and the first shift register, and a second is disposed between the first and second shift registers An adder, a fourth adder is disposed between the second and third shift registers, and an output of the first adder and an output of the third shift register are connected to the fifth adder, the second shift register and the third shift The output of the bit register is coupled to the third adder; the output of the third adder is coupled to the first adder;

The switch on the A road switches between the original data input end and the output end of the third adder, and the switch on the B line switches between the original data input end and the ground end; when there is input data, the A and B roads The switch is closed to the original data input. When all the data is input and the code is completed, the switch is switched to the other end.

Each of the component code encoders includes three shift registers, five adders, and a pair of switching a switch, the component code encoder has two inputs A and B, each of which is provided with a switch; the input of the B channel is simultaneously connected to the first, second, and fourth adders; on the A, at the original data input end A first adder is disposed between the switch and the switch, and the switch is connected between the first adder and the first shift register, and the second adder is disposed between the first and second shift registers, the second and the second A fourth adder is disposed between the three shift registers, the output of the first adder and the output of the third shift register are connected to the fifth adder, and the outputs of the second shift register and the third shift register are connected to the a triple adder; the output of the third adder is connected to the first adder;

The turbo code encoding apparatus according to claim 4, wherein the component code used by each component code encoder is (13, 15);

Each of the component code encoders includes three shift registers, six adders, and a pair of switchers, the component code encoders having two inputs A and B, each of which is provided with a switch; The input is simultaneously connected to the first, third, and fifth adders; on the A, a first adder is disposed between the switch and the first shift register, and a third is disposed between the first and second shift registers An adder, a fifth adder is disposed between the second and third shift registers, an output of the first adder and an output of the first shift register are connected to the second adder, and an output of the second adder and the third An output of the shift register is coupled to the sixth adder; an output of the second shift register and the third shift register is coupled to the fourth adder; an output of the fourth adder is coupled to the first adder;

The switch on the A road is switched between the original data input end and the output end of the fourth adder, and the switch on the B line is switched between the original data input end and the ground end; when there is input data, the A and B roads The switch is closed to the original data input. When all the data is input and the code is completed, the switch is switched to the other end.

The turbo code encoding apparatus according to claim 4, wherein each of said each The component code used by the component code encoder is (13, 15);

Each of the component code encoders includes three shift registers, six adders, and a pair of switchers, the component code encoders having two inputs A and B, each of which is provided with a switch; The input is simultaneously connected to the first, third, and fifth adders; on the A, a first adder is disposed between the original data input end and the switch, and the switch is connected to the first adder and the first shift register. A third adder is disposed between the first and second shift registers, and a fifth adder is disposed between the second and third shift registers, an output of the first adder and an output of the first shift register Connected to the second adder, the output of the second adder and the output of the third shift register are connected to the sixth adder; the outputs of the second shift register and the third shift register are connected to the fourth adder; The output of the adder is connected to the first adder;

The turbo code encoding apparatus according to claim 4, wherein the component code used by each component code encoder is (13, 17);

Each of the component code encoders includes three shift registers, seven adders, and a pair of switchers, the component code encoders having two inputs A and B, each of which is provided with a switch; The input is simultaneously connected to the first, third, and sixth adders; on the A, a first adder is disposed between the switch and the first shift register, and a third is disposed between the first and second shift registers An adder, a sixth adder is disposed between the second and third shift registers, an output of the first adder and an output of the first shift register are connected to the second adder, and the output of the second adder is second The output of the shift register is coupled to the fourth adder; the output of the fourth adder and the output of the third shift register are coupled to the seventh adder; the outputs of the second shift register and the third shift register are coupled to the fifth An adder; the output of the fifth adder is connected to the first adder;

The switch on the A switch switches between the raw data input and the output of the fifth adder. The switch on the B line switches between the original data input terminal and the ground terminal; when there is input data, the switch of the A channel and the B channel is closed to the original data input terminal, and when all the data is input and the code is completed, the switch is switched. Switch to the other end.

Each of the component code encoders includes three shift registers, seven adders, and a pair of switchers, the component code encoders having two inputs A and B, each of which is provided with a switch; The input is simultaneously connected to the first, third, and sixth adders; on the A, a first adder is disposed between the original data input end and the switch, and the switch is connected to the first adder and the first shift register. a third adder is disposed between the first and second shift registers, and a sixth adder is disposed between the second and third shift registers, an output of the first adder and an output of the first shift register Connected to the second adder, the output of the second adder and the output of the second shift register are connected to the fourth adder; the output of the fourth adder and the output of the third shift register are connected to the seventh adder; The outputs of the second shift register and the third shift register are connected to the fifth adder; the output of the fifth adder is connected to the first adder;

The turbo code encoding apparatus according to claim 4, wherein the component code used by each component code encoder is (15, 11);

Each of the component code encoders includes three shift registers, five adders, and a pair of switchers, the component code encoders having two inputs A and B, each of which is provided with a switch; The input is simultaneously connected to the first, third, and fourth adders; on the A, a first adder is disposed between the switch and the first shift register, and a third is disposed between the first and second shift registers An adder, a fourth adder is disposed between the second and third shift registers, and the first adder The output of the third shift register is coupled to the fifth adder; the outputs of the first shift register and the third shift register are coupled to the second adder; the output of the second adder is coupled to the first adder;

The switch on the A road switches between the original data input end and the output end of the second adder, and the switch on the B line switches between the original data input end and the ground end; when there is input data, the A and B roads The switch is closed to the original data input. When all the data is input and the code is completed, the switch is switched to the other end.

Each of the component code encoders includes three shift registers, five adders, and a pair of switchers, the component code encoders having two inputs A and B, each of which is provided with a switch; The input is simultaneously connected to the first, third, and fourth adders; on the A, a first adder is disposed between the original data input end and the switch, and the switch is connected to the first adder and the first shift register. A third adder is disposed between the first and second shift registers, and a fourth adder is disposed between the second and third shift registers, an output of the first adder and an output of the third shift register Connected to the fifth adder; the outputs of the first shift register and the third shift register are connected to the second adder; the output of the second adder is connected to the first adder;

The turbo code encoding apparatus according to claim 4, wherein the component code used by each component code encoder is (15, 13);

Each of the component code encoders includes three shift registers, six adders, and a pair of switchers, the component code encoders having two inputs A and B, each of which is provided with a switch; Input is connected to the first, third, and fifth adders at the same time; on the A, in the switch and the first A first adder is disposed between the shift registers, a third adder is disposed between the first and second shift registers, and a fifth adder is disposed between the second and third shift registers, the first addition The output of the second shift register is coupled to the fourth adder; the output of the fourth adder and the output of the third shift register are coupled to a sixth adder; a first shift register and a third shift register The output is connected to the second adder; the output of the second adder is connected to the first adder;

Each of the component code encoders includes three shift registers, six adders, and a pair of switchers, the component code encoders having two inputs A and B, each of which is provided with a switch; The input is simultaneously connected to the first, third, and fifth adders; on the A, a first adder is disposed between the original data input end and the switch, and the switch is connected to the first adder and the first shift register. A third adder is disposed between the first and second shift registers, and a fifth adder is disposed between the second and third shift registers, an output of the first adder and an output of the second shift register Connected to the fourth adder; the output of the fourth adder and the output of the third shift register are connected to the sixth adder; the outputs of the first shift register and the third shift register are connected to the second adder; The output of the adder is connected to the first adder;

The turbo code encoding apparatus according to claim 4, wherein the component code used by each component code encoder is (15, 17); Each of the component code encoders includes three shift registers, seven adders, and a pair of switchers, the component code encoders having two inputs A and B, each of which is provided with a switch; The input is simultaneously connected to the first, fourth, and sixth adders; on the A, a first adder is disposed between the switch and the first shift register, and a fourth is disposed between the first and second shift registers An adder, a sixth adder is disposed between the second and third shift registers, an output of the first adder and an output of the first shift register are connected to the second adder, and the output of the second adder is second The output of the shift register is coupled to the fifth adder; the output of the fifth adder and the output of the third shift register are coupled to the seventh adder; the outputs of the first shift register and the third shift register are coupled to the third An adder; the output of the third adder is coupled to the first adder;

The turbo code encoding apparatus according to claim 4, wherein the component code used by each component code encoder is (15, 17);

Each of the component code encoders includes three shift registers, seven adders, and a pair of switchers, the component code encoders having two inputs A and B, each of which is provided with a switch; The input is simultaneously connected to the first, fourth, and sixth adders; on the A, a first adder is disposed between the original data input end and the switch, and the switch is connected to the first adder and the first shift register. A fourth adder is disposed between the first and second shift registers, and a sixth adder is disposed between the second and third shift registers, an output of the first adder and an output of the first shift register Connected to the second adder, the output of the second adder and the output of the second shift register are connected to the fifth adder; the output of the fifth adder and the output of the third shift register are connected to the seventh adder; An output of a shift register and a third shift register is coupled to a third adder; an output of the third adder is coupled to the first adder; The switches on the A and B roads are switched between the original data input terminal and the ground terminal; when there is input data, the switch switches of the A and B channels are closed to the original data input terminal, and all the data is input and the code is completed. After that, the switch is switched to the ground.

The turbo code encoding apparatus according to claim 1, wherein the interleaver further comprises an outer interleaving unit and an inner interleaving unit, respectively performing outer layer interleaving and inner layer interleaving on the original data block.

The turbo code encoding apparatus according to claim 21, wherein the outer layer interleaving unit is configured to implement an interleaving process based on a quadratic permutation polynomial;

The inner layer interleaving unit is configured to perform position exchange of two pairs of data bits in an even pair position of the original data block.

23. A Turbo code encoding method, the method comprising:

The turbo code encoding method according to claim 23, wherein the parity bit sequence Y1, Υ2 includes a parity bit of a systematic bit bit and a parity bit of a tail bit.

The turbo code encoding method according to claim 23, wherein the first quantized code is encoded and the second component code is encoded, and three tail bits and their corresponding check bit bits are respectively output.

The turbo code encoding method according to claim 23, wherein the interleaving process comprises: outer layer interleaving processing based on a quadratic permutation polynomial; and pairwise in an even pair position of the original data block Two layers of data bits for inner layer interleaving processing for position exchange; The quadratic permutation polynomial used in the outer layer interleaving process is 1 = (frj + f _{2 -} j ² ) mod N; the inner layer interleaving process is: when the i value satisfies imod2 = 0, the i data is input to the i th Two pairs of pairs (Α, Β^ exchange position, become (Β^Α), placed in the jth paired position after the outer layer is interwoven;

Where i is the paired position number of the original data block, j is the paired position number of the data block after outer layer interleaving and inner layer interleaving, N is the pairwise number of data blocks, and is the quadratic permutation polynomial coefficient.

The turbo code encoding method according to claim 23, wherein each of the component code codes uses one or more feedforward polynomials and a feedback polynomial, and the one of the above feedforward polynomials is a different feedforward polynomial.

The turbo code encoding method according to claim 27, wherein when the component code encoding uses a feedforward polynomial and a feedback polynomial, the component codes used are (11, 13), (11, 15), (13, 11), (13, 15), (13, 17), (15, 11), (15, 13), (15, 17);

Wherein, the first parameter in each parenthesis is a feedback polynomial of the component code represented by an octal number, and the remaining parameters are feedforward polynomials of the component code expressed in octal numbers.

A Turbo code coding interleaver, comprising: an outer layer interleaving unit and an inner layer interleaving unit, respectively performing outer layer interleaving and inner layer interleaving on the original data block.

The turbo code encoding interleaver according to claim 29, wherein the outer layer interleaving unit is configured to implement an interleaving process based on a quadratic permutation polynomial; The inner layer interleaving unit is configured to perform position exchange between two pairs of data bits in an even pair position of the original data block.