TWI448102B - Channel interleaving method, channel interleaver and channel encoding apparatus - Google Patents

Description

Channel interleaving method, channel interleaver and channel coding device Cross-reference to related applications

This application claims priority under 35 USC § 119: US Provisional Application No. 61/141,831, filed on December 12, 2011, entitled "Interleaver design for error correction code"; number 61/149,716, application date is 2009/2/4, US Provisional Application entitled "Bit Grouping Design for Error Correction Code"; number 61/154,027, filing date is 2009/2/20, US name "Bit Grouping Design for Error Correction Code" Temporary application; US Provisional Application No. 61/163,941, filed on Jan. 3/27, entitled "Bit Grouping Design for Error Correction Code", the subject of which is hereby incorporated by reference.

Embodiments of the present invention relate to interleaver designs for error correction codes, and more particularly to permutation-based constellation-based arrangements for channel interleaving.

Most Error Correction Codes (ECC) are designed to correct random channel errors. Decoder performance is often affected by a series of channel errors. Interleaving the bits in the error correction code can upset a series of channel errors to improve performance. At the transmitting end, the channel interleaving scrambles the encoded bits, so that the effects of continuous channel fading are distributed over the entire coding block. Therefore, at the receiving end, the length of the burst channel error is greatly reduced in one coding block.

Figure 1 (Prior Art) is a block diagram of an interleaving scheme for channel coding taken in an IEEE 802.16e wireless system. In the IEEE 802.16e wireless system, a Convolutional Turbo Code (CTC) interleaver is used for channel coding. As shown in FIG. 1, the CTC interleaver 11 includes a bit separation module 12, a subblock interleaver 13, and a bit-grouping module 14. The bit separation module 12 receives all coded bits from the CTC encoder and distributes the coded bits to a plurality of information subblocks A and B, and a plurality of parity subblocks (parity) Subblock) Y1, Y2, W1 and W2. The secondary block interleaver 13 independently interleaves all of the secondary blocks. The bit grouping module 14 multiplexes the interleaved sub-blocks and regroups them into sub-blocks A, B, Y, and W.

In IEEE 802.16e, the entire sub-block of the bit to be interleaved is written to an array having an address range of 0 to the number of bits to be interleaved minus 1 (N-1), and the interleave bits are interleaved. Read out in a permuted order, where the i-th bit is read from the address AD _i (i = 0...N-1). The formula of the secondary block interleaver 13 is as follows:

Where T _k is the tentative output address, m and J are the sub-block interleaver parameters, and BRO _m( y) represents the y-bit-inverted m-bit value (ie, BRO ₃ ( 6) = 3). If T _{k is} less than N, then AD _i =T _k and i and k are each incremented by one; otherwise T _{k is} discarded and only k is added. The above-described sub-block interleaving procedure is repeated until all N interleaver output addresses are obtained.

Then, at the transmitting end, the interleaved bits are modulated and then transmitted. At the receiving end, the received bits are de-modulated, de-interleaved, and then decoded by the CTC decoder. In the high-order modulation scheme (for example, 16 Quadrature Amplitude Modulation (QAM) and 64QAM, the modulation symbol carries more than two bits) because it is in a modulation symbol. With multiple levels of bit reliabilities, different bits have different error probabilities. As a result, two problems arise when using the IEEE 802.16e CTC interleaving scheme with high-order modulation. First, based on the sub-block interleaving equation (1), in each block, adjacent coded bits are mapped to levels in the modulation symbols having the same bit reliability. This problem is also referred to as intra-block continuity as shown in Figure 1, where adjacent coded bits 0, 1, and 2 in the secondary block A are mapped to high bit reliability. H. Second, because each block is interleaved based on the same interleaving equation, multiple bits with the same index in different sub-blocks are mapped to the levels of the same bit reliability in the modulated symbols. . This problem is also referred to as inter-block continuity as shown in FIG. 1, in which the same bit 93 in different sub-blocks A and B is mapped to the low-order reliability L.

Figure 2 (Prior Art) is a more detailed diagram of the continuity problem within the block. Figure 2 contains a schematic diagram of sub-block A after sub-block interleaving and a 16QAM symbolization constellation map 21. Interleaved sub-block A is provided to the symbol mapper using the selected modulation scheme (symbol mapper). In the 16QAM modulation scheme, each modulation symbol carries four bits b0b1b2b3, where b0 and b2 have high bit reliability H, and b1 and b3 have low bit reliability L. As shown in FIG. 2, based on the sub-block interleaving equation (1), adjacent bits in the sub-block A are mapped to the level of the same bit reliability. For example, bits 0-31, 96-160 are all mapped to H, and bits 32-95, 161-191 are mapped to L.

Figure 3 (Prior Art) is a more detailed diagram of the problem of continuity between blocks. Figure 3 contains the symbol modulation constellation 32 of the CTC encoder 31 and 64QAM. The CTC encoder 31 takes a pair of input bits A and B and sets-by-set produces the encoded bit sets A, B, Y1, W1, Y2 and W2. Each set of encoded bits is interleaved and provided to a symbol mapper using the selected modulation scheme. In 64QAM, each modulation symbol carries six bits b0b1b2b3b4b5, where b0 and b3 have high bit reliability H, b1 and b4 have intermediate reliability M, and b2 and b5 have low bit reliability L. As shown in Figure 3, because all sub-blocks are interleaved based on the same interleave equation, the same set of encoded bits is mapped to the same bit reliability level. For example, the same bit 93 of both sub-blocks A and B is mapped to L.

The IEEE 802.16e channel interleaver generates burst error bits due to continuity issues within the block and between blocks, and decoder performance is affected. Therefore, it is necessary to avoid that adjacent coded bits in each block are mapped to the level of the same bit reliability in the modulation symbol, and avoid multiple coded bits having the same index in different sub-blocks. A technical solution that maps to the level of reliability of the same bit.

In view of this, the following technical solutions are provided: a channel interleaver including a new permutation module based on a symbol modulation constellation. The channel interleaver first receives a plurality of encoded bit sets generated from the forward error correction encoder. The coded bits are distributed to a plurality of secondary blocks and each time block contains a plurality of adjacent bits. The secondary block interleaver interleaves each block and outputs a plurality of interleaved bits. The arrangement module based on the symbol modulation constellation rearranges the interleaved bits and outputs a plurality of rearranged bits. The rearranged bits are provided to the symbol mapper to avoid mapping of a plurality of consecutively encoded bits in the same set of coded bits generated by the forward error correction encoder to the level of the same bit reliability in the modulated symbols. In addition, it is also avoided that multiple adjacent bits of each block are mapped to levels having the same bit reliability to achieve symbol modulation constellation diversity and improve decoding performance at the receiving end.

In one embodiment, the permutation module based on the symbol modulation constellation performs block-type scrambling on the interleaved bits (meaning the interleaved bits are scrambled in units of blocks). In one example, the permutation module based on the symbol modulation constellation scrambles the interleaved bits by cyclically shifting the selected number of sub-blocks by a selected number of bits. In another example, the permutation module based on the symbol modulation constellation scrambles the interleaved bits by swapping a selected number of bits for the selected number of sub-blocks.

In another embodiment, the permutation module based on the symbol modulation constellation performs unit scrambling on the interleaved bits (referring to scramble the interleaved bits in units of cells). In an example, the permutation module based on the symbol modulation constellation first divides each block into a plurality of cells, and then scrambles by cyclically shifting the selected bits for a selected number of cells of each block. Interlaced bit yuan. In an example, the permutation module based on the symbol modulation constellation first divides each block into a plurality of cells, and then upsets by switching a selected number of cells for a selected number of cells of each block. Interleaved bits.

The channel interleaving method, channel interleaver and channel coding apparatus described above can realize diversity of symbol modulation constellation diagrams and improve decoder performance at the receiving end.

Other embodiments and advantages will be described in detail below. This Summary is not intended to be a limitation of the invention. The invention is defined by the scope of the patent application.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Figure 4 is a block diagram of a transmitter-encoder 41 and a receiver-decoder 51 in accordance with an embodiment of the present invention. The transmit encoder 41 includes a Forward Error Correction (hereinafter referred to as FEC) encoder 42, a channel interleaver 43, a symbol mapper 45, a modulation module 40, and a transmitting antenna 66. . The channel interleaver 43 further includes a bit separation module 46, a secondary block interleaver 47, a bit grouping module 48, and an arrangement module 49 based on a symbol modulation constellation. Similarly, the receiving decoder 51 includes an FEC decoder (52), a channel de-interleaver 53, a symbol de-mapper 55, and a demodulation module. 50. And a receiving antenna 76. The channel deinterleaver 53 further includes a bit de-separation module 56, a subblock de-interleaver 57, and a bit de-packet mode. A bit de-grouping module 58 and a constellation-based de-permutation module 59. At the transmitting end, a plurality of sets of encoded bits 101 from the FEC encoder 42 are interleaved, mapped and modulated into a transmission symbol 102, which is then transmitted by the antenna 66. At the receiving end, the received symbols 103 received by the antenna 76 are demodulated, demapped, and deinterleaved into decoder input bits 104 for decoding by the FEC decoder 52.

In one embodiment, the channel interleaver 43 includes an arrangement module 49 based on a symbol modulation constellation to achieve diversity of symbol modulation constellations for improving the performance of the decoder against burst channel errors. The bit separation module 46 receives a plurality of encoded bit sets 101 from the FEC encoder and distributes them to a plurality of information sub-blocks and parity sub-blocks. The secondary block interleaver 47 independently interleaves each block. The bit grouping module 48 multiplexes the interleaved bits and recombines the interleaved bits 105 into the second sub-block set. The present invention does not limit the number of initial multiple secondary block sets to be the same as the number of second multiple secondary block sets, wherein the second plurality of secondary block sets are generated after recombination. The number of the second plurality of sub-block sets may be different from the number of the initial plurality of sub-block sets, depending on design considerations. The permutation module 49 based on the symbol modulation constellation is segmented (optional) and the interleaved bit 105 is scrambled into the rearranged bit 106. By scrambling the interleaved bit 105, a plurality of consecutively encoded bits in each encoded bit set 101 can be prevented from being mapped through the symbol mapper 45 to a level having the same bit reliability in the modulated symbol. In addition, by dividing and scrambling the interleaved bit 105, it is also possible to prevent a plurality of adjacent bits in a sub-block from being mapped to the level of the same bit reliability in the modulated symbol. Therefore, at the receiving end, this arrangement based on the symbol modulation constellation can achieve symbol modulation The diversity of constellation diagrams and improved decoder performance.

There are two basic types of symbol-based constellation constellation arrangements, one called block-wise scrambling and the other called unit-wise scrambling. The permutation type of each symbol-based modulation constellation will be described in detail below.

Block disruption

Fig. 5A is a block diagram of the channel interleaver 61 of the first embodiment of the channel interleaver 43 shown in Fig. 4. In the example of Figure 5A, the channel interleaver 61 is designed based on the IEEE 802.16e channel interleaver 11 shown in Figure 1 of the prior art portion. The channel interleaver 61 includes a bit separation module 62, a secondary block interleaver 63, and a bit grouping module 64. In addition, the channel interleaver 61 includes a new permutation module 65 based on the symbol modulation constellation.

Figure 5B is a flow diagram of the channel interleaving using the block scrambling scheme performed by the channel interleaver 61 of Figure 5A. First, the FEC encoder 42 generates a plurality of encoded bit sets 101 (step 201). In IEEE 802.16e, a CTC encoder is employed as the FEC encoder 42. In CTC coding, every two input bits are encoded to produce six coded bits (ie, two information bits A and B and four parity bits Y1, Y2, W1, and W2). . Therefore, two bits of the encoder input bit 100 are provided at one time to the CTC encoder 42, which continuously encodes a plurality of encoded bit sets 101, and the CTC encoder 42 generates six bits at a time. The six bits form a set of encoded bits. Then, the plurality of encoded bit sets 101 are distributed by the bit separation module 62 to six sub-blocks (steps) 202). The six sub-blocks include two information sub-blocks A and B and four parity sub-blocks Y1, Y2, W1 and W2. Then, each of the six sub-blocks is independently interleaved by the sub-block interleaver 63 (step 203). The formula of the sub-block interleaver 63 is given by the sub-block interleaving equation (1) described in the prior art section. The bit grouping module 64 multiplexes each of the interleaved sub-blocks, wherein the information sub-blocks A and B remain unchanged, and the parity sub-blocks Y1 and Y2 are multiplexed and recombined into the sub-block Y, And the parity sub-blocks W1 and W2 are multiplexed and recombined into the sub-block W (step 204). After multiplexing and reassembling each interleaved sub-block into a plurality of interleaved bits 105, the interleaved bit 105 is tiled in a block-based manner based on the symbol modulation constellation arrangement module 65 (step 205) . After scrambling, the rearranged bit 106 is mapped by the symbol mapper 45 such that all six bits in each encoded bit set 101 are mapped to different modulations in the modulated symbols prior to transmission. Level (step 208).

In the example of FIG. 5A, the permutation constellation-based permutation module 65 performs block scrambling by cyclically shifting a selected number of sub-blocks by a selected number of bits. First, a number of sub-blocks are selected from four sub-blocks A, B, Y, and W (i.e., step 206 of Figure 5B). The selected number of sub-blocks are determined according to the modulation order, the FEC block size (Nep), and the coding scheme. In this particular example, the information sub-block B and the parity sub-block W are selected. Next, each selected sub-block is cyclically shifted left by a number of bits (i.e., step 207 of Figure 5B). The selection of the number of bits to be shifted per block must be such that each encoded bit set 101 generated by the FEC encoder 42 is mapped to a level of different bit reliability in the modulated symbols. In this special case, the sub-block B and the sub-block W are shifted by k bits, Wherein when the FEC block size Nep is equal to a multiple of the modulation order, k is set to an integer of 1, otherwise k is set to zero. In the example of 64QAM (the modulation order is six), if Nep is equal to a multiple of 6, k is set to 1, otherwise k is set to zero. For a selected number of sub-blocks, by circularly left-shifting a selected number of bits, the diversity of the symbol-modulated constellation can be implemented at the receiving end to improve decoder performance.

Figure 6A illustrates a schematic diagram of how the diversity of the symbol modulation constellation is achieved by the arrangement of the symbol-based modulation constellation. FIG. 6A includes a simplified diagram of a CTC encoder 42, a channel interleaver 43 having an arrangement based on a symbol modulation constellation, and a symbol mapper 45. The CTC encoder 42 produces an encoded set of bits 101 from the encoder input bit 100. As shown in FIG. 6A, two bits of the encoder input bits A and B are provided to the CTC encoder 42 at a time, and each two encoder bits are encoded to output an encoded bit every six bits. The metaset contains six bits A, B, Y1, Y2, W1 and W2. For example, the first bit of input A and the first bit of input B are provided to CTC encoder 42 at a time. After the CTC encoding, the first encoded bit set is continuously encoded and generated at another time, and the first encoded bit set includes the first bit of A, B, Y1, Y2, W1 and W2, respectively. In other words, the nth bit of A, B, Y1, Y2, W1, and W2 is generated to form the nth encoded bit set at the corresponding time. Channel interleaver 43 distributes, interleaves, and scrambles the plurality of encoded bit sets into reordered bits 106. The rearranged bit 106 is mapped to the modulated symbol by the symbol mapper 45. In the example of Figure 6A, a 64QAM modulation scheme is used. Each modulation symbol carries six bits b0b1b2b3b4b5, where b0 and b3 have high bit reliability H, b1 and b4 have intermediate reliability M, and b2 and b5 have low bits Reliability L.

In the special case of FIG. 6A, an encoded bit set "Y1, W1, A, B, Y2, and W2" is generated from the CTC encoder 43, and each of the six bits is mapped to "L, M, respectively. M, H, H, L". Therefore, the levels L, M, and H of all three bit reliability of the 64QAM modulation symbol are mapped, where each two bits are mapped to a level of bit reliability. In addition, two information bits and four parity bits are also mapped to levels with different bit reliability to achieve diversity of symbol modulation constellations. In other instances, the six encoded bits of the same set are not always mapped to all levels of the modulated symbols that have different bit reliability. However, by cyclically shifting the selected number of bits to the selected secondary block, at least some of the consecutively encoded bits in the same encoded bit set are not mapped to the level of the same bit reliability in the modulated symbol.

As shown in the third section of the prior art, since all the sub-blocks are interleaved based on the same interleave equation, the same index-encoded bits are mapped to the level having the same bit reliability. This problem means continuity between blocks. However, in the example of FIG. 6A, the secondary blocks B, W1, and W2 have been shifted left by k bits, and when Nep is equal to a multiple of the modulation order, k is equal to the integer 1. For example, for 64QAM, when Nep=576 or 1960, k=1, and the modulation order is equal to 6. Therefore, by cyclically shifting the selected number of bits by the selected sub-block, the problem of continuity between blocks can be avoided, and successively coded bits in the same coded bit set can be mapped to different bits in the modulation symbol. The level of reliability is used to achieve the diversity of symbol-modulated constellations.

Figure 6B illustrates a schematic diagram of how the decoding operation can be performed at the receiving end using the diversity of the symbol modulation constellation. Figure 6B contains the decoder input bits An illustration of 104 and FEC decoder 52. As shown in FIG. 6B, the decoder input bit 104 includes a plurality of sets of decoding bits; after the interleaving, mapping, modulation, and demodulation, demapping, and deinterleaving processes at the transmitting end, each The deinterleaved bit set is equivalent to each encoded bit set. Each set of deinterleaved bits is provided to FEC decoder 52 and decoded on a per-set basis. Since each de-interlaced bit set has a diversity of symbol-modulated constellations such as each encoded bit set, reducing the error bit length caused by the channel can improve the decoding performance of the receiving end.

Fig. 7 is a block diagram of the channel interleaver 71 of the second embodiment of the channel interleaver 43 shown in Fig. 4. The channel interleaver 71 includes a bit separation module 72, a sub-block interleaver 73, a bit grouping module 74, and an arrangement module 75 based on a symbol modulation constellation. Channel interleaver 71 is very similar to channel interleaver 61 of Figure 5A. However, before the sub-blocks W1 and W2 are supplied to the bit grouping module 74, the order is reversed. Therefore, the permutation module 75 based on the symbol modulation constellation selects three sub-blocks B, Y, and W instead of the two sub-blocks B and W to perform scrambling by shifting. The sub-block Y is shifted left by one bit, and the sub-block B and W are left shifted by k bits, wherein k is set to integer 1 when the FEC block size Nep is equal to a multiple of the modulation order. And otherwise k is set to 0. Although the order of the sub-blocks W1 and W2 is reversed, for each encoded bit set, the diversity of the symbol-modulated constellation can also be achieved by shifting the selected number of sub-blocks by a selected number of bits. .

Fig. 8 is a block diagram showing a channel interleaver 81 of the third embodiment of the channel interleaver 43 shown in Fig. 4. The channel interleaver 81 includes a bit separation module 82, a secondary block interleaver 83, a bit grouping module 84, and a symbol based The array module 85 of the modulation constellation. Channel interleaver 81 is also very similar to channel interleaver 61 of Figure 5A. However, the permutation module based on the symbol modulation constellation 85 performs block scrambling by swapping instead of shifting. First, a number of sub-blocks are selected from four sub-blocks A, B, Y, and W. The selected number of sub-blocks are determined based on the modulation order, the FEC block size (Nep), and the coding scheme. In this particular example, the information sub-block B and the parity sub-block W are selected. Next, each selected sub-block is swapped. The block swap includes swapping the i-th bit and the (N-i+1)th bit of the selected sub-block having N bits, where i is a running index from 1 to N/2. For each of the encoded bit sets generated by the FEC encoder, swapping the selected number of sub-blocks, the diversity of the symbol modulation constellation can be realized to improve the decoding performance.

Unit disruption

In addition to block scrambling, cell scrambling is another permutation scheme based on symbol-modulated constellation for channel interleaver to achieve symbolic modulation constellation diversity and improved decoder performance. Fig. 9A is a block diagram of the channel interleaver 91 of the fourth embodiment of the channel interleaver 43 shown in Fig. 4. The channel interleaver 91 includes a bit separation module 92, a secondary block interleaver 93, a bit grouping module 94, and an array module 95 based on a symbol modulation constellation. The permutation constellation-based permutation module 95 performs unitized scrambling on the interleaved bit 105 instead of performing block-type scrambling, and outputs a plurality of rearranged bit elements 106.

Figure 9B is a flow diagram of the channel interleaver 91 of Figure 9A performing channel interleaving using a unitized scrambling scheme. First, the bit separation module 92 distributes the plurality of encoded bit sets 101 from the FEC encoder to six sub-blocks (steps). Step 301). The six sub-blocks contain two information sub-blocks A and B, and four parity sub-blocks Y1, Y2, W1 and W2. Each of the six sub-blocks includes a plurality of adjacent bits. Sub-block interleaver 93 then independently interleaves each of the six sub-blocks (step 302). The bit grouping module 94 further multiplexes each of the interleaved sub-blocks, wherein the information sub-blocks A and B remain unchanged, and the parity sub-blocks Y1 and Y2 are multiplexed and recombined into the sub-block Y. And the parity sub-blocks W1 and W2 are multiplexed and recombined into the sub-block W (step 303). After multiplexing and recombining each of the interleaved sub-blocks into a plurality of interleaved bits 105, the interleaved bit 105 is unitarily scrambled using the symbol modulation constellation-based permutation module 95 to produce the rearranged bits. Element 106 is implemented to implement the diversity of the symbol modulation constellation (step 304).

Unit disruption further includes some steps. First, each block is divided into a plurality of units (step 305). Next, a number of units are selected from each block (step 306). Finally, the selected unit is shuffled by shifting or swapping (step 307). In the example of Figure 9A, each block is divided into two units: a first unit and a second unit. For the secondary blocks A and Y, the second unit is selected to be scrambled, and for the secondary blocks B and W, the first unit is selected to be scrambled. Each selected unit is then shifted left by one bit. In one embodiment, for each block, cell scrambling is performed on a selected number of cells to achieve diversity of symbol modulation constellation to improve receiver decoder performance.

Figure 10 illustrates a schematic diagram of how the diversity of the symbol modulation constellation is implemented in each block by the permutation constellation 95 based on the symbol modulation constellation shown in Figure 9A. Figure 10 contains the sub-block interleaving and before and after the disruption A simplified diagram of the secondary block A. First, a plurality of encoded bit sets 101 are distributed to a plurality of sub-blocks, and each block contains a plurality of adjacent bits, such as "188, 189, 190, 191" of the sub-block A. Each block is then interleaved and scrambled by the channel interleaver 91 into the rearranged bit 106. The rearranged bit 106 is mapped to the modulation symbol by the symbol mapper 45. In the example of Figure 10, a 16QAM modulation scheme is applied. With 16QAM, each modulation symbol carries four bits b0b1b2b3; where b0 and b2 have high bit reliability H, and b1 and b3 have low bit reliability L.

As shown in FIG. 2 of the prior art, using the IEEE 802.16e channel interleaver 11, adjacent bits of the secondary block A (i.e., "188, 189, 190, 191" due to the sub-block interleaving scheme adopted. ") is mapped to the same bit reliability (ie, "L"), and this problem is meant to be intra-block continuity. However, in the example of FIG. 10, since the secondary block is divided into two units, and only one of the two units is selected to be scrambled, neighboring bits of the secondary block A can be avoided (ie, " 188, 189, 190, 191") maps the level of the same bit reliability in the modulation symbol. In fact, the neighboring bits of the secondary block A are mapped to levels having different bit reliability (i.e., "LHLH"). Therefore, intra-block continuity can be avoided to improve decoder performance. In addition, because different units of different sub-blocks are selected for scrambling, inter-block continuity can also be avoided.

Fig. 11 is a block diagram showing a channel interleaver 111 of the fifth embodiment of the channel interleaver 43 shown in Fig. 4. The channel interleaver 111 includes a bit separation module 112, a secondary block interleaver 113, a bit grouping module 114, and an arrangement module 115 based on a symbol modulation constellation. Channel interleaver 111 is very similar to channel interleaver 91 of Figure 9A. However, the permutation module based on the symbol modulation constellation performs unit typing by swapping instead of shifting Chaos. First, each block is divided into a number of units. Next, select a quantity of units. The selected number of cells is determined based on the modulation order, the FEC block size (Nep), and the location of the selected block. Finally, swap each selected unit. The swapping includes swapping an ith bit of the selected cell having N bits with a (N-i+1)th bit, where i is a run index from 1 to N/2.

In the example of FIG. 11, the secondary blocks A and B are divided into N/3 units, and the secondary blocks Y and W are divided into 2*N/3 units, each of which contains three bits. . For the secondary blocks A and Y, the first (first) N/6 and N/3 units are selected, and in each selected unit, the first bit and the last bit are swapped. For the secondary blocks B and W, the last N/6 and N/3 units are selected, and for each selected unit, the first and last bits are swapped. By dividing the secondary block into multiple units and swapping the bits within the selected unit, symbolic tuning can be implemented for each encoded bit set generated from the FEC encoder and adjacent bits in each block. Change the diversity of the constellation.

Simulation result

Figures 12A and 12B are graphical representations of simulation results for channel interleaver performance using different interleaving schemes. In Fig. 12A, the FEC block size Nep is 960, the modulation is changed to 64QAM, and the code rate is 1/3. In Fig. 12B, the FEC block size Nep is 960, the modulation is changed to 64QAM, and the code rate is 1/2. As shown in Figures 12A and 12B, the signal-to-noise ratio (SNR) performance of all proposed channel interleavers is about 2 dB better than the original IEEE 802.16e channel interleaver. The block error rate (BLER) is 0.01). When the code rate is 1/3, the performance of the channel interleaver using the block scrambling scheme is similar to that of the channel interleaver using the unit scrambling scheme. However, when the code rate is 1/2, the performance of the channel interleaver using the unitized scrambling scheme exceeds the channel interleaver using the block-type scrambling scheme by about 0.1 to 0.3 dB. Because in each block, the unitized scrambling scheme obtains the diversity of the symbol modulation constellation at the expense of increased complexity, thereby providing better performance.

Other embodiments

Figures 13A, 13B and 13C are schematic views of other different embodiments of the channel interleaver 43 shown in Figure 4. In the example of FIG. 13A, bit separation module 46 receives a plurality of encoded bit sets 101 from FEC encoder 42 and distributes the encoded bits to a plurality of information sub-blocks and parity sub-blocks. The secondary block interleaver 47 independently interleaves all of the secondary blocks. The bit grouping module 48 multiplexes the interleaved sub-blocks and reassembles them into a plurality of sub-blocks. The alignment module based on the symbol modulation constellation receives the interleaved bit 105 and scrambles the interleaved bit to the rearranged bit 106. In the example of FIG. 13B, the permutation constellation based array module 49 receives the interleaved bit 105 from the sub-block interleaver 47 and scrambles the interleaved bit to the rearranged bit 106. The bit grouping module 48 then multiplexes the rearranged bit 106 and reassembles it into a plurality of sub-blocks. In the example of FIG. 13C, the bit grouping module 48 is implemented as a single bit grouping module together with the symbol modulation constellation based array module 49.

Although the present invention is described in terms of specific embodiments, the invention is not limited thereto. For example, the FEC encoder 42 of FIG. 4 may not be programmed for CTC. The encoder is another type of encoder. Furthermore, the symbol mapper 45 of FIG. 4 may map the rearranged bits to the modulated symbols without using 16QAM or 64QAM. Accordingly, various modifications, adaptations, and combinations of various features of the described embodiments may be practiced without departing from the scope of the invention.

11‧‧‧Interlacer

21, 32‧‧‧ symbol modulation constellation

31, 42‧‧‧ encoder

40‧‧‧Transformation Module

41‧‧‧Send encoder

45‧‧‧symbol mapper

43, 61, 71, 81, 91, 111‧‧‧ channel interleaver

12, 46, 62, 72, 82, 92, 112‧‧‧ bit separation modules

13, 47, 63, 73, 83, 93, 113 ‧ ‧ block interleaver

14, 48, 64, 74, 84, 94, 114‧‧ ‧ bit grouping modules

49, 65, 75, 85, 95, 115‧‧‧ Alignment modules based on symbolic modulation constellation

50‧‧‧Demodulation Module

51‧‧‧Receiver decoder

52‧‧‧FEC decoder

53‧‧‧Channel Deinterleaver

55‧‧‧ Symbol Demapper

56‧‧‧ bit dissociation module

57‧‧‧Subblock deinterlacer

58‧‧‧ bit deblocking module

59‧‧‧Decoding module based on symbol modulation constellation

66‧‧‧Send antenna

76‧‧‧Receiving antenna

100‧‧‧Encoder input bit

101‧‧‧coded bit set

102‧‧‧Send symbol

103‧‧‧ receiving symbols

104‧‧‧Decoder input bit

105‧‧‧ Interleaved bits

106‧‧‧Reordered bits

201, 202, 203, 204, 205, 206, 207, 208 ‧ ‧ steps

301, 302, 303, 304, 305, 306, 307 ‧ ‧ steps

The accompanying drawings are used to illustrate the embodiments of the invention

Figure 1 (Prior Art) is a block diagram of a channel coding interleaving scheme employed in an IEEE 802.16e wireless system.

Figure 2 (previous technique) is a schematic diagram of a sub-block map and a 16QAM symbol modulation constellation after sub-block interleaving.

Figure 3 (Prior Art) is a schematic diagram of a CTC encoder and a 64QAM symbol modulation constellation.

Figure 4 is a block diagram of a transmit encoder and a receive decoder in accordance with an embodiment of the present invention.

Figure 5A is a block diagram of a first embodiment of the channel interleaver of Figure 4.

Figure 5B is a flow diagram of the channel interleaving of the channel interleaver performing a block scrambling scheme.

Figure 6A is a diagram showing how the diversity of the symbol modulation constellation is implemented for each encoded bit set through the permutation module based on the symbol modulation constellation.

Figure 6B shows how the symbolic modulation constellation is used at the receiving end. Schematic diagram of improving decoding performance.

Figure 7 is a block diagram of a second embodiment of the channel interleaver of Figure 4.

Figure 8 is a block diagram of a third embodiment of the channel interleaver of Figure 4.

Figure 9A is a block diagram of a fourth embodiment of the channel interleaver of Figure 4.

Figure 9B is a flow diagram of the channel interleaving of the channel interleaver performing a unitized scrambling scheme.

Figure 10 is a schematic diagram of how the diversity of the symbol-modulated constellation is realized by the permutation module based on the symbol-modulated constellation in each block.

Figure 11 is a block diagram of a fifth embodiment of the channel interleaver of Figure 4.

A schematic diagram of the simulation results of the channel interleaver performance of Figures 12A and 12B.

Figures 13A, 13B and 13C are block diagrams of different embodiments of a new embodiment of the channel interleaver of Figure 4.

40‧‧‧Transformation Module

41‧‧‧Send encoder

42‧‧‧Encoder

43‧‧‧Channel Interleaver

45‧‧‧symbol mapper

46‧‧‧ bit separation module

47‧‧‧Subblock Interleaver

48‧‧‧ bit grouping module

49‧‧‧Arrangement module based on symbol modulation constellation

50‧‧‧Demodulation Module

51‧‧‧Receiver decoder

52‧‧‧FEC decoder

53‧‧‧Channel Deinterleaver

55‧‧‧ Symbol Demapper

56‧‧‧ bit dissociation module

57‧‧‧Subblock deinterlacer

58‧‧‧ bit deblocking module

59‧‧‧Decoding module based on symbol modulation constellation

66‧‧‧Send antenna

76‧‧‧Receiving antenna

100‧‧‧Encoder input bit

101‧‧‧coded bit set

102‧‧‧Send symbol

103‧‧‧ receiving symbols

104‧‧‧Decoder input bit

105‧‧‧ Interleaved bits

106‧‧‧Reordered bits

Claims (64)

A channel interleaving method includes: distributing a plurality of encoded bit sets to a first plurality of sub-blocks, wherein each of the plurality of encoded bit sets includes a majority generated by a forward error correction encoder a bit bit; interleaving each of the plurality of sub-blocks and outputting a plurality of interleaved bits; and rearranging the plurality of interleaved bits and outputting a plurality of rearranged bits, wherein the plurality of are already heavy The ranking elements are provided to a symbol mapper, and a plurality of consecutively encoded bits of the same encoded bit set are prevented from being mapped to a level of the same bit reliability in a modulated symbol to implement a symbol modulation constellation Diversity. The channel interleaving method of claim 1, wherein the plurality of bits in each of the plurality of encoded bit sets are mapped to a level of different bit reliability in the modulated symbol . The channel interleaving method of claim 1, wherein the plurality of bits of each of the plurality of encoded bit sets comprise a first number of information bits, and wherein the first number The information bits are not mapped to the level of the same bit reliability in the modulation symbol. The channel interleaving method of claim 1, wherein the rearranging the plurality of interleaved bits further comprises: multiplexing the plurality of interleaved bits and interleaving the plurality of multiplexed bits The plurality of sub-blocks are grouped into a second plurality of sub-blocks; a number of sub-blocks are selected from the second plurality of sub-blocks; and each of the selected sub-blocks is cyclically shifted by a number of bits. The channel interleaving method according to claim 1, wherein The rearranging the plurality of interleaved bits further comprises: grouping the plurality of interleaved bits into a second plurality of sub-blocks; selecting a quantity of the sub-blocks from the second plurality of sub-blocks; And cyclically shifting a number of bits for each of the selected sub-blocks. The channel interleaving method of claim 4, wherein the selected number of sub-blocks are determined based on a modulation order, a forward error correction block size, and a coding scheme. The channel interleaving method of claim 4, wherein the number of shifted bits is determined for each of the selected sub-blocks to be generated by the forward error correction encoder Each of the plurality of encoded bit sets is mapped to a level of different bit reliability in the modulated symbol. The channel interleaving method of claim 1, further comprising: selecting a quantity of the second block from the plurality of sub-blocks; and performing a block swapping for each of the selected sub-blocks . The channel interleaving method of claim 8, wherein the selected number of sub-blocks are determined based on a modulation order, a forward error correction block size, and a coding scheme. The channel interleaving method of claim 8, wherein the block type switching comprises ith bit and (N-i+1)th bit of a sub-block selected by one of N bits. Meta-switching, where i is an index running from one of 1 to N/2. For example, the channel interleaving method described in claim 1 of the patent scope further includes: The plurality of interleaved bits or the plurality of rearranged bits are multiplexed. A channel interleaver comprising: a bit splitter for distributing a plurality of encoded bit sets to a first plurality of sub-blocks, wherein each of the plurality of encoded bit sets comprises a a plurality of bits generated by the error correction encoder; a primary block interleaver for interleaving each of the plurality of sub-blocks and outputting a plurality of interleaved bits; and an arrangement based on a symbol modulation constellation a module for rearranging the plurality of interleaved bits and outputting a plurality of rearranged bits, wherein the plurality of rearranged bits are provided to a symbol mapper to avoid the same encoded bit set A plurality of consecutively encoded bits are mapped to a level of the same bit reliability in a modulated symbol to achieve diversity of the symbol modulated constellation. The channel interleaver of claim 12, wherein the plurality of bits in each of the plurality of coded bit sets are mapped to a level of different bit reliability in the modulation symbol . The channel interleaver of claim 12, wherein the plurality of bits of each of the plurality of encoded bit sets comprise a first number of information bits, and wherein the first number The information bits are not mapped to the level of the same bit reliability in the modulation symbol. The channel interleaver according to claim 12, further comprising: a one-bit packet module, configured to group the plurality of interleaved bits into a second plurality of sub-blocks, wherein the symbol-based modulation The arranging module of the constellation constellation selects a number of sub-blocks from the second plurality of sub-blocks, and then cyclically shifts a number of bits for each of the selected sub-blocks. The channel interleaver according to claim 12, further comprising: a one-bit packet module, configured to multiplex the plurality of interleaved bits and group the plurality of multiplexed interleaved bits to a second plurality of sub-blocks, wherein the permutation constellation-based permutation module selects a quantity of sub-blocks from the second plurality of sub-blocks, and then each of the selected sub-blocks Cycle through a number of bits. The channel interleaver of claim 16, wherein the selected number of sub-blocks are determined based on a forward error correction block size, a modulation order, and a coding scheme. The channel interleaver of claim 16, wherein the number of shifted bits is determined for each of the selected sub-blocks, so that the forward error corrects the plurality of generated by the encoder Each of the set of coded bits is mapped to a level of different bit reliability in the modulated symbol. The channel interleaver according to claim 12, wherein the symbol modulation constellation-based array module selects a quantity of the second block from the plurality of sub-blocks, and then selects the second sub-block. Each performs a block swap. The channel interleaver of claim 19, wherein the selected number of sub-blocks are determined based on a forward error correction block size, a modulation order, and a coding scheme. The channel interleaver of claim 19, wherein the block switching comprises an i-th bit and an (N-i+1)th bit of a sub-block having one of N bits selected. Swap, where i is the index from one of 1 to N/2. The channel interleaver according to claim 12, further comprising: a one-bit packet module, configured to multiplex the plurality of interleaved bits or the plurality of rearranged bits. A channel coding apparatus includes: an encoder for performing forward error correction coding and outputting a plurality of coded bit sets, wherein each of the plurality of coded bit sets includes a first to a plurality of coded bit sets a plurality of bits of the sub-block; and an interleaver for interleaving each of the first plurality of sub-blocks and outputting a plurality of interleaved bits to reduce an error code caused by a burst channel error The length of the word, wherein the interleaver is also used to rearrange the plurality of interleaved bits and output a plurality of rearranged bits, wherein the plurality of rearranged bits are provided to a symbol mapper to avoid the same A plurality of consecutively encoded bits in the encoded bit set are mapped to a level of the same bit reliability in a modulated symbol to achieve diversity of the symbol modulated constellation. The channel coding apparatus of claim 23, wherein the plurality of bits in each of the plurality of coded bit sets are mapped to a level of different bit reliability in the modulation symbol . The channel coding apparatus of claim 23, wherein the plurality of bits of each of the plurality of coded bit sets comprise a first number of information bits and wherein the first number is The information bits are not mapped to the level of the same bit reliability in the modulation symbol. The channel encoding device of claim 23, wherein the encoder comprises a convoluted turbo code encoder. a channel coding device as described in claim 23, The interleaver that rearranges the plurality of interleaved bits includes a permutation module based on a symbol modulation constellation, and the permutation module based on the symbol modulation constellation selects a quantity of interleaved bits and cyclically shifts The selected number of interleaved bits. The channel coding apparatus of claim 23, wherein the interleaver that rearranges the plurality of interleaved bits comprises an arrangement module based on a symbol modulation constellation, the arrangement of the symbol-based modulation constellation The module selects a quantity of the first plurality of secondary blocks and performs block switching for each of the selected secondary blocks. The channel encoding device of claim 23, wherein the interleaver that rearranges the plurality of interleaved bits comprises a one-bit packet module, the bit grouping module is configured to interleave the plurality of interleaved modules Bit multiplexing and grouping the plurality of multiplexed interleaved bits into a second plurality of sub-blocks, wherein an array module based on the symbol modulation constellation is from the second plurality of sub-blocks A number of interleaved bits are selected and the selected number of interleaved bits are cyclically shifted. The channel encoding device of claim 23, wherein the interleaver that rearranges the plurality of interleaved bits comprises a one-bit packet module, the bit grouping module is configured to interleave the plurality of interleaved modules Bit multiplexing and grouping the plurality of multiplexed interleaved bits into a second plurality of sub-blocks, wherein an array module based on the symbol modulation constellation is from the second plurality of sub-blocks A number of secondary blocks are selected and block swapping is performed for each of the selected secondary blocks. A channel interleaving method comprising: integrating a plurality of encoded bits generated by a forward error correction encoder Deploying to a first plurality of sub-blocks, wherein each block includes a plurality of adjacent bits; interleaving each of the first plurality of sub-blocks and outputting a plurality of interleaved bits; and rearranging the a plurality of interleaved bits and outputting a plurality of rearranged bits, wherein the plurality of rearranged bits are provided to a symbol mapper to prevent the plurality of adjacent bits of each block from being mapped to one The level of the same bit reliability in the modulation symbol is used to achieve the diversity of the symbol modulation constellation. The channel interleaving method of claim 31, wherein a plurality of consecutive coded bits of the same coded bit set are also prevented from being mapped to the same bit reliability level in the modulation symbol. The channel interleaving method of claim 31, wherein the rearranging further comprises: multiplexing the plurality of interleaved bits and grouping the plurality of multiplexed interleaved bits into a second plurality a secondary block; dividing each of the second plurality of secondary blocks into a plurality of units; and for each of the second plurality of secondary blocks, selecting a quantity of units from the plurality of units; And for each of the second plurality of sub-blocks, each of the selected number of units is cyclically shifted by a number of bits. The channel interleaving method of claim 31, wherein the rearranging further comprises: dividing the plurality of interleaved bits into a plurality of units; selecting a quantity of units from the plurality of units; Selecting each of the number of units to cyclically shift a quantity Bit. The channel interleaving method of claim 33, wherein the number of units selected is based on a modulation order, a forward error correction block size, and each of the second plurality of sub-blocks. To decide. The channel interleaving method of claim 33, wherein the shifted number of bits is determined based on a modulation order, a forward error correction block size, and a location of the selected number of cells. . The channel interleaving method according to claim 33, wherein a 16-quadrant modulation modulation scheme is used, each block is divided into two units, and the two blocks from each block. One of the cells is selected to shift the cell by one bit. The channel interleaving method described in claim 33, wherein a 64-quadrant modulation modulation scheme is used, each block is divided into three units, and the three blocks from each block Two cells are selected from the cells, and one of the selected two cells is shifted by one bit and the other cell is shifted by two bits. The channel interleaving method of claim 31, wherein the rearranging further comprises: multiplexing the plurality of interleaved bits and grouping the plurality of multiplexed interleaved bits into a second plurality a secondary block; dividing each of the second plurality of secondary blocks into a plurality of units; selecting a quantity of units from the plurality of units; and for each of the second plurality of secondary blocks The block performs a unit exchange for each of the selected number of units. a channel interleaving method as described in claim 31 of the patent application, The rearrangement further includes: dividing each of the first plurality of sub-blocks into a plurality of units; selecting a quantity of units from the plurality of units; and for the first plurality of sub-blocks Each time block, a unit exchange is performed for each of the selected number of units. The channel interleaving method of claim 39, wherein the number of units selected is based on a modulation order, a forward error correction block size, and each of the second plurality of sub-blocks. was decided. The channel interleaving method of claim 39, wherein the unit switching comprises transposing an ith bit having a selected one of N bits with a (N-i+1)th bit, wherein Run the index from one of 1 to N/2. The channel interleaving method of claim 39, wherein a 16-quadrant modulation modulation scheme is used, and each of the second plurality of sub-blocks having N bits is used. It is divided into N/2 units, each unit contains two bits, and the first bit and the last bit of each selected unit are swapped. The channel interleaving method of claim 39, wherein the 64 quadrature amplitude modulation modulation scheme is used, and each of the second plurality of sub-blocks having N bits is used. It is divided into N/3 units, each unit contains three bits, and the first bit and the last bit of each selected unit are swapped. A channel interleaver comprising: a one-bit splitter for distributing a plurality of encoded bit sets generated by a forward error correction encoder to a first plurality of sub-blocks, wherein each time zone The block includes a plurality of adjacent bits; a primary block interleaver for interleaving each of the plurality of secondary blocks and outputting a plurality of interleaved bits; and an array module based on a symbol modulation constellation, Re-arranging the plurality of interleaved bits and outputting a plurality of rearranged bits, wherein the plurality of rearranged bits are provided to a symbol mapper to avoid the plurality of phases in each block The adjacent bit maps to the level of the same bit reliability in a modulation symbol to achieve the diversity of the symbol modulation constellation. The channel interleaver of claim 45, wherein a plurality of consecutive coded bits of the same coded bit set are also prevented from being mapped to a level of bit reliability in the modulation symbol. The channel interleaver according to claim 45, wherein the permutation module based on the symbol modulation constellation divides each block of the first plurality of sub-blocks into a plurality of units, from the plurality of The unit selects a number of units, and for each of the first plurality of sub-blocks, cyclically shifts each of the selected units by a number of bits. The channel interleaver according to claim 45, further comprising: a one-bit multiplexer for multiplexing the plurality of interleaved bits and grouping the plurality of multiplexed interleaved bits And a second plurality of sub-blocks, wherein the permutation module based on the symbol modulation constellation divides each of the second plurality of sub-blocks into a plurality of units, and selects one of the plurality of units A unit of quantity, and for each block of the second plurality of sub-blocks, cyclically shifting a number of bits for each of the selected units. A channel interleaver as described in claim 48, wherein The number of units selected is determined based on the modulation order, the forward error correction block size, and each block position of the second plurality of secondary blocks. The channel interleaver of claim 48, wherein the shifted number of bits is determined based on a modulation order, a forward error correction block size, and a location of the selected unit. The channel interleaver of claim 48, wherein a 16-quadrant modulation modulation scheme is used, and each block is divided into two units, and from the second plurality of times One of the two cells of each block of the block is selected to shift the cell by one bit. The channel interleaver of claim 48, wherein a 64 quadrature amplitude modulation modulation scheme is used, each block is divided into three units, and from the second plurality of sub-regions Two of the three cells of each block of the block are selected, and one of the selected two cells is shifted by one bit and the other cell is shifted by two bits. The channel interleaver according to claim 45, wherein the permutation module based on the symbol modulation constellation divides each block of the first plurality of sub-blocks into a plurality of units, from the plurality of A unit of the number is selected in the unit, and for each of the blocks of the first plurality of sub-blocks, a unit exchange is performed for each of the selected units. The channel interleaver according to claim 45, further comprising: a one-bit packet module for multiplexing the plurality of interleaved bits and grouping the plurality of multiplexed interleaved bits And a second plurality of sub-blocks, wherein the permutation module based on the symbol modulation constellation divides each of the second plurality of sub-blocks into a plurality of units, and selects one of the plurality of units number A unit of quantities, and for each block of the second plurality of sub-blocks, performs a unitary swap for each of the selected units. The channel interleaver of claim 54, wherein the selected number of units is based on a modulation order, a forward error correction block size, and each block of the second plurality of sub-blocks. Position to decide. The channel interleaver of claim 54, wherein the unit exchange comprises transposing an ith bit and a (N-i+1)th bit of a selected one of N bits, wherein Run the index from one of 1 to N/2. The channel interleaver according to claim 54, wherein a 64-quadrant modulation modulation scheme is used, and each block having N bits is divided into N/3 units, Each cell contains three bits and the first bit and the last bit of each selected cell are swapped. A channel encoding apparatus comprising: an encoder for performing forward error correction encoding and outputting a plurality of encoded bit sets, wherein each of the plurality of encoded bit sets is distributed to a first plurality of times a block, and each block includes a plurality of adjacent bits; and an interleaver for interleaving each of the plurality of sub-blocks and outputting a plurality of interleaved bits to reduce channel errors due to bursts And causing the length of the error codeword, wherein the interleaver is further configured to rearrange the plurality of interleaved bits and output a plurality of rearranged bits, the plurality of rearranged bits being provided to a symbol mapper, The plurality of adjacent bits in each block are prevented from being mapped to a level of the same bit reliability in a modulation symbol to achieve diversity of the symbol modulation constellation. The channel coding apparatus according to claim 58, wherein a plurality of consecutive coding bits in the same coded bit set are also prevented from being mapped to the level of the same bit reliability in the modulation symbol. The channel encoding device of claim 58, wherein the encoder comprises a cyclotron turbo code encoder. The channel coding apparatus of claim 58, wherein the interleaver comprises an arrangement module based on a symbol modulation constellation for dividing each block of the first plurality of sub-blocks into multiple Units, selecting one or more units, and for each of the first plurality of sub-blocks, cyclically shifting each of the selected units by a number of bits. The channel coding apparatus of claim 58, wherein the interleaver comprises a one-bit packet module for multiplexing the plurality of interleaved bits and interleaving the plurality of multiplexed bits Meta-grouping to a second plurality of sub-blocks; and an arranging module based on the symbol-modulated constellation for dividing each of the second plurality of sub-blocks into a plurality of units, selecting one or a plurality of units, and for each of the second plurality of sub-blocks, each of the selected units is cyclically shifted by a number of bits. The channel coding apparatus of claim 58, wherein the interleaver comprises an arrangement module based on a symbol modulation constellation for dividing each block of the first plurality of sub-blocks into multiple Units, selecting one or more units, and performing a unitary swap for each of the selected units for each of the first plurality of sub-blocks. The channel coding apparatus of claim 58, wherein the interleaver comprises a one-bit packet module for multiplexing the plurality of interleaved bits and interleaving the plurality of multiplexed bits Meta-grouping to a second multiple a sub-block; and an arrangement module based on the symbol modulation constellation for dividing each of the second plurality of sub-blocks into a plurality of units, selecting one or more units, and for the Each of the two plurality of sub-blocks performs a unit exchange for each of the selected units.