WO2008155826A1 - キャッシュ制御装置およびキャッシュ制御方法 - Google Patents

キャッシュ制御装置およびキャッシュ制御方法 Download PDF

Info

Publication number
WO2008155826A1
WO2008155826A1 PCT/JP2007/062339 JP2007062339W WO2008155826A1 WO 2008155826 A1 WO2008155826 A1 WO 2008155826A1 JP 2007062339 W JP2007062339 W JP 2007062339W WO 2008155826 A1 WO2008155826 A1 WO 2008155826A1
Authority
WO
WIPO (PCT)
Prior art keywords
unit
valid bit
cash control
request
thread
Prior art date
Application number
PCT/JP2007/062339
Other languages
English (en)
French (fr)
Inventor
Yuji Shirahige
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to JP2009520180A priority Critical patent/JP4621292B2/ja
Priority to EP07767197A priority patent/EP2159701A4/en
Priority to PCT/JP2007/062339 priority patent/WO2008155826A1/ja
Publication of WO2008155826A1 publication Critical patent/WO2008155826A1/ja
Priority to US12/654,167 priority patent/US20100095071A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)

Abstract

　複数のスレッドに対するパイプライン処理が実行される場合に、確実に処理効率を向上すること。この課題を解決するために、サイクルＴ処理部（１４２ａ）からサイクルＲ処理部（１４２ｄ）までの各処理部は、ストールしたスレッドのリクエストに関する処理中である場合に、対応するウェイトポート（１４３ａ～１４３ｄ）においてストールしたスレッドのバリッドビットを１にセットする。リクエスト記憶部（１４８）は、いずれかのスレッドに関するバリッドビットに１となったものが検出されると、このバリッドビットに対応するリクエストを順次レジスタ部（１４９）へ出力する。プライオリティ決定部（１４４）は、バリッドビットに基づいてセレクタ（１４１）における出力の優先度を決定する。セレクタ（１４１）は、プライオリティ決定部（１４４）からのセレクト信号に従い、いずれか１つのリクエストを出力する。
PCT/JP2007/062339 2007-06-19 2007-06-19 キャッシュ制御装置およびキャッシュ制御方法 WO2008155826A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2009520180A JP4621292B2 (ja) 2007-06-19 2007-06-19 キャッシュ制御装置およびキャッシュ制御方法
EP07767197A EP2159701A4 (en) 2007-06-19 2007-06-19 CACHE MEMORY CONTROL DEVICE AND CONTROL METHOD
PCT/JP2007/062339 WO2008155826A1 (ja) 2007-06-19 2007-06-19 キャッシュ制御装置およびキャッシュ制御方法
US12/654,167 US20100095071A1 (en) 2007-06-19 2009-12-11 Cache control apparatus and cache control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/062339 WO2008155826A1 (ja) 2007-06-19 2007-06-19 キャッシュ制御装置およびキャッシュ制御方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/654,167 Continuation US20100095071A1 (en) 2007-06-19 2009-12-11 Cache control apparatus and cache control method

Publications (1)

Publication Number Publication Date
WO2008155826A1 true WO2008155826A1 (ja) 2008-12-24

Family

ID=40155992

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/062339 WO2008155826A1 (ja) 2007-06-19 2007-06-19 キャッシュ制御装置およびキャッシュ制御方法

Country Status (4)

Country Link
US (1) US20100095071A1 (ja)
EP (1) EP2159701A4 (ja)
JP (1) JP4621292B2 (ja)
WO (1) WO2008155826A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016186689A (ja) * 2015-03-27 2016-10-27 富士通株式会社 演算処理装置及び演算処理装置の制御方法
JP2020095464A (ja) * 2018-12-12 2020-06-18 富士通株式会社 演算処理装置及び演算処理装置の制御方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9135087B1 (en) * 2012-12-27 2015-09-15 Altera Corporation Workgroup handling in pipelined circuits
US10474365B2 (en) * 2013-01-25 2019-11-12 Stroz Friedberg, LLC System and method for file processing from a block device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6785803B1 (en) * 1996-11-13 2004-08-31 Intel Corporation Processor including replay queue to break livelocks
US6385715B1 (en) * 1996-11-13 2002-05-07 Intel Corporation Multi-threading for a processor utilizing a replay queue
US6609193B1 (en) * 1999-12-30 2003-08-19 Intel Corporation Method and apparatus for multi-thread pipelined instruction decoder
JP3295728B2 (ja) * 2000-01-07 2002-06-24 北陸先端科学技術大学院大学長 パイプラインキャッシュメモリの更新回路
US7719540B2 (en) * 2004-03-31 2010-05-18 Intel Corporation Render-cache controller for multithreading, multi-core graphics processor
US7664936B2 (en) * 2005-02-04 2010-02-16 Mips Technologies, Inc. Prioritizing thread selection partly based on stall likelihood providing status information of instruction operand register usage at pipeline stages

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
ITO E. ET AL.: "Kansugata Program no Jikko ni Tekishita Multi-thread-gata Processor.Architecture no Teian", INFORMATION PROCESSING SOCIETY OF JAPAN KENKYU HOKOKU, vol. 96, no. 121, 12 December 1996 (1996-12-12), pages 81 - 88, XP008118288 *
KIMURA K. ET AL.: "Multi-thread Processor no Data cache Seigyo Hoshiki", GAZO JOHO MEDIA GAKKAISHI, vol. 52, no. 5, 20 May 1998 (1998-05-20), pages 742 - 749, XP008118286 *
POONACHA KONGETIRA ET AL.: "NIAGARA: A 32-WAY MULTITHREADED SPARC PROCESSOR (Niagara 32 Bit Way Multi-thread SPARC Processor)", IEEE MICRO, vol. 25, no. 2, March 2005 (2005-03-01), pages 21 - 29, XP002355469 *
See also references of EP2159701A4 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016186689A (ja) * 2015-03-27 2016-10-27 富士通株式会社 演算処理装置及び演算処理装置の制御方法
US10031751B2 (en) 2015-03-27 2018-07-24 Fujitsu Limited Arithmetic processing device and method for controlling arithmetic processing device
JP2020095464A (ja) * 2018-12-12 2020-06-18 富士通株式会社 演算処理装置及び演算処理装置の制御方法
JP7318203B2 (ja) 2018-12-12 2023-08-01 富士通株式会社 演算処理装置及び演算処理装置の制御方法

Also Published As

Publication number Publication date
EP2159701A1 (en) 2010-03-03
JP4621292B2 (ja) 2011-01-26
US20100095071A1 (en) 2010-04-15
JPWO2008155826A1 (ja) 2010-08-26
EP2159701A4 (en) 2011-08-10

Similar Documents

Publication Publication Date Title
WO2008076896A3 (en) Configurable cache for a microprocessor
EP2190143A8 (en) Cryptographic processing apparatus with improved resistance to power analysis
WO2007100915A3 (en) Systems, methods, and media for outputting data based on anomaly detection
WO2008155826A1 (ja) キャッシュ制御装置およびキャッシュ制御方法
WO2008019189A3 (en) Secure storage of data
ATE479185T1 (de) Speicher mit selektiver vorladung
TW200710723A (en) Dual thread processor
GB2481567A (en) Unpacking packed data in multiple lanes
WO2009013832A1 (ja) 予備ライン割当装置、メモリ救済装置、予備ライン割当方法、メモリ製造方法、およびプログラム
WO2011112354A3 (en) Sensing operations in a memory device
WO2009114341A3 (en) Method and system for configuring solar energy systems
TW200834306A (en) Configurable cache for a microprocessor
EP2031594A3 (en) Information processing device and information processing method
ATE512399T1 (de) Registerbasierte verschiebungen für einen unidirektionalen rotator
WO2008069971A3 (en) Apparatus and associated methods for diagnosing configuration faults
WO2008051350A3 (en) Mapping primary operations sequences of an algorithm in ram
WO2012033410A3 (en) Led driver circuit and method
WO2007140040A3 (en) Contention-free hierarchical bit line in embedded memory and method thereof
WO2012046864A3 (en) Multicore type error correction processing system and error correction processing apparatus
WO2008114315A1 (ja) Fault攻撃対策機能を搭載した組み込み装置
WO2010123541A3 (en) Method and structure for solving the evil-twin problem
WO2008027567A3 (en) Integral parallel machine
TW200729230A (en) Memory module and register with minimized routing path
WO2010041022A3 (en) Analysis of a connection between two computers
WO2007072051A3 (en) Data tracking system

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07767197

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2009520180

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 2007767197

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE