WO2008155826A1 - キャッシュ制御装置およびキャッシュ制御方法 - Google Patents
キャッシュ制御装置およびキャッシュ制御方法 Download PDFInfo
- Publication number
- WO2008155826A1 WO2008155826A1 PCT/JP2007/062339 JP2007062339W WO2008155826A1 WO 2008155826 A1 WO2008155826 A1 WO 2008155826A1 JP 2007062339 W JP2007062339 W JP 2007062339W WO 2008155826 A1 WO2008155826 A1 WO 2008155826A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- unit
- valid bit
- cash control
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- thread
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0855—Overlapped cache accessing, e.g. pipeline
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multimedia (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Advance Control (AREA)
Abstract
複数のスレッドに対するパイプライン処理が実行される場合に、確実に処理効率を向上すること。この課題を解決するために、サイクルT処理部(142a)からサイクルR処理部(142d)までの各処理部は、ストールしたスレッドのリクエストに関する処理中である場合に、対応するウェイトポート(143a~143d)においてストールしたスレッドのバリッドビットを1にセットする。リクエスト記憶部(148)は、いずれかのスレッドに関するバリッドビットに1となったものが検出されると、このバリッドビットに対応するリクエストを順次レジスタ部(149)へ出力する。プライオリティ決定部(144)は、バリッドビットに基づいてセレクタ(141)における出力の優先度を決定する。セレクタ(141)は、プライオリティ決定部(144)からのセレクト信号に従い、いずれか1つのリクエストを出力する。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2007/062339 WO2008155826A1 (ja) | 2007-06-19 | 2007-06-19 | キャッシュ制御装置およびキャッシュ制御方法 |
JP2009520180A JP4621292B2 (ja) | 2007-06-19 | 2007-06-19 | キャッシュ制御装置およびキャッシュ制御方法 |
EP07767197A EP2159701A4 (en) | 2007-06-19 | 2007-06-19 | CACHE MEMORY CONTROL DEVICE AND CONTROL METHOD |
US12/654,167 US20100095071A1 (en) | 2007-06-19 | 2009-12-11 | Cache control apparatus and cache control method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2007/062339 WO2008155826A1 (ja) | 2007-06-19 | 2007-06-19 | キャッシュ制御装置およびキャッシュ制御方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/654,167 Continuation US20100095071A1 (en) | 2007-06-19 | 2009-12-11 | Cache control apparatus and cache control method |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2008155826A1 true WO2008155826A1 (ja) | 2008-12-24 |
Family
ID=40155992
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2007/062339 WO2008155826A1 (ja) | 2007-06-19 | 2007-06-19 | キャッシュ制御装置およびキャッシュ制御方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20100095071A1 (ja) |
EP (1) | EP2159701A4 (ja) |
JP (1) | JP4621292B2 (ja) |
WO (1) | WO2008155826A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016186689A (ja) * | 2015-03-27 | 2016-10-27 | 富士通株式会社 | 演算処理装置及び演算処理装置の制御方法 |
JP2020095464A (ja) * | 2018-12-12 | 2020-06-18 | 富士通株式会社 | 演算処理装置及び演算処理装置の制御方法 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9135087B1 (en) * | 2012-12-27 | 2015-09-15 | Altera Corporation | Workgroup handling in pipelined circuits |
US10474365B2 (en) * | 2013-01-25 | 2019-11-12 | Stroz Friedberg, LLC | System and method for file processing from a block device |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6385715B1 (en) * | 1996-11-13 | 2002-05-07 | Intel Corporation | Multi-threading for a processor utilizing a replay queue |
US6785803B1 (en) * | 1996-11-13 | 2004-08-31 | Intel Corporation | Processor including replay queue to break livelocks |
US6609193B1 (en) * | 1999-12-30 | 2003-08-19 | Intel Corporation | Method and apparatus for multi-thread pipelined instruction decoder |
JP3295728B2 (ja) * | 2000-01-07 | 2002-06-24 | 北陸先端科学技術大学院大学長 | パイプラインキャッシュメモリの更新回路 |
US7719540B2 (en) * | 2004-03-31 | 2010-05-18 | Intel Corporation | Render-cache controller for multithreading, multi-core graphics processor |
US7664936B2 (en) * | 2005-02-04 | 2010-02-16 | Mips Technologies, Inc. | Prioritizing thread selection partly based on stall likelihood providing status information of instruction operand register usage at pipeline stages |
-
2007
- 2007-06-19 EP EP07767197A patent/EP2159701A4/en not_active Withdrawn
- 2007-06-19 JP JP2009520180A patent/JP4621292B2/ja not_active Expired - Fee Related
- 2007-06-19 WO PCT/JP2007/062339 patent/WO2008155826A1/ja active Application Filing
-
2009
- 2009-12-11 US US12/654,167 patent/US20100095071A1/en not_active Abandoned
Non-Patent Citations (4)
Title |
---|
ITO E. ET AL.: "Kansugata Program no Jikko ni Tekishita Multi-thread-gata Processor.Architecture no Teian", INFORMATION PROCESSING SOCIETY OF JAPAN KENKYU HOKOKU, vol. 96, no. 121, 12 December 1996 (1996-12-12), pages 81 - 88, XP008118288 * |
KIMURA K. ET AL.: "Multi-thread Processor no Data cache Seigyo Hoshiki", GAZO JOHO MEDIA GAKKAISHI, vol. 52, no. 5, 20 May 1998 (1998-05-20), pages 742 - 749, XP008118286 * |
POONACHA KONGETIRA ET AL.: "NIAGARA: A 32-WAY MULTITHREADED SPARC PROCESSOR (Niagara 32 Bit Way Multi-thread SPARC Processor)", IEEE MICRO, vol. 25, no. 2, March 2005 (2005-03-01), pages 21 - 29, XP002355469 * |
See also references of EP2159701A4 * |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016186689A (ja) * | 2015-03-27 | 2016-10-27 | 富士通株式会社 | 演算処理装置及び演算処理装置の制御方法 |
US10031751B2 (en) | 2015-03-27 | 2018-07-24 | Fujitsu Limited | Arithmetic processing device and method for controlling arithmetic processing device |
JP2020095464A (ja) * | 2018-12-12 | 2020-06-18 | 富士通株式会社 | 演算処理装置及び演算処理装置の制御方法 |
JP7318203B2 (ja) | 2018-12-12 | 2023-08-01 | 富士通株式会社 | 演算処理装置及び演算処理装置の制御方法 |
Also Published As
Publication number | Publication date |
---|---|
EP2159701A4 (en) | 2011-08-10 |
US20100095071A1 (en) | 2010-04-15 |
JPWO2008155826A1 (ja) | 2010-08-26 |
JP4621292B2 (ja) | 2011-01-26 |
EP2159701A1 (en) | 2010-03-03 |
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