WO2008152557A1 - Procédé de test à un composant semiconducteur - Google Patents

Procédé de test à un composant semiconducteur Download PDF

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Publication number
WO2008152557A1
WO2008152557A1 PCT/IB2008/052251 IB2008052251W WO2008152557A1 WO 2008152557 A1 WO2008152557 A1 WO 2008152557A1 IB 2008052251 W IB2008052251 W IB 2008052251W WO 2008152557 A1 WO2008152557 A1 WO 2008152557A1
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WO
WIPO (PCT)
Prior art keywords
block
parameter
measured
tolerance window
target value
Prior art date
Application number
PCT/IB2008/052251
Other languages
English (en)
Inventor
Antonius M. P. J. Hendriks
Hermanus H. W. Thoonen
Gerard Lemmen
Kitty Van Dijk
Johannes D. Dingemanse
Original Assignee
Nxp B.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp B.V. filed Critical Nxp B.V.
Publication of WO2008152557A1 publication Critical patent/WO2008152557A1/fr

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2894—Aspects of quality control [QC]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31705—Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits

Definitions

  • the present invention relates to a method of testing a semiconductor device, the device comprising a plurality of blocks of identical design.
  • Contemporary semiconductor devices such as integrated circuits (ICs) fulfil crucial roles in many application domains, such as the automotive industry. Because of the crucial functional roles that these devices play, it is of paramount importance that semiconductor device manufacturers provide flawless semiconductor devices to their customers to minimize the risk of the failure of an apparatus incorporating the semiconductor device because of a fault in the semiconductor device.
  • the semiconductor device manufacturer has to robustly test each semiconductor device prior to clearing the device for delivery to a customer.
  • Such testing typically includes a wafer test, which means that the semiconductor devices undergo testing whilst still forming part of the wafer on which they were manufactured. Faulty devices on the wafer are marked and discarded after the sawing process, with the passed devices being packaged and subjected to further tests to ensure that the packaging process has not damaged the devices.
  • the detection of faulty semiconductor devices at wafer test (which are also referred to as semiconductor dies at this stage) is important because it can avoid wasting money in packaging faulty semiconductor devices as well as give clear insights into which steps of the manufacturing process are responsible for the occurrence of any detected defects. These insights can be used to improve the manufacturing process.
  • Defining reliable test criteria for testing semiconductor devices on a wafer is not trivial, because the wafer typically exhibits variations in parameters of the manufacturing process, e.g. variations in dopant concentrations, thickness, critical dimension layer, resistivity and so on. Such variations can cause semiconductor devices in one section of the wafer (e.g. on an edge of the wafer) to produce significantly different test results than the semiconductor devices in another section of the wafer (e.g. in the centre of the wafer), in particular when testing an electrical parameter of the semiconductor device which magnitude is directly related to such a process parameter. Care has to be taken that the acquisition of such different test results does not lead to the rejection of properly functioning devices, and at the same time, does not lead to faulty devices remaining undetected.
  • variations in parameters of the manufacturing process e.g. variations in dopant concentrations, thickness, critical dimension layer, resistivity and so on.
  • Such variations can cause semiconductor devices in one section of the wafer (e.g. on an edge of the wafer) to produce significantly different test results than the semiconductor devices
  • the present invention seeks to provide a method according to the opening paragraph that does not suffer from the drawbacks of the prior art.
  • this method comprises the steps of measuring a block parameter of each block; calculating a target value for the block parameter from at least one measured block parameter; defining a tolerance window around the target value; determining, for each measured block parameter, if said parameter falls inside the tolerance window; and classifying the semiconductor device as faulty if at least one of the measured block parameters falls outside the tolerance window.
  • the method of the present invention is based on the realization that semiconductor devices such as ICs typically have a large number of blocks of identical design, i.e.
  • a semiconductor device can be tested by evaluating the statistical property of a measured device parameter such as an electrically measured parameter, e.g. jitter, signal frequency, signal hsetime or falltime, leakage currents, start-up currents, operational currents, I/O voltage levels, resistivity and so on, because the allowable statistical property of such a parameter for all measured blocks is typically well-defined. Since the method of the present invention considers intra-die variations, the outcome of a wafer test based on the method of the present invention is insensitive to the starting location on the wafer.
  • the method can be applied at any stage of the manufacturing process, e.g. at wafer-test or at final test after packaging.
  • a target value may be used during test that is based on the distribution of all measured block parameters, e.g. the average value in case of a Gaussian distribution.
  • the step of calculating the target value comprises, after a performed determining step, calculating an updated target value from the target value used in the performed determining step and the measured block value of the performed determining step, such that an intra-die moving limits approach is achieved.
  • the tolerance window may be updated as well by means of the step of defining the tolerance window comprising calculating the tolerance window after the performed determining step from the standard deviation of the block parameters measured in all preceding measuring steps.
  • the tolerance window may be calculated from all measured block parameters of a single semiconductor device. This has the advantage that a stringent, i.e. narrow, tolerance window may be defined because the tolerance window is based on a known statistical spread around a known mean value.
  • the tolerance window may also be calculated from a subset of block parameters of a single device, for instance from all blocks that share an orientation on the device in case the block parameter valus is sensitive to the orientation of the block on the device. The subset may be extended to include the measured block parameters of other semiconductor devices on the same wafer that share this orientation.
  • the tolerance window may be predefined. Although this approach yields less a stringent tolerance windows compared to a tolerance window calculated from all measured block parameters, this approach reduces test time and avoids the inclusion of parameters of potentially faulty blocks in the calculation of the tolerance window.
  • the method further comprises the steps of defining a further tolerance window having an upper limit and a lower limit; determining, for each measured block parameter, if the measured block parameter falls inside the further tolerance window; and classifying the semiconductor device as faulty if at least one of the measured block parameters falls outside the further tolerance window.
  • the further tolerance window may for instance be an absolute tolerance window that is governed by the applied process technology. This has the advantage that if a semiconductor device has a narrow distribution of its measured block parameter, the semiconductor device can still be rejected if part of its distribution falls outside the absolute tolerance window.
  • Fig. 1 depicts an IC to which the method of the invention is applicable
  • Fig. 2 shows a flowchart of the method of the present invention
  • Fig. 3 depicts a test result from a test applied to two devices using the method of the present invention
  • Fig. 4 depicts an evaluation of test results from a test applied to a batch of semiconductor devices
  • Fig. 5 depicts another evaluation of test results from the test applied to one wafer of said batch
  • Fig. 6 depicts yet another evaluation of test results from the test applied to a single device on the one wafer
  • Fig. 7 shows a scanning electron microscope (SEM) image of a faulty block detected with the method of the present invention
  • Fig. 8 shows a SEM image of the same block when correctly manufactured.
  • Fig. 1 depicts a semiconductor device, i.e. IC 100, suitable for being tested according to the method of the present invention.
  • IC 100 has a plurality of blocks of identical design 110.
  • the functional blocks 110 are I/O pads, but it will be appreciated that other blocks, e.g. memory cells, may be tested using the same approach.
  • IC 100 further has a small number of blocks of identical design 120 and an even smaller number of blocks of identical design 130.
  • test method of the present invention may be applied to small numbers of blocks of identical design, it will be understood that higher confidence levels in the test results are achieved when larger numbers of blocks of identical design are tested, due to the fact that the method of the present invention relies on determining and evaluating statistical spreads of a measured parameter of the blocks of identical design.
  • Fig. 2 depicts a flowchart of an embodiment of the method of the present invention.
  • a semiconductor device is selected for testing.
  • step 210 one of the blocks of identical design of the selected semiconductor device is selected for testing.
  • step 220 a parameter of the selected block is measured and stored, e.g. in the memory of automated test equipment (ATE) or a computer used in the execution of the test method.
  • ATE automated test equipment
  • the selected parameter of each functionally identical block is measured before a target value of this parameter is determined in step 230.
  • the target value ⁇ of this parameter ⁇ may be defined as the average of all measured N block parameter values (N>1 ):
  • an average-based target value is by way of non-limiting example only.
  • the target value may be defined in other known ways, e.g. as a median value.
  • im is defined. These limits define the extent any parameter value ⁇ may deviate from its target value ⁇ .
  • the amount of allowed deviation may be based on a calculated distribution of the N values of ⁇ , e.g. a Gaussian distribution. It will be appreciated that the method of the present invention is equally applicable to other distributions.
  • ⁇ is the standard deviation of the N values of ⁇
  • j is a predefined scaling factor, with 2 ⁇ j ⁇ 5 as preferred range, although values of j outside this range may also be feasible.
  • the method of the present invention may use several different tolerance windows, such as a first window in which the tolerance limits are based on the expected distribution of the N values of ⁇ , and a second window in which the tolerance limits are based on the minimum and maximum allowed values of ⁇ in the applied process technology, e.g. guardband limits.
  • step 250 a measured block parameter value ⁇ is selected, and in step 252, it is determined whether or not a measured block parameter value ⁇ falls inside the tolerance window determined in step 240. If the value ⁇ of the block parameter falls outside this window, the block is marked faulty in step 260. If not all measured block parameters have been evaluated, which is checked in step 254, the steps 250, 252 and, if necessary 260 are repeated until all blocks have been checked, and is repeated until all semiconductor devices have been tested, as checked in step 270, after which the method terminates in step 280.
  • Step 256 loops back to step 250 in this embodiment of the method of the present invention because all block parameter values are pre-measured before the target parameter value and its tolerance window are defined.
  • the calculation of the target parameter value in step 230 is repeated after each measurement of the value ⁇ of a selected block.
  • the target value ⁇ may be determined by calculating the average of all measurements of performed up to and including the last, i.e. most recent, measurement i:
  • the tolerance window should preferably also be updated in step 250 after the determination of ⁇ ,:
  • the block parameter value measured in step 220 is compared against the tolerance window before the updating of the target parameter value and tolerance window.
  • comparison step 252 is performed before update steps 230 and 240 are executed.
  • This alternative is not explicitly disclosed in Fig. 2, but is equally feasible. It will be appreciated that in this alternative the comparison of the very first measured block parameter value will be skipped because no target parameter value is available yet.
  • Step 250 may be skipped in the second main embodiment of the present invention because each measured block value is compared against the appropriate tolerance window before the next block is selected for testing. Hence, block 256 loops back to step 210 in the second main embodiment of the method of the present invention.
  • the above steps may be repeated at different operating conditions, e.g. different temperatures to facilitate the detection of faults that are sensitive to variations in said conditions.
  • the above steps may also be repeated at different stages of the manufacturing process of the device under test (DUT), e.g. at wafer test or at final test after packaging the DUT. This for instance facilitates the monitoring of shifts in the parameter values of the identically designed blocks.
  • DUT device under test
  • different tolerance windows may be used at different stages of the manufacture of the DUT.
  • the set of parameter values from which the tolerance window is calculated is limited to include parameter values from compatible blocks.
  • the orientation of a block can influence the parameter value of the block.
  • the set of parameter values may be limited to include parameter values from only those blocks that share the same orientation on a wafer, e.g blocks on one side of the DUT.
  • the set may be extended to include parameter values of blocks from multiple dies on the wafer that all share this orientation, e.g. all devices in a single row or column on the wafer.
  • the set of parameter values may be based on the parameter values of the identically designed blocks of two neighbouring dies that are oriented on either side of the boundary line between the neighbouring dies, because such blocks, when functioning correctly, typically exhibit very little deviation in behaviour due to their close proximity.
  • Fig. 3 depicts the test results of two devices under test DUT1 and DUT2 using the method of the present invention.
  • a tolerance window 310 is given for DUT1 and a tolerance window 315 is given for DUT2.
  • Measurement 320 indicates that one of the tested blocks of identical design of the DUT1 has a parameter value well outside the tolerance window 310, even though this value still lies within the lower limit 330 and the upper limit 340 of the fixed technology-based specification limits.
  • the parameter values of DUT2 all fall within its tolerance window 315, and these values assume a Gaussian distribution. Consequently, DUT1 has been identified as a faulty device while DUT2 has been cleared.
  • the method of the present invention has been verified using an IC of the applicant (NXP B.V.), and the robustness of the method of the present invention has been compared with other test data evaluation approaches.
  • the selected IC is a 144 pins device having 94 identical general purpose input/output (GPIO) pins.
  • GPIO pin typically is a complex IO pin containing digital circuitry that enables plain input, pull up/down, digital/analog output and further containing ESD protection measures. For each of these pins, the input leakage current (l lh ) at a logic high input level has been determined. In this exercise, the GPIO pins of a batch of ICs from 15 wafers of multiple diffusion lots have been tested this way.
  • the input leakage current has been chosen as parameter by way of example only; other parameters, such as a negative diode value, a low or high output voltage level, or low input leakage current, a pull-up/down current and many other parameters are equally feasible. Other parameters for blocks of identical design other than I/O pins can also be used.
  • Fig. 4 shows the cumulative distribution of the input leakage on pin 48 for the devices from these 15 wafers.
  • the distribution is clearly non-Gaussian; in fact, a double distribution with minor tails is observed. Although the existence of a tail in a distribution is an indication of the presence of a faulty device in the batch, it is not immediately apparent from Fig. 4 which devices are faulty.
  • Fig. 5 shows the cumulative distribution of the high input leakage on pins 43-53 (pin 48 and five neighbouring pins on each side of pin 48) for the devices on a single wafer. Again minor tails are observed in the distribution but it is yet again not evident which devices can be marked as faulty.
  • Fig. 4 shows the cumulative distribution of the input leakage on pin 48 for the devices from these 15 wafers. The distribution is clearly non-Gaussian; in fact, a double distribution with minor tails is observed. Although the existence of a tail in a distribution is an indication of the presence of a faulty device in the batch, it is not immediately apparent from
  • FIG. 6 shows the cumulative distribution the measured input leakage current of all 94 GPIO pins of a single DUT using the method of the present invention.
  • the tail in the distribution is clearly visible and indicated by the arrow. It can be seen that three pins of this DUT clearly fall outside the main distribution and that pin 48 has the most deviating input leakage current.
  • the intra-die test method of the present invention as shown in Fig. 6 has a superior resolution to the inter-die test data evaluation methods shown in Fig. 4 and Fig. 5.
  • the method of the present invention facilitates the detection of a faulty individual block. This can be used to more closely examine the cause for the faulty behaviour in a subsequent failure analysis step. Failure analysis is an indispensable tool for understanding why and where certain faults develop in the manufacturing process so that the manufacturing process can be improved accordingly.
  • Fig. 7 shows the failure analysis by means of SEM imaging of the faulty pin 48 in Fig. 6.
  • Fig. 8 shows a SEM image of a correctly functioning pin of the same semiconductor device.
  • the SEM image of Fig. 7 reveals a problem with the self-aligned suicide (salicide) of the device incorporating faulty pin 48.
  • the rough area in Fig.7 as indicated by the arrow reveals that the salicide top layer has not been fully removed, whereas the smooth layer in the same location in Fig. 8 indicates the successful removal of this top layer.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

L'invention concerne un procédé de test d'un composant à semiconducteur. Le dispositif comprend une pluralité de blocs de conception identique, et le procédé comprend la mesure (220) d'un paramètre de bloc de chaque bloc, le calcul (230) d'une valeur cible pour les paramètres de bloc provenant d'au moins un paramètre de bloc mesuré, la définition (240) d'une fenêtre de tolérance (310, 315) autour de la valeur cible, la détermination (252) pour chaque paramètre de bloc mesuré, si ledit paramètre est à l'intérieur de la fenêtre de tolérance (310, 315), ainsi que le classement (260) du composant à semiconducteur comme étant défaillant si au moins un des paramètres de bloc mesuré est à l'extérieur de la fenêtre de tolérance (310, 315). Ce procédé permet la détection d'un composant à semiconducteur défaillant au moyen de la détection d'écart depuis une répartition statistique pouvant être permise à un paramètre du processus particulier appartenant à un bloc fonctionnellement identique. On démontre que ce procédé de test présente une résolution améliorée par rapport aux procédés bien connus de test entre composants tels que les procédés de test bien connus de tranches
PCT/IB2008/052251 2007-06-12 2008-06-09 Procédé de test à un composant semiconducteur WO2008152557A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP07110132.3 2007-06-12
EP07110132 2007-06-12

Publications (1)

Publication Number Publication Date
WO2008152557A1 true WO2008152557A1 (fr) 2008-12-18

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4961053A (en) * 1985-07-24 1990-10-02 Heinz Krug Circuit arrangement for testing integrated circuit components
US5446395A (en) * 1992-09-22 1995-08-29 Nec Corporation Test circuit for large scale integrated circuits on a wafer
EP1291662A2 (fr) * 2001-05-18 2003-03-12 Sony Computer Entertainment Inc. Système de débogage pour circuit intégré à semi-conducteur
EP1296154A2 (fr) * 2001-09-25 2003-03-26 Kabushiki Kaisha Toshiba Circuit intégré à semi-conducteur

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4961053A (en) * 1985-07-24 1990-10-02 Heinz Krug Circuit arrangement for testing integrated circuit components
US5446395A (en) * 1992-09-22 1995-08-29 Nec Corporation Test circuit for large scale integrated circuits on a wafer
EP1291662A2 (fr) * 2001-05-18 2003-03-12 Sony Computer Entertainment Inc. Système de débogage pour circuit intégré à semi-conducteur
EP1296154A2 (fr) * 2001-09-25 2003-03-26 Kabushiki Kaisha Toshiba Circuit intégré à semi-conducteur

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