WO2008149783A1 - 半導体集積回路及びフィルタ制御方法 - Google Patents

半導体集積回路及びフィルタ制御方法 Download PDF

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Publication number
WO2008149783A1
WO2008149783A1 PCT/JP2008/059974 JP2008059974W WO2008149783A1 WO 2008149783 A1 WO2008149783 A1 WO 2008149783A1 JP 2008059974 W JP2008059974 W JP 2008059974W WO 2008149783 A1 WO2008149783 A1 WO 2008149783A1
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WO
WIPO (PCT)
Prior art keywords
adaptors
distribution
distribution information
request signal
integrated circuit
Prior art date
Application number
PCT/JP2008/059974
Other languages
English (en)
French (fr)
Inventor
Hiroaki Inoue
Masamichi Takagi
Masaki Uekubo
Sunao Torii
Masato Edahiro
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Priority to US12/663,474 priority Critical patent/US8531963B2/en
Priority to JP2009517828A priority patent/JP5287718B2/ja
Publication of WO2008149783A1 publication Critical patent/WO2008149783A1/ja

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L63/00—Network architectures or network communication protocols for network security
    • H04L63/02—Network architectures or network communication protocols for network security for separating internal from external traffic, e.g. firewalls
    • H04L63/0227—Filtering policies
    • H04L63/0263—Rule management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7825—Globally asynchronous, locally synchronous, e.g. network on chip
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L63/00—Network architectures or network communication protocols for network security
    • H04L63/02—Network architectures or network communication protocols for network security for separating internal from external traffic, e.g. firewalls
    • H04L63/0209—Architectural arrangements, e.g. perimeter networks or demilitarized zones
    • H04L63/0218—Distributed architectures, e.g. distributed firewalls

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Theoretical Computer Science (AREA)
  • General Business, Economics & Management (AREA)
  • Computer Security & Cryptography (AREA)
  • Business, Economics & Management (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Multi Processors (AREA)

Abstract

　本発明の半導体集積回路は、複数のコアと、複数のコア毎に接続されたアダプタおよびアダプタ間を通信可能に接続する複数のルータを含む相互結合網１１００とを有し、送信側アダプタ３０００Ｓ１、３０００Ｓ２は、自身に接続された第１のコアから受け取る要求信号の配送条件を示す第１の配送情報を保持し、第１のコアから受信する要求信号の配送を第１の配送情報にしたがって制御し、受信側アダプタ３０００Ｒ１、３０００Ｒ２は、自身に接続された第２のコア宛の要求信号の配送条件を示す第２の配送情報を保持し、相互結合網を介して受信する要求信号に対して第２のコアへの配送を第２の配送情報にしたがって制御し、第１の配送情報および第２の配送情報が階層的に設定されている。
PCT/JP2008/059974 2007-06-08 2008-05-30 半導体集積回路及びフィルタ制御方法 WO2008149783A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/663,474 US8531963B2 (en) 2007-06-08 2008-05-30 Semiconductor integrated circuit and filter control method
JP2009517828A JP5287718B2 (ja) 2007-06-08 2008-05-30 半導体集積回路及びフィルタ制御方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-152795 2007-06-08
JP2007152795 2007-06-08

Publications (1)

Publication Number Publication Date
WO2008149783A1 true WO2008149783A1 (ja) 2008-12-11

Family

ID=40093599

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/059974 WO2008149783A1 (ja) 2007-06-08 2008-05-30 半導体集積回路及びフィルタ制御方法

Country Status (3)

Country Link
US (1) US8531963B2 (ja)
JP (1) JP5287718B2 (ja)
WO (1) WO2008149783A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011125889A1 (ja) * 2010-04-06 2011-10-13 日本電気株式会社 半導体集積回路システム及び半導体集積回路におけるパケット伝送制御方法
JP2021525908A (ja) * 2018-05-24 2021-09-27 テキサス インスツルメンツ インコーポレイテッド システムオンチップファイアウォールメモリアーキテクチャ

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5287718B2 (ja) * 2007-06-08 2013-09-11 日本電気株式会社 半導体集積回路及びフィルタ制御方法
WO2008149784A1 (ja) * 2007-06-08 2008-12-11 Nec Corporation 半導体集積回路及びフィルタ制御方法
JP2012146201A (ja) * 2011-01-13 2012-08-02 Toshiba Corp オンチップルータ及びそれを用いたマルチコアシステム
US9203806B2 (en) 2013-01-11 2015-12-01 Centripetal Networks, Inc. Rule swapping in a packet network
US10560428B2 (en) * 2017-08-17 2020-02-11 Texas Instruments Incorporated Flexible hybrid firewall architecture

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09152990A (ja) * 1995-11-30 1997-06-10 Toshiba Corp アクセス制御システムおよびアクセス制御方法
JPH09231187A (ja) * 1996-02-22 1997-09-05 Hitachi Ltd 並列計算機のデータ転送方法
JP2004234378A (ja) * 2003-01-30 2004-08-19 Fujitsu Ltd セキュリティ管理装置及びセキュリティ管理方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
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US6335939B1 (en) * 1997-08-28 2002-01-01 Advanced Micro Devices, Inc. Apparatus and method for selectively supplying data packets between media domains in a network repeater
JP4588262B2 (ja) 2001-07-04 2010-11-24 富士通株式会社 ルータ及びネットワークにおける一時停止方法
US7069448B2 (en) * 2001-12-05 2006-06-27 Tecsec, Inc. Context oriented crypto processing on a parallel processor array
JP2003204328A (ja) 2002-01-09 2003-07-18 Matsushita Electric Ind Co Ltd 管理装置およびその管理方法
JP4302004B2 (ja) 2004-06-10 2009-07-22 日本電信電話株式会社 パケットフィルタ設定方法およびパケットフィルタ設定システム
US8640194B2 (en) 2004-08-25 2014-01-28 Nec Corporation Information communication device and program execution environment control method
US7877796B2 (en) 2004-11-16 2011-01-25 Cisco Technology, Inc. Method and apparatus for best effort propagation of security group information
FR2883117B1 (fr) 2005-03-08 2007-04-27 Commissariat Energie Atomique Architecture de noeud de communication dans un systeme de reseau sur puce globalement asynchrone.
JP2006302295A (ja) 2006-04-26 2006-11-02 Fuji Xerox Co Ltd ネットワーク接続制御方法および装置
JP5287718B2 (ja) * 2007-06-08 2013-09-11 日本電気株式会社 半導体集積回路及びフィルタ制御方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09152990A (ja) * 1995-11-30 1997-06-10 Toshiba Corp アクセス制御システムおよびアクセス制御方法
JPH09231187A (ja) * 1996-02-22 1997-09-05 Hitachi Ltd 並列計算機のデータ転送方法
JP2004234378A (ja) * 2003-01-30 2004-08-19 Fujitsu Ltd セキュリティ管理装置及びセキュリティ管理方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011125889A1 (ja) * 2010-04-06 2011-10-13 日本電気株式会社 半導体集積回路システム及び半導体集積回路におけるパケット伝送制御方法
JP2021525908A (ja) * 2018-05-24 2021-09-27 テキサス インスツルメンツ インコーポレイテッド システムオンチップファイアウォールメモリアーキテクチャ
JP7469579B2 (ja) 2018-05-24 2024-04-17 テキサス インスツルメンツ インコーポレイテッド システムオンチップファイアウォールメモリアーキテクチャ

Also Published As

Publication number Publication date
US8531963B2 (en) 2013-09-10
US20100183015A1 (en) 2010-07-22
JPWO2008149783A1 (ja) 2010-08-26
JP5287718B2 (ja) 2013-09-11

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