WO2008146389A1 - 電子装置を試験する方法及び装置 - Google Patents

電子装置を試験する方法及び装置 Download PDF

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Publication number
WO2008146389A1
WO2008146389A1 PCT/JP2007/061109 JP2007061109W WO2008146389A1 WO 2008146389 A1 WO2008146389 A1 WO 2008146389A1 JP 2007061109 W JP2007061109 W JP 2007061109W WO 2008146389 A1 WO2008146389 A1 WO 2008146389A1
Authority
WO
WIPO (PCT)
Prior art keywords
electronic device
power supply
testing
testing electronic
repeating turning
Prior art date
Application number
PCT/JP2007/061109
Other languages
English (en)
French (fr)
Inventor
Rikizo Nakano
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2007/061109 priority Critical patent/WO2008146389A1/ja
Priority to JP2009516125A priority patent/JP5024376B2/ja
Publication of WO2008146389A1 publication Critical patent/WO2008146389A1/ja
Priority to US12/556,241 priority patent/US7990172B2/en

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3004—Current or voltage test
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/24—Marginal checking or other specified testing methods not covered by G06F11/26, e.g. race tests
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/06—Acceleration testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2836—Fault-finding or characterising
    • G01R31/2837—Characterising or performance testing, e.g. of frequency response

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

　電子装置の初期劣化不良品を取り除くのに有効なストレス印加ステップを導入した、電子装置の試験方法。一個又は複数個の半導体部品から構成される電子装置を試験する方法が、該電子装置に接続される電源のオン／オフサイクル及び／又は電圧値を変更しつつ電源のオン／オフを繰り返すステップと、前記電源のオン／オフの繰返し後、該電子装置が正常に動作するか否かを確認するステップと、を含むように構成される。
PCT/JP2007/061109 2007-05-31 2007-05-31 電子装置を試験する方法及び装置 WO2008146389A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/JP2007/061109 WO2008146389A1 (ja) 2007-05-31 2007-05-31 電子装置を試験する方法及び装置
JP2009516125A JP5024376B2 (ja) 2007-05-31 2007-05-31 電子装置を試験する方法及び装置
US12/556,241 US7990172B2 (en) 2007-05-31 2009-09-09 Method and apparatus for testing electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/061109 WO2008146389A1 (ja) 2007-05-31 2007-05-31 電子装置を試験する方法及び装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/556,241 Continuation US7990172B2 (en) 2007-05-31 2009-09-09 Method and apparatus for testing electronic device

Publications (1)

Publication Number Publication Date
WO2008146389A1 true WO2008146389A1 (ja) 2008-12-04

Family

ID=40074671

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/061109 WO2008146389A1 (ja) 2007-05-31 2007-05-31 電子装置を試験する方法及び装置

Country Status (3)

Country Link
US (1) US7990172B2 (ja)
JP (1) JP5024376B2 (ja)
WO (1) WO2008146389A1 (ja)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7839160B1 (en) * 2007-03-21 2010-11-23 Marvell International Ltd. Stress programming of transistors
JP5024376B2 (ja) * 2007-05-31 2012-09-12 富士通株式会社 電子装置を試験する方法及び装置
KR20090022603A (ko) * 2007-08-31 2009-03-04 삼성전자주식회사 디바이스 파워 서플라이 확장 회로, 이를 포함하는 테스트시스템 및 반도체 장치의 테스트 방법
CN111552594B (zh) * 2020-04-27 2024-01-02 杭州海康存储科技有限公司 一种固态硬盘掉电检测方法、装置、系统及电子设备

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6363979A (ja) * 1986-09-04 1988-03-22 Hitachi Ltd 半導体部品エ−ジング方法
JPH06118128A (ja) * 1992-10-08 1994-04-28 Fujitsu Ltd 半導体集積回路のバーンイン試験装置
JP2000174081A (ja) * 1998-12-07 2000-06-23 Mitsubishi Electric Corp 半導体チップのバーンイン試験方法、バーンイン試験装置及びバーンイン試験方法に使用する半導体チップ

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2959699B2 (ja) 1993-12-20 1999-10-06 川崎製鉄株式会社 半導体集積回路の加速寿命試験方法
DE10339025B4 (de) * 2002-09-13 2013-08-14 Fuji Electric Co., Ltd. Stromversorgungssystem
JP2004226220A (ja) 2003-01-22 2004-08-12 Matsushita Electric Ind Co Ltd 半導体集積回路、および半導体チップに対するストレス印加量制御方法
US7486098B2 (en) * 2005-06-16 2009-02-03 International Business Machines Corporation Integrated circuit testing method using well bias modification
US7521947B2 (en) * 2006-05-23 2009-04-21 Integrated Technology Corporation Probe needle protection method for high current probe testing of power devices
JP5024376B2 (ja) * 2007-05-31 2012-09-12 富士通株式会社 電子装置を試験する方法及び装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6363979A (ja) * 1986-09-04 1988-03-22 Hitachi Ltd 半導体部品エ−ジング方法
JPH06118128A (ja) * 1992-10-08 1994-04-28 Fujitsu Ltd 半導体集積回路のバーンイン試験装置
JP2000174081A (ja) * 1998-12-07 2000-06-23 Mitsubishi Electric Corp 半導体チップのバーンイン試験方法、バーンイン試験装置及びバーンイン試験方法に使用する半導体チップ

Also Published As

Publication number Publication date
JP5024376B2 (ja) 2012-09-12
US20090322344A1 (en) 2009-12-31
JPWO2008146389A1 (ja) 2010-08-12
US7990172B2 (en) 2011-08-02

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