WO2008143285A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2008143285A1
WO2008143285A1 PCT/JP2008/059350 JP2008059350W WO2008143285A1 WO 2008143285 A1 WO2008143285 A1 WO 2008143285A1 JP 2008059350 W JP2008059350 W JP 2008059350W WO 2008143285 A1 WO2008143285 A1 WO 2008143285A1
Authority
WO
WIPO (PCT)
Prior art keywords
control
circuits
logic
function
fields
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/059350
Other languages
English (en)
French (fr)
Inventor
Yoshifumi Kawamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2009515256A priority Critical patent/JP4852149B2/ja
Priority to US12/600,716 priority patent/US20100153676A1/en
Publication of WO2008143285A1 publication Critical patent/WO2008143285A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17752—Structural details of configuration resources for hot reconfiguration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Logic Circuits (AREA)

Abstract

　可変論理機能を実現するためにそれぞれ記憶回路と制御回路を有する複数の機能再構成セルを備え、真理値データを格納する記憶回路の読み出しアドレスを機能再構成セルそれ自体で自律的に制御する。例えば前記制御回路は記憶回路のデータフィールド及び制御フィールドから同期的に読み出された情報を帰還入力し、制御フィールドからの帰還入力情報に基づいて、データフィールドからの帰還入力情報又は別の情報をデータフィールド及び制御フィールドを次に同期的に読み出し制御するためのアドレス情報とする。真理値データを格納する記憶回路の読み出しを機能再構成セルそれ自体で自律的に制御することができるから、可変論理機能を実現するための記憶回路を論理回路と等価な回路として扱うことができる。実現可能な論理構成や論理規模に融通性を得ることができ、小さなチップ占有面積で大きな論理規模にも対応可能な可変論理機能を実現可能になる。
PCT/JP2008/059350 2007-05-21 2008-05-21 半導体装置 Ceased WO2008143285A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009515256A JP4852149B2 (ja) 2007-05-21 2008-05-21 半導体装置
US12/600,716 US20100153676A1 (en) 2007-05-21 2008-05-21 Semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
PCT/JP2007/060335 WO2008142767A1 (ja) 2007-05-21 2007-05-21 半導体装置
JPPCT/JP2007/060335 2007-05-21

Publications (1)

Publication Number Publication Date
WO2008143285A1 true WO2008143285A1 (ja) 2008-11-27

Family

ID=40031494

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/JP2007/060335 Ceased WO2008142767A1 (ja) 2007-05-21 2007-05-21 半導体装置
PCT/JP2008/059350 Ceased WO2008143285A1 (ja) 2007-05-21 2008-05-21 半導体装置

Family Applications Before (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/060335 Ceased WO2008142767A1 (ja) 2007-05-21 2007-05-21 半導体装置

Country Status (2)

Country Link
US (1) US20100153676A1 (ja)
WO (2) WO2008142767A1 (ja)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8214672B2 (en) * 2009-01-07 2012-07-03 Micron Technology, Inc. Method and systems for power consumption management of a pattern-recognition processor
JP5785357B2 (ja) * 2009-06-25 2015-09-30 スパンション エルエルシー リコンフィグ演算装置を備えるコンピュータシステムおよびリコンフィグ演算装置
US9501705B2 (en) 2009-12-15 2016-11-22 Micron Technology, Inc. Methods and apparatuses for reducing power consumption in a pattern recognition processor
WO2011123151A1 (en) * 2010-04-02 2011-10-06 Tabula Inc. System and method for reducing reconfiguration power usage
US10741226B2 (en) * 2013-05-28 2020-08-11 Fg Src Llc Multi-processor computer architecture incorporating distributed multi-ported common memory modules
GB2537856A (en) * 2015-04-28 2016-11-02 Nordic Semiconductor Asa Communication between intergrated circuits
US9904586B2 (en) * 2015-10-28 2018-02-27 Intel Corporation Interfacing with block-based storage in a processor
CN107423256B (zh) * 2017-03-17 2019-03-01 清华大学 可重构处理器及可重构处理器的时序控制方法
US10541010B2 (en) * 2018-03-19 2020-01-21 Micron Technology, Inc. Memory device with configurable input/output interface
US10635598B2 (en) * 2018-03-30 2020-04-28 Intel Corporation Memory-addressed maps for persistent storage device
US11862217B2 (en) * 2019-02-16 2024-01-02 Tohoku University Device, sensor node, access controller, data transfer method, and processing method in microcontroller
US10969993B2 (en) * 2019-07-25 2021-04-06 Arm Limited Methods and apparatus for reconfiguring nodes and reissuing data access requests
CN114442736B (zh) * 2020-11-02 2023-09-05 芯启源(上海)半导体科技有限公司 基于动态配置接口的时钟配置器、fpga系统

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000516418A (ja) * 1996-08-21 2000-12-05 ネオ・ラム・リミテッド・ライアビリティー・カンパニー 再構成可能な演算システム
JP2006099305A (ja) * 2004-09-29 2006-04-13 Hitachi Ltd プログラマブルｌｓｉのコンフィグレーション制御方法

Family Cites Families (6)

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Publication number Priority date Publication date Assignee Title
US4984192A (en) * 1988-12-02 1991-01-08 Ultrasystems Defense Inc. Programmable state machines connectable in a reconfiguration switching network for performing real-time data processing
US5267187A (en) * 1990-05-10 1993-11-30 Xilinx Inc Logic structure and circuit for fast carry
US6101143A (en) * 1998-12-23 2000-08-08 Xilinx, Inc. SRAM shutdown circuit for FPGA to conserve power when FPGA is not in use
US7103708B2 (en) * 2002-08-10 2006-09-05 Cisco Technology, Inc. Performing lookup operations using associative memories optionally including modifying a search key in generating a lookup word and possibly forcing a no-hit indication in response to matching a particular entry
US7370310B1 (en) * 2005-08-08 2008-05-06 Xilinx, Inc. Static address mapping
US8239658B2 (en) * 2006-02-21 2012-08-07 Cypress Semiconductor Corporation Internally derived address generation system and method for burst loading of a synchronous memory

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000516418A (ja) * 1996-08-21 2000-12-05 ネオ・ラム・リミテッド・ライアビリティー・カンパニー 再構成可能な演算システム
JP2006099305A (ja) * 2004-09-29 2006-04-13 Hitachi Ltd プログラマブルｌｓｉのコンフィグレーション制御方法

Also Published As

Publication number Publication date
US20100153676A1 (en) 2010-06-17
WO2008142767A1 (ja) 2008-11-27

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