WO2008136595A2 - Dispositif et procédé de transmission de données par division de la vitesse - Google Patents

Dispositif et procédé de transmission de données par division de la vitesse Download PDF

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Publication number
WO2008136595A2
WO2008136595A2 PCT/KR2008/002476 KR2008002476W WO2008136595A2 WO 2008136595 A2 WO2008136595 A2 WO 2008136595A2 KR 2008002476 W KR2008002476 W KR 2008002476W WO 2008136595 A2 WO2008136595 A2 WO 2008136595A2
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WO
WIPO (PCT)
Prior art keywords
data
speed
upstream
downstream
terminal device
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PCT/KR2008/002476
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English (en)
Other versions
WO2008136595A3 (fr
Inventor
Hyun Gon Lee
Original Assignee
Seokyo Telecommunication Co., Ltd.
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Application filed by Seokyo Telecommunication Co., Ltd. filed Critical Seokyo Telecommunication Co., Ltd.
Publication of WO2008136595A2 publication Critical patent/WO2008136595A2/fr
Publication of WO2008136595A3 publication Critical patent/WO2008136595A3/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/02—Details
    • H04L12/16—Arrangements for providing special services to substations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/22—Traffic shaping
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/22—Time-division multiplex systems in which the sources have different rates or codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/38—Flow control; Congestion control by adapting coding or compression rate
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/43—Assembling or disassembling of packets, e.g. segmentation and reassembly [SAR]

Definitions

  • the present invention relates to a data speed division transmission apparatus, and more particularly, to a data speed division transmission apparatus for allowing a transmitter to divide a data signal of a terminal device and a receiver to combine the divided data signals received through a plurality of (at least two) links so that the data signal of the terminal device, which has a higher transmission speed than a standard transmission speed (e.g., 2.048 Mbps), can be transmitted through the plurality of links having the standard transmission speed.
  • a standard transmission speed e.g. 2.048 Mbps
  • link aggregation technology for increasing the amount of data transmission using at least two physical transmission links is generally referred to as "link aggregation".
  • link aggregation technology for using at least two Ethernet links to increase a transmission rate of data having a predetermined frame structure as in the Ethernet or technology for dividing and transmitting data using a plurality of 2 Mbps transmission links has already been put to practical use.
  • this technology has been developed for the purpose of maximizing data conversion efficiency when data is divided and transmitted, by which a predetermined frame structure of data is delineated or a predetermined line block code is converted and then data to be transmitted is detected, arranged in bytes, and mapped to transmission links. For this reason, when the frame structure of data is not known or line block encoding is not used for security, this technology cannot be used.
  • the present invention also provides a data speed division transmission apparatus and method for dividing and transmitting data and combining divided data regardless of the frame structure of the data or the use or non-use of a line block code.
  • sequence information is added to each data frame when data is divided and transmitted and a receiver arranges data frames received through different transmission links in order using the sequence information.
  • FIG. 2 is a functional diagram of the data speed division transmission apparatus according to some embodiments of the present invention.
  • FIG. 3 is a detailed block diagram of an upstream speed conversion unit illustrated in
  • FIG. 5 is a detailed block diagram of a downstream speed conversion unit illustrated in FIG. 2.
  • FIG. 6 is a flowchart of the operation of the downstream speed conversion unit illustrated in FIG. 5.
  • FIG. 9 is a timing chart of a speed division unit illustrated in FIG. 2.
  • FIG. 10 illustrates the frame structures of El data in a data speed division transmission apparatus according to some embodiments of the present invention. Best Mode for Carrying Out the Invention
  • a data speed division transmission apparatus for transmitting a data signal of a terminal device having a second speed higher than a first speed, which is a standard transmission speed, through "n" links having the first speed where "n" is 2 or an integer greater than 2.
  • the data speed division transmission apparatus includes a data dividing block configured to divide upstream data of the terminal device having the second speed into "n" divided upstream data, convert a speed of the divided upstream data into the first speed, and transmit the divided upstream data having the first speed to standard transmission devices respectively connected with the "n” links so that the divided upstream data are transmitted through the respective "n” links; and a data combining block configured to combine "n" downstream data received at the first speed from the standard transmission devices respectively connected with the "n” links according to a clock signal corresponding to the second speed and transmit combined data to the terminal device at the second speed.
  • the first speed may be an El transmission speed
  • Each of the first through n-th downstream speed conversion units may include a frame analyzer configured to track a frame of the downstream data, detect frame synchronization and a frame start position, and generate a sync state flag signal and a receiving frame start position signal; a sequence information analyzer configured to extract sequence information from a frame subjected to synchronization, detect a sequence number, and generate a sequence start flag signal when the sequence number is a predetermined initial value; and a downstream elastic buffer configured to write the downstream data based on the sync state flag signal, the receiving frame start position signal, and the sequence start flag signal.
  • the data speed division transmission method includes a data dividing operation of dividing upstream data received from the terminal device into "n" divided upstream data, respectively storing the divided upstream data in upstream elastic buffers, converting a speed of the divided upstream data stored in the respective upstream elastic buffers into the standard transmission speed, and respectively transmitting the divided upstream data having the standard transmission speed to standard transmission devices respectively connected with the "n” links so that the divided upstream data are transmitted through the respective "n” links; and a data combining operation of respectively storing "n” divided downstream data received from the standard transmission devices respectively connected with the "n” links in downstream elastic buffers, combining the divided downstream data stored in the downstream elastic buffers according to a clock signal corresponding to a speed of the terminal device, and transmit combined data to the terminal device.
  • FIG. 1 is a schematic diagram illustrating communication network connection using a data speed division transmission apparatus 102 according to some embodiments of the present invention.
  • the data speed division transmission apparatus 102 is interposed between a terminal device 101 having a transmission speed of over 2.048 Mbps, i.e., m*2.048 Mbps (e.g., 4 Mbps, 6 Mbps, or 8 Mbps) and a transmission network 103 having a plurality of 2.048 Mbps (hereinafter, referred to as El) transmission links.
  • the data speed division transmission apparatus 102 divides the transmission speed of the terminal device 101 into a plurality of El transmission speeds to match with the El transmission links and transmits data through the plurality of ("n") Eltransmission link s, and vice versa.
  • Transmission delay occurring when the plurality of El transmission links have different paths is compensated for by inserting a frame sequence number into data transmitted from a transmitter and synchronizing the El transmission links based on the frame sequence number at a receiver.
  • the data speed division transmission apparatus 102 may be interposed between the terminal device 101 and the transmission network 103 such that the terminal device 101 having a transmission speed of at least 4 Mbps is connected with the transmission network 103 having the plurality of El transmission links in a communication network.
  • the transmission network 103 may include a ple- siochronous digital hierarchy (PDH) or synchronous digital hierarchy (SDH) transmission device having the plurality of El transmission links.
  • PDH ple- siochronous digital hierarchy
  • SDH synchronous digital hierarchy
  • the data speed division transmission apparatus 102 transmits inter-El link frame synchronization information and sequence number information for transmission delay compensation together with data received from the terminal device 101 when it devices the speed of the terminal device 101 into a plurality of El transmission speeds.
  • another El transmission link is required. For instance, when the terminal device 101 has a speed of 4 Mbps, three El transmission links are required. When the terminal device 101 has a speed of 6 Mbps, four El transmission links are required. When the terminal device 101 has a speed of 8 Mbps, five El transmission links are required.
  • a terminal device has a speed of 4 Mbps for clarity of the description, but the same principle is applied when the speed of the terminal device is different (e.g., 6 Mbps or 8 Mbps), with the exception that the number of bits allocated to each link is different when a different number of (e.g., 4 or 5) transmission links are used.
  • an upstream is a direction from a terminal device to a transmission network and a downstream is an opposite direction.
  • FIG. 2 is a functional diagram of the data speed division transmission apparatus 102 according to some embodiments of the present invention.
  • the data speed division transmission apparatus 102 includes a data dividing/combining block 200, a terminal device matching block 210, and a device management block 270.
  • the data dividing/combining block 200 includes a terminal speed conversion unit 220, a clock generation unit 260, and first through third speed division units 230, 240, and 250.
  • the terminal device matching block 210 is connected with the terminal device 101 having a data speed (hereinafter, referred to as a "terminal device speed") of 4 Mbps.
  • the terminal device matching block 210 detects a signal system matching with an electrical interface such as V.35, RS530, G.703, or HSSI of the terminal device 101, extracts a terminal speed clock signal (hereinafter, referred to as a "terminal device receiving clock signal") TE RCLK corresponding to the upstream terminal device speed (e.g., 4 Mbps) input from the terminal device 101, and performs signal level conversion.
  • a terminal speed clock signal hereinafter, referred to as a "terminal device receiving clock signal”
  • the first through third speed division units 230, 240, and 250 divide data TTD input at the upstream terminal device speed from the terminal device matching block 210 into three segments and converts the speed of each segment into an El transmission speed, and they perform vice versa.
  • the first through third speed division units 230, 240, and 250 include upstream speed conversion units 231, 241, and 251, downstream speed conversion units 232, 242, and 252, and transmission device matching units 233, 243, and 253.
  • Each of the upstream speed conversion units 231, 241, and 251 converts the speed of divided upstream data, which is allocated thereto among the three segments of the data TTD received at the upstream terminal device speed from the terminal device matching block 210, into an upstream El transmission speed.
  • a data dividing block and a data combining block are not distinguished, but the upstream speed conversion units 231, 241, and 251 belong to the data dividing block.
  • Each of the transmission device matching units 233, 243, and 253 receives divided upstream El data El TD [i] at the upstream El transmission speed from the upstream speed conversion unit 231, 241, or 251, performs signal conversion so that the divided upstream El data El TD[i] matches with an El transmission device (not shown), and sends a converted data to the El transmission device.
  • Each of the transmission device matching units 233, 243, and 253 performs line coding such as HDB 3 for normal communication with the El transmission device, converts a monopolar signal into a bipolar signal, and extracts a downstream El transmission speed clock signal El RC[i] corresponding to a downstream El transmission speed input from the El transmission device (not shown).
  • i denotes a signal having a particular function or feature, but may be an identifier 1, 2, or 3 used to distinguish signals generated in the first through third speed division units 230, 240, and 250.
  • the transmission device matching units 233, 243, and 253 are shared by the data dividing block and the data combining block.
  • the El transmission device (not shown) is connected with a corresponding one among a plurality of ("n") El transmission links and transmits a signal, i.e., upstream El data received from the transmission device matching unit 233, 243, or 253 through the El transmission link or transmits a signal, i.e., downstream El data received through the El transmission link to the transmission device matching unit 233, 243, or 253.
  • the upstream El data and the downstream El data are data obtained through division so that they can be separately transmitted through the plurality of ("n") El transmission links.
  • Each of the downstream speed conversion units 232, 242, and 252 converts the speed of divided downstream El data El RD [i] input at a downstream El transmission speed from the corresponding transmission device matching unit 233, 243, or 253, thereby generating divided downstream data RD [i].
  • the upstream El transmission speed and the downstream El transmission speed may be the same as the speed of the El transmission device (e.g., 2.048 Mbps).
  • the first through third speed division units 230, 240, and 250 have the same structures and functions, and therefore, among them only the first speed division unit 230 will be described in detail for the shake of convenience.
  • the terminal speed conversion unit 220 converts the speed of three divided downstream data RD [i] received from the first through third speed division units 230, 240, and 250 into a downstream terminal speed to recover an original data speed.
  • An upstream terminal speed and a downstream terminal speed may be the same as the speed of a terminal device (e.g., 4 Mbps).
  • the downstream speed conversion units 232, 242, and 252 and the terminal speed conversion unit 220 belong to the data combining block for combining data.
  • the clock generation unit 260 generates and provides clock signals and control signals TE RCLK, TE TCLK, TC[1,2,3], RC[1,2,3], TFR, and El TC for other elements.
  • the device management block 270 manages the overall operation of the data speed division transmission apparatus 102.
  • FIG. 3 is a detailed block diagram of the upstream speed conversion unit 231, 241, or
  • FIG. 9 is a timing chart of the first through third speed division units 230, 240, and 250 illustrated in FIG. 2.
  • FIG. 10 illustrates the frame structures of El data (i.e., upstream El data or downstream El data) in the data speed division transmission apparatus 102 according to some embodiments of the present invention.
  • the upstream speed conversion units 231, 241, and 251 include an upstream elastic buffer 310, an upstream elastic buffer controller 320, an El frame generator 330, a sequence information generator 340, a management information transmission matching unit 350, an upstream common controller 360, and an upstream data multiplexer 370.
  • the upstream speed conversion units 231, 241, and 251 process 512 bits in a bitstream of terminal data TTD continuously input from the terminal device matching block 210 as one data block.
  • the size of the data block is not limited to 512 bits and may vary with the transmission speed of the terminal device 101.
  • the upstream elastic buffer 310 of the upstream speed conversion unit 231 of the first speed division unit 230 writes 171 bits thereto in a data bitstream from the first bit through the 512th bit of a data block by way of writing every third bits from the first bit to the 51 lth bit, i.e., 1st, 4th, 7th, ..., 51 lth according to a first write clock TC[I] provided from the clock generation unit 260, as illustrated in FIG. 9.
  • the upstream elastic buffer 310 of the upstream speed conversion unit 241 of the second speed division unit 240 writes 171 bits thereto in the data bitstream from the first bit through 512th bit of the data block by way of writing every third bits from the second bit to the 512th bit, i.e., 2nd, 5th, 8th, ..., 512th according to a second write clock TC[2] provided from the clock generation unit 260.
  • the upstream elastic buffer 310 of the upstream speed conversion unit 251 of the third speed division unit 250 writes 170 bits thereto in the data bitstream from the first bit through 512th bit of the data block by way of writing every third bits from the third bit to the 510th bit, i.e., 3rd, 6th, 9th, ..., 510th according to a third write clock TC[3] provided from the clock generation unit 260.
  • the upstream speed conversion units 231, 241, and 251 together write 512 bits to their upstream elastic buffers 310 as a single data block in the same manner as that described above.
  • data written to each upstream elastic buffer 310 is referred to as divided terminal data (or divided upstream terminal data).
  • the first through third write control signals WRC[i] are obtained by dividing the frequency of the terminal device receiving clock signal TE RCLK by 3 and are activated at every three clocks of the terminal device receiving clock signal TE RCLK.
  • the first through third write control signals WRC[i] are alternately activated at every clock of the terminal device receiving clock signal TE RCLK in order from the first to the third write control signal WRC[i]. Accordingly, the bitstream of the terminal data TTD is sequentially written to the upstream elastic buffer 310 of the first speed division unit 230, the upstream elastic buffer 310 of the second speed division unit 240, and the upstream elastic buffer 310 of the third speed division unit 250.
  • the upstream El transmission speed clock signal El TC is obtained by dividing the frequency of the terminal device receiving clock signal TE RCLK and is generated by the clock generation unit 260. The structure and the operation of the clock generation unit 260 will be described in detail later.
  • the upstream elastic buffer 310 selectively writes bits in the bitstream of the terminal data TTD in response to the write control signal WRC[i] received from the upstream elastic buffer controller 320 and the write clock signal TC[i] received from the clock generation unit 260 and outputs the written divided terminal data in response to the read control signal RDC[i] received from the upstream elastic buffer controller 320 and the upstream El transmission speed clock signal El TC received from the clock generation unit 260.
  • the upstream elastic buffer controller 320 generates and provides the write control signal WRC[i] and the read control signal RDC[i] to the upstream elastic buffer 310 in response to the write clock signal TC[i] and a buffer control signal BUF CTRL received from the upstream common controller 360.
  • the buffer control signal BUF CTRL controls the overall timing of the three speed division units 230, 240, and 250.
  • the upstream common controller 360 generates the buffer control signal BUF CTRL, a frame control signal FR CTRL, a sequence control signal SEQ CTRL, and a management information control signal OAM CTRL in response to the write clock signal TC[i], a transmission frame start position signal TER, and the upstream El transmission speed clock signal El TC.
  • the frame control signal FR CTRL, the sequence control signal SEQ CTRL, and the management information control signal OAM CTRL are illustrated in FIG. 10.
  • the El frame generator 330 generates frame information in response to the upstream
  • the frame information may be a predefined signal allowing a receiver to find the start position of a frame.
  • the frame control signal FR CTRL is activated at a position of the first to eighth bits of the frame comprised of 256 bits, as illustrated in FIG. 10.
  • the sequence information generator 340 generates sequence numbers respectively having values from 0 to 255 in response to the upstream El transmission speed clock signal El TC and the sequence control signal SEQ CTRL.
  • the sequence control signal SEQ CTRL is activated at a position of the ninth to sixteenth bits of the frame comprised of 256 bits, as illustrated in FIG. 10.
  • a sequence number generated by the sequence information generator 340 starts from
  • the management information transmission matching unit 350 outputs 8-bit management information generated by the device management block 270 in response to the upstream El transmission speed clock signal El TC and the management information control signal OAM CTRL.
  • the management information control signal OAM CTRL is activated at a position of the 249th to 256th bits of the frame comprised of 256 bits, as illustrated in FIG. 10.
  • the management information of the device management block 270 is transmitted using a spare region in an El frame structure excluding a region for divided terminal data corresponding to service information of the terminal device 101 to accomplish remote device control, so that it is convenient to control devices.
  • a frame of the upstream El data is comprised of 256 bits (from the first bit to 256th bit).
  • the upstream data multiplexer 370 of the third upstream speed conversion unit 251 inserts frame information generated by the El frame generator 330 to a position of the first through eighth bits FO to F7 in a frame of upstream El data El TD [i], inserts a sequence number generated by the sequence information generator 340 to a position of the ninth to 16th bits SO to S7, inserts 170-bit divided terminal data DT Data output from the upstream elastic buffer 310 to a position of the 17th to 187th bits, inserts null data with logic values 1 and 0 repeated to a position of the 188th to 248th bits, and inserts 8-bit management information OAM transmitted from the management information transmission matching unit 350 to a position of the 249th to 256th bits, thereby generating the upstream El data El TD[3] comprised of 256 bits.
  • the upstream El data El TD [i] output from the upstream data multiplexer 370 in each of the first through third upstream speed conversion units 231, 241, and 251 is transmitted to the corresponding transmission device matching unit 233, 243, or 253.
  • Each transmission device matching unit 233, 243, or 253 receives the upstream El data El TD[i] having the upstream El transmission speed, performs signal processing (e.g., line coding and conversion of a monopolar signal into a bipolar signal) necessary for matching with an El transmission device (not shown) on the upstream El data El TD[i], and then transmits processed El data to the El transmission device (not shown).
  • signal processing e.g., line coding and conversion of a monopolar signal into a bipolar signal
  • FIG. 4 is a flowchart of the operation of the upstream speed conversion unit 231 .
  • the upstream speed conversion unit 231, 241, or 251 determines whether the state of a terminal device is effective, that is, whether data can be effectively received from the terminal device in operation SI lO. When it is determined that the state is effective, the upstream speed conversion unit 231, 241, or 251 determines whether the first pulse of a transmission frame start position signal TFR has been generated in operation S 120. When it is determined that the state is not effective, the upstream speed conversion unit 231, 241, or 251 performs initialization in operation S 130. The initialization include resetting the upstream elastic buffer 310, resetting the sequence information generator 340, and setting a buffer read flag signal to an initial value of "0". The buffer read flag signal is one of flag signals which can be generated by the upstream speed conversion unit 231, 241, or 251 and indicates that the read operation of the upstream elastic buffer 310 can be performed.
  • the upstream speed conversion unit 231, 241, or 251 writes receiving information (i.e., data received from the terminal device) to the upstream elastic buffer 310 in operation S 140.
  • a write unit may be a predetermined data block (e.g., 512 bits). The receiving information is written in response to the transmission frame start position signal TFR to achieve frame synchronization.
  • the upstream elastic buffer empty flag signal EF is one of the flag signals that can be generated by the upstream speed conversion unit 231, 241, or 251 and indicates whether writing of the data block to the upstream elastic buffer 310 has been completed. Cancellation of the upstream elastic buffer empty flag signal EF indicates that the data block has completely been written to the upstream elastic buffer 310.
  • the upstream speed conversion unit 231, 241, or 251 sets sequence information to an initial value (e.g., "0"), sets the buffer read flag signal to "1", and outputs the data written to the upstream elastic buffer 310 in operation S 170.
  • FIG. 5 is a detailed block diagram of the downstream speed conversion unit 232
  • the downstream speed conversion unit 232, 242, or 252 includes a downstream elastic buffer 510, a downstream elastic buffer controller 520, an El frame analyzer 530, a sequence information analyzer 540, a management information receiving matching unit 550, and a downstream common controller 560.
  • the El frame analyzer 530 receives downstream El data El RD[i] and a downstream
  • El transmission speed clock signal El RC[i] from the corresponding transmission device matching unit 233, 243, or 253.
  • the downstream El data El RD [i] is divided El data received through an El link and an El transmission device (not shown) connected with the El link and has the same frame structure as that defined in FIG. 10.
  • the downstream El transmission speed clock signal El RC[i] is a clock signal corresponding to a downstream El transmission speed which the transmission device matching unit 233, 243, or 253 extracts from El data received from the El transmission device.
  • the downstream El transmission speed clock signal El RC[i] and the upstream El transmission speed clock signal El TC may have an El transmission speed 2.048 Mbps.
  • the El frame analyzer 530 tracks a frame of the downstream El data El RD [i], detects the position of the frame, and generates a sync state flag signal SYNC[i] and a receiving frame start position signal RFR[i]. For instance, the El frame analyzer 530 may detect the start position of a frame and acquire frame synchronization by finding out predetermined frame information. After acquiring El frame synchronization, the El frame analyzer 530 generates the sync state flag signal SYNC[i] and generates a pulse of the receiving frame start position signal RFR[i] at the start position of each frame.
  • the sequence information analyzer 540 extracts sequence information from a sequence information position (i.e., a position from the 9th to 16th bits SO through S7) of a synchronized frame, identifies a sequence number, and generates a sequence start flag signal STS [i] at a frame corresponding to a sequence number "0".
  • the management information receiving matching unit 550 extracts management information from a management in- formation position (i.e., a position from the 249th to 256th bits) of a frame and transmits the management information to the device management block 270 (FIG. 2) when receiving effective management information.
  • a management in- formation position i.e., a position from the 249th to 256th bits
  • the downstream common controller 560 In response to the downstream El transmission speed clock signal El RC[i], the receiving frame start position signal RFR[i], the sequence start flag signal STS [i], and the sync state flag signal SYNC[i], the downstream common controller 560 generates a buffer control signal BUF CTRL, the frame control signal FR CTRL, the sequence control signal SEQ CTRL, and the management information control signal OAM CTRL.
  • the frame control signal FR CTRL, the sequence control signal SEQ CTRL, and the management information control signal OAM CTRL are illustrated in FIG. 10.
  • the downstream elastic buffer controller 520 In response to a read clock RC[i] and the buffer control signal BUF CTRL received from the downstream common controller 560, the downstream elastic buffer controller 520 generates and provides a write control signal WRC[i] and a read control signal RDC[i] to the downstream elastic buffer 510.
  • the downstream elastic buffer 510 writes the downstream El data El RD[i] according to the downstream El transmission speed clock signal El RC[i] in response to the write control signal WRC [i].
  • the downstream elastic buffer 510 also outputs data, which has already been written thereto, according to a read clock signal RC [i] in response to the read control signal RDC[i] received from the downstream elastic buffer controller 520.
  • the downstream El data El RD[i] is subjected to frame synchronization and sequence synchronization and is then written to the downstream elastic buffer 510 at the El transmission speed according to the write control signal WRC [i] of the downstream elastic buffer controller 520.
  • the downstream El data El RD [i] is written to the downstream elastic buffer 510 in the same order of bits as the corresponding speed division unit 230, 240, and 250 generates a divided upstream data, as illustrated in FIG. 9.
  • the terminal speed conversion unit 220 combines divided downstream terminal data received from the downstream speed conversion units 232, 242, and 252 according to the read clock signals RC[I, 2, 3] and recovers combined data to an original speed according to a terminal device transmission clock signal TE TCLK and then transmits it to the terminal device 101 through the terminal device matching block 210.
  • FIG. 6 is a flowchart of the operation of the downstream speed conversion unit 232.
  • the downstream speed conversion unit 232, 242, or 252 determines whether an El sync state flag signal SYNC has been generated or activated in operation S210, determines whether a pulse of a receiving frame start position signal RFR has been generated in operation S220 when it is determined that the El sync state flag signal SYNC has been generated, and performs initialization in operation S230 when it is determined that the El sync state flag signal SYNC has not been generated. Operations S210 through S230 are performed to regard data received before El synchronization as invalid and effectively write data received after the El synchronization to the downstream elastic buffer 510.
  • the initialization includes resetting the downstream elastic buffer 510, resetting the sequence information analyzer 540, and setting a buffer read flag signal to an initial value ("0").
  • the buffer read flag signal is one of flag signals that may be generated by the downstream speed conversion unit 232, 242, or 252 and indicates that the read operation of the downstream elastic buffer 510 can be performed.
  • the downstream speed conversion unit 232, 242, or 252 determines whether a receiving sequence number of a receiving frame is 0 in operation S240. When it is determined that the receiving sequence number is 0, the downstream speed conversion unit 232, 242, or 252 sets the buffer read flag signal to " 1 " and writes receiving data (or downstream El data El RD [i]) to the downstream elastic buffer 510 in operation S250. At this time, a write unit may be a predetermined data block (e.g., 512 bits). The receiving data is written in response to the receiving frame start position signal RFR to achieve frame synchronization. The receiving sequence number is determined to be 0 to write beginning with a frame having a receiving sequence number of 0.
  • the downstream speed conversion unit 232, 242, or 252 determines whether another pulse of the receiving frame start position signal RFR has been generated and whether an other buffer read flag signal is 1 in operation S260. When it is determined that the another pulse of the receiving frame start position signal RFR has been generated and that the other buffer read flag signal is 1, the downstream speed conversion unit 232, 242, or 252 outputs the data written to the downstream elastic buffer 510 in operation S270. When the other buffer read flag signal is 1, another downstream elastic buffer 510 can also perform a read operation, that is, a frame having the same sequence number (e.g., 0) has been received by the another downstream elastic buffer 510.
  • the other buffer read flag signal is checked in order to output data written to each of the downstream elastic buffers 510 when frames having the same sequence number have been received by the downstream elastic buffers 510.
  • FIG. 7 is a detailed diagram of the clock generation unit 260 illustrated in FIG. 2.
  • the clock generation unit 260 includes an upstream clock generator 710 and a downstream clock generator 720.
  • the upstream clock generator 710 includes a 1/8 divider 711, a selector 712, a 1/3 divider 713, a 1/2 divider 714, and a 1/256 divider 715.
  • the 1/8 divider 711 divides the frequency of an oscillator clock signal OSC_CLK (e.g., 32.768 MHz) by 8 and generates a frequency-divided clock signal CLK4M having a frequency of about 4 MHz.
  • the selector 712 is a 2:1 selector and selectively outputs the frequency-divided clock signal CLK4M or a terminal device receiving clock signal TE RCLK.
  • the terminal device receiving clock signal TE RCLK is a clock signal extracted from data received from the terminal device 101.
  • the selector 712 selects and outputs the terminal device receiving clock signal TE RCLK in a data communication equipment (DCE) mode and selects and outputs the frequency-divided clock signal CLK4M in a data terminal equipment (DTE) mode.
  • DCE data communication equipment
  • CLK4M frequency-divided clock signal
  • the DTE mode or the DCE mode may be set according to the setting of the device management block 270.
  • the terminal device matching block 210 in FIG. 2 should switch the receiving clock signal TE RCLK between the DTE mode and the DCE mode so as to match with various interface conditions such as V.35, RS530, G.703, and HSSI.
  • a clock signal is extracted from data received from the terminal device 101 in the DCE mode and a clock signal is generated in the data speed division transmission apparatus 102 in the DTE mode.
  • the 1/3 divider 713 divides the frequency of an output signal of the selector 712, i.e., the terminal device receiving clock signal TE RCLK, by 3 and provides write clock signals TC[I, 2, 3]. Accordingly, the write clock signals TC[I, 2, 3] for the upstream elastic buffer 310 are clock signals corresponding to "terminal device speed/3".
  • the 1/2 divider 714 divides the frequency of the output signal of the selector 712, i.e., the terminal device receiving clock signal TE RCLK by 2 and provides an upstream El transmission speed clock signal El TC having a frequency of about 2 MHz.
  • the 1/256 divider 715 divides the frequency of the upstream El transmission speed clock signal El TC by 256 and generates a transmission frame start position signal TFR.
  • the downstream clock generator 720 includes a frequency multiplier 721, a 1/3 divider 722, and first through third AND gates 723, 724, and 725.
  • the frequency multiplier 721 multiplies the frequency of a downstream El transmission speed clock signal El RC[I] by 2 and generates a clock signal corresponding to double of an El transmission speed as a terminal device transmission clock signal TE TCLK.
  • the downstream El transmission speed clock signal El RC[I] received from the transmission device matching unit 233 of the first speed division unit 230 may be used, but a downstream El transmission speed clock signal El RC[2] or El RC[3] received from another transmission device matching unit 243 or 253 may be used.
  • FIG. 8 is a detailed diagram of the terminal speed conversion unit 220 illustrated in FIG. 2.
  • Each of the first through fourth flip-flops 810, 820, 830, and 850 may be im- plemented by a D-Q flip-flop.
  • the first flip-flop 810 latches divided downstream data RD[I] output from the downstream elastic buffer 510 in response to a read clock signal RC[I].
  • each of the second and third flip-flops 820 and 830 latches divided downstream data RD[2] or RD[3] output from the corresponding downstream elastic buffer 510 in response to a read clock signal RC[2] or RC[3].
  • the OR gate 840 performs an OR operation on data output from the first through third flip-flops 810, 820, and 830.
  • the fourth flip-flop 840 latches output data of the OR gate 840 in response to the terminal device transmission clock signal TE TCLK, thereby outputting the data TRD in which the divided downstream data RD[I], RD[2], and RD[3] are combined at the terminal device speed.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Communication Control (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

L'invention concerne un dispositif et un procédé de transmission de données par division de la vitesse. Le dispositif de transmission de données par division de la vitesse s'utilise pour transmettre un signal de donnée émis par un dispositif terminal, dont la vitesse est supérieure à une vitesse de transmission normale via n 'maillons' affecté de la vitesse de transmission normale, 'n' valant 2 ou étant un entier supérieur à 2. Le dispositif de transmission de données par division de la vitesse comprend un bloc diviseur de données qui divise les données amont reçues du dispositif terminal en 'n' données amont divisées, stocke les données amont divisées en tampons élastiques amont, convertit une vitesse des données amont divisées stockées dans les tampons élastiques amont en vitesse de transmission normale, et transmet les données amont divisées à vitesse de transmission normale à des dispositifs de transmission normaux connectés respectivement aux 'n' maillons de sorte que les données amont divisées sont transmises par les 'n' liaisons correspondantes; et un bloc de combinaison de données qui stocke 'n' données amont divisées reçues des dispositifs de transmission standard connectés aux 'n' maillons dans les tampons élastiques aval combine les données aval divisées stockées dans les tampons élastiques aval selon un signal d'horloge correspondant à une vitesse du dispositif terminal, et transmet les données combinées au dispositif terminal.
PCT/KR2008/002476 2007-05-03 2008-04-30 Dispositif et procédé de transmission de données par division de la vitesse WO2008136595A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2007-0042869 2007-05-03
KR1020070042869A KR100758183B1 (ko) 2007-05-03 2007-05-03 데이터 속도 분할 전송 장치 및 그 방법

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WO2008136595A2 true WO2008136595A2 (fr) 2008-11-13
WO2008136595A3 WO2008136595A3 (fr) 2008-12-31

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KR100951437B1 (ko) 2008-07-01 2010-04-13 주식회사 장광엔지니어링 다기능 디지털 신호 변환 장치
KR101636029B1 (ko) 2010-03-23 2016-07-20 삼성전자주식회사 다중 셀 다중 안테나 시스템에서 레이트 스플리팅 기법을 사용하기 위한 빔포밍 방법 및 장치

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000078163A (ja) * 1998-08-28 2000-03-14 Nec Eng Ltd 速度変換アダプタ
JP2003023406A (ja) * 2001-07-05 2003-01-24 Nec Access Technica Ltd バルク伝送装置及びこれに用いられる制御プログラム、並びにバルク伝送装置の制御方法
US6574191B1 (en) * 1998-08-09 2003-06-03 Nec Corporation Line switching system and method

Family Cites Families (3)

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Publication number Priority date Publication date Assignee Title
MY106680A (en) * 1989-02-28 1995-07-31 Whitaker Corp Zero insertion force connector for cable to board applications
KR20010047796A (ko) * 1999-11-23 2001-06-15 김훈철 축 시일이 없는 전동펌프
KR20190000880A (ko) * 2018-12-27 2019-01-03 김영문 제 3 차량의 서치라이트에 의한 운전 방해 방지 기능이 구비된 택시 운전석 보호장치

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6574191B1 (en) * 1998-08-09 2003-06-03 Nec Corporation Line switching system and method
JP2000078163A (ja) * 1998-08-28 2000-03-14 Nec Eng Ltd 速度変換アダプタ
JP2003023406A (ja) * 2001-07-05 2003-01-24 Nec Access Technica Ltd バルク伝送装置及びこれに用いられる制御プログラム、並びにバルク伝送装置の制御方法

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