WO2008133940A3 - Serialization of data in multi-chip bus implementation - Google Patents

Abstract

Bus communication for components of a system on a chip. In one aspect of the invention, a serializer for interfacing bus communications for a slave or from a master in a bus system includes one or more shift registers that serialize information to send over a communication bus and deserialize information received from the communication bus. In one aspect of the invention, a system including bus communication to a slave includes a bridge operative to interface a first bus protocol to a bus matrix that uses a second bus protocol. A first serializer provided on a first device serializes information received from the matrix or bridge and sends the serialized information over a communication bus. A second serializer provided on a second device receives the serialized information and deserializes the serialized information, where the deserialized information is provided to a peripheral provided on the second device. In an aspect, a mechanism provides parallel bus information from a bus matrix or from a master to the shift registers for serialization and communication to the slave or to the master, and where the mechanism provides deserialized information received from the shift registers to a bus matrix or the master. The mechanism inserts one or more wait cycles in communication with the matrix or the master during the serialization and deserialization.