WO2008133437A1 - Procédé d'émission et de réception d'un signal et appareil d'émission et de réception d'un signal - Google Patents

Procédé d'émission et de réception d'un signal et appareil d'émission et de réception d'un signal Download PDF

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Publication number
WO2008133437A1
WO2008133437A1 PCT/KR2008/002327 KR2008002327W WO2008133437A1 WO 2008133437 A1 WO2008133437 A1 WO 2008133437A1 KR 2008002327 W KR2008002327 W KR 2008002327W WO 2008133437 A1 WO2008133437 A1 WO 2008133437A1
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WO
WIPO (PCT)
Prior art keywords
data
symbol
signal
fec
output
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Application number
PCT/KR2008/002327
Other languages
English (en)
Inventor
Woo Suk Ko
Sang Chul Moon
Original Assignee
Lg Electronics Inc.
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Filing date
Publication date
Application filed by Lg Electronics Inc. filed Critical Lg Electronics Inc.
Publication of WO2008133437A1 publication Critical patent/WO2008133437A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
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    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
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    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
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    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/02—Arrangements for detecting or preventing errors in the information received by diversity reception
    • H04L1/04—Arrangements for detecting or preventing errors in the information received by diversity reception using frequency diversity
    • H—ELECTRICITY
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    • H04L1/02—Arrangements for detecting or preventing errors in the information received by diversity reception
    • H04L1/06—Arrangements for detecting or preventing errors in the information received by diversity reception using space diversity
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    • H04L27/2602—Signal structure
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    • H04L27/2613—Structure of the reference signals
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    • H04N21/438—Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
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    • H04N21/442—Monitoring of processes or resources, e.g. detecting the failure of a recording device, monitoring the downstream bandwidth, the number of times a movie has been viewed, the storage space available from the internal hard disk
    • H04N21/4425—Monitoring of client processing errors or hardware failure
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    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
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    • H04N21/60—Network structure or processes for video distribution between server and client or between remote clients; Control signalling between clients, server and network components; Transmission of management data between server and client, e.g. sending from server to client commands for recording incoming content stream; Communication details between server and client 
    • H04N21/63—Control signaling related to video distribution between client, server and network components; Network processes for video distribution between server and clients or between remote clients, e.g. transmitting basic layer and enhancement layers over different transmission paths, setting up a peer-to-peer communication via Internet between remote STB's; Communication protocols; Addressing
    • H04N21/647—Control signaling between network components and server or clients; Network processes for video distribution between server and clients, e.g. controlling the quality of the video stream, by dropping packets, protecting content from unauthorised alteration within the network, monitoring of network load, bridging between two different networks, e.g. between IP and wireless
    • H04N21/64784—Data processing by the network
    • H04N21/64792—Controlling the complexity of the content stream, e.g. by dropping packets
    • H—ELECTRICITY
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    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H—ELECTRICITY
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    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
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    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
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    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
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    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
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Definitions

  • the present invention relates to a method of transmitting/receiving a signal and an apparatus for transmitting/receiving a signal, and more particularly to a method of transmitting/receiving a signal and an apparatus for transmitting/receiving a signal, which are capable of increasing a data transfer rate.
  • a digital television (DTV) system can receive a digital broadcasting signal and provide a variety of supplementary services to users as well as a video signal and an audio signal.
  • DTV digital television
  • An object of the present invention is to provide a method of transmitting/receiving a signal and an apparatus for transmitting/receiving a signal, which are capable of increasing a data transfer rate and using the existing network for transmitting/receiving the signal.
  • the present invention provides an apparatus for transmitting a signal including a forward error correction (FEC) encoder configured to FEC-encode input data at a plurality of code rates and output the FEC-encoded data, a symbol mapper configured to convert the output data into data symbols according to a plurality of symbol mapping methods, a frame builder configured to insert a pilot symbol into a frame including the data symbols and a transmitter configured to transmit the signal having the frame into which the pilot symbol is inserted, and a method thereof.
  • FEC forward error correction
  • the FEC encoder may FEC-encode the input data with a high-code-rate FEC code and a low-code-rate FEC code.
  • the symbol mapper may include a bit parser configured to parse the interleaved data into a plurality of bit streams, a plurality of mapping units configured to map the plurality of parsed bit streams to symbols according to the plurality of symbol mapping methods and a symbol merger configured to merge the plurality of symbols mapped by the mapping units to a symbol stream and output the symbol stream.
  • the frame builder may arranges a low-rate symbol in a pilot carrier interval by the plurality of mapping methods of the symbol mapper, in the case where a pilot carrier is included in the frame.
  • the present invetion provides an apparatus for receiving a signal including a receiver configured to receive the signal, a synchronizer configured to acquire synchronization of the received signal, a demodulator configured to demodulate the signal, of which the synchronization is acquired, a frame parser configured to parse the demodulated signal frame, a symbol demapper configured to demap symbols included in the frame to bit data according to a plurality of symbol mapping methods and output the data and a forward error correction (FEC) decoder configured to FEC-decode the output data at a plurality of code rates, and a method thereof.
  • FEC forward error correction
  • the FEC decoder may FEC-decode the input data with a high-code-rate FEC code and a low-code-rate FEC code.
  • the symbol demapper may include a symbol parser configured to parse input symbol into a plurality of symbol streams and output the symbol streams, a demapping unit configured to demap the symbol streams parsed by the symbol parser to bit data streams according to the plurality of symbol mapping methods and a bit merger configured to merge the bit data streams output from the demapping unit to a bit stream and outputs the bit stream.
  • the apparatus may further include an equalizer configured to estimate and compensate for a channel using symbols modulated by a lower order modulation as a pilot carrier by the plurality of symbol mapping methods.
  • the channel may be estimated by a decision-directed channel estimation (DDCE) method.
  • the equalizer may estimate and compensate for a channel using symbols modulated by a lower order modulation as a pilot carrier by the plurality of symbol mapping methods.
  • FIG. 1 is a schematic block diagram showing an apparatus for transmitting a signal according to an embodiment of the present invention.
  • FIG. 2 is a schematic block diagram showing a forward error correction encoder according to the embodiment of the present invention.
  • FIG. 3 is a view showing an interleaver for interleaving input data according to the embodiment of the present invention.
  • FIG. 4 is a schematic block diagram showing a linear pre-coder according to the embodiment of the present invention.
  • FIGs. 5 to 7 are views showing code matrixes for dispersing input data according to the embodiment of the present invention.
  • FIG. 8 is a view showing a structure of a transfer frame according to the embodiment of the present invention. [22] FIG.
  • FIG. 9 is a schematic block diagram showing an apparatus for transmitting a signal with a plurality of transmission paths according to the embodiment of the present invention.
  • FIGs. 10 to 14 are views showing examples of 2x2 code matrixes for dispersing input symbols according to the embodiment of the present invention.
  • FIG. 15 is a view showing an example of the interleaver according to the embodiment of the present invention.
  • FIG. 16 is a view showing a detailed example of the interleaver of FIG. 15 according to the embodiment of the present invention.
  • FIG. 17 is a view showing an example of a multi-input/output encoding method according to the embodiment of the present invention.
  • FIG. 10 to 14 are views showing examples of 2x2 code matrixes for dispersing input symbols according to the embodiment of the present invention.
  • FIG. 15 is a view showing an example of the interleaver according to the embodiment of the present invention.
  • FIG. 16 is a view showing a detailed example of the interleaver of FIG. 15 according to the embodiment
  • FIG. 18 is a view showing a structure of a pilot symbol interval according to the embodiment of the present invention.
  • FIG. 19 is a view showing another structure of the pilot symbol interval according to the embodiment of the present invention.
  • FIG. 20 is a schematic block diagram showing an apparatus for receiving a signal according to an embodiment of the present invention.
  • FIG. 21 is a schematic block diagram showing an example of a linear pre-coding decoder according to the embodiment of the present invention.
  • FIG. 22 is a schematic block diagram showing another example of the linear pre- coding decoder according to the embodiment of the present invention.
  • FIGs. 23 to 25 are views showing examples of a 2x2 code matrix for restoring the dispersed symbols according to the embodiment of the present invention.
  • FIG. 26 is a schematic block diagram showing a forward error correction decoder according to the embodiment of the present invention.
  • FIG. 27 is a schematic block diagram showing an apparatus for receiving a signal with a plurality of reception paths according to the embodiment of the present invention.
  • FIG. 28 is a view showing an example of a multi-input/output decoding method according to the embodiment of the present invention.
  • FIG. 29 is a view showing a detailed example of FIG.
  • FIG. 30 is a schematic block diagram showing another example of the apparatus for transmitting the signal according to the embodiment of the present invention.
  • FIG. 31 is a schematic block diagram showing another example of the apparatus for receiving the signal according to the embodiment of the present invention.
  • FIG. 32 is a view showing another example of the apparatus for transmitting the signal.
  • FIG. 33 is a view showing an example of a symbol mapper of FIG. 32.
  • FIG. 34 is a view showing another example of the apparatus for receiving the signal.
  • FIG. 35 is a view showing an example of a symbol demapper of FIG. 34.
  • FIG. 36 is a view showing an experimental result of reception performance in the case where the signal transmitted according to the examples of FIGs. 32 and 34 is received.
  • FIG. 37 is a flowchart illustrating a method of transmitting a signal according to an embodiment of the present invention.
  • FIG. 38 is a flowchart illustrating a method of receiving a signal according to an embodiment of the present invention.
  • FIG. 1 is a schematic block diagram showing an apparatus for transmitting a signal according to an embodiment of the present invention.
  • the apparatus for transmitting the signal of FIG. 1 may be a broadcasting signal transmitting system for transmitting a broadcasting signal including video data and so on.
  • a signal transmitting system according to a digital video broadcasting (DVB) system will now be described. Accordingly, the following embodiments relate to the DVB system. If the present invention is applied to other systems, components may be arranged in order different from the order of components of the following embodiments.
  • FIG. 1 includes a forward error correction (FEC) encoder 100, a first interleaver 110, a symbol mapper 120, a linear pre-coder 130, a second interleaver 140, a multi- input/output encoder 150, a frame builder 160, a modulator 170 and a transmitter 180.
  • FEC forward error correction
  • the FEC encoder 100 encodes an input signal and outputs the encoded signal.
  • FEC encoder 100 makes it possible for a signal receiving system to detect an error which occurs in transmitted data, and correct the error.
  • the data encoded by the FEC encoder 100 is input to the first interleaver 110.
  • a detailed example of the FEC encoder 100 is shown in FIG. 2.
  • the first interleaver 110 shuffles the data output from the FEC encoder 100 to random positions so as to become robust against a burst error which occurs in the data when transmitting the data.
  • the first interleaver 110 can use a convolution interleaver or a block interleaver, which may be changed according to the transmitting system. The embodiment of the first interleaver 110 is shown in FIG. 3 in detail.
  • the data interleaved by the first interleaver 110 is input to the symbol mapper 120.
  • the symbol mapper 120 maps the transmitted signal to a symbol according to a scheme such as a QAM scheme or a QPSK scheme, in consideration of a transmission parameter signal and a pilot signal according to a transmission mode.
  • the linear pre-coder 130 disperses input symbol data into several pieces of output symbol data so as to decrease a probability that all information is lost due to fading when being subjected to frequency selective fading of a channel.
  • a detailed example of the linear pre-coder 130 is shown in FIGs. 4 to 7.
  • the second interleaver 140 interleaves the symbol data output from the linear pre- coder 130. That is, if the interleaving is performed by the second interleaver 140, an error which occurs when the symbol data is subjected to the same frequency selective fading at a specific position can be corrected.
  • the second interleaver 140 may use a convolution interleaver or a block interleaver.
  • the linear pre-coder 130 and the second interleaver 140 process data to be transmitted so as to become robust against the frequency selective fading of the channel and may be called a frequency selective fading coder.
  • the multi- input/output encoder 150 encodes the data interleaved by the second interleaver 140 such that the data is processed via a plurality of transmission paths.
  • the apparatus for transmitting/receiving the signal can process the signal according to the multi-input/output method.
  • the multi-input/output method includes the multi-input multi-output (MIMO) method, a single-input multi-output (SIMO) method and a multi-input single-output (MISO) method.
  • a spatial multiplexing method and a spatial diversity method can be used.
  • the spatial multiplexing method data having different information are simultaneously transmitted using multiple antennas of a transmitter and a receiver. Accordingly, the data can be more rapidly transmitted without further increasing the bandwidth of the system.
  • the spatial diversity method data having the same information is transmitted via multiple transmission antennas such that diversity effect can be obtained.
  • a space-time block code STBC
  • SFBC space-frequency block code
  • STTC space- time trellis code
  • a method of dividing a data stream by the number of transmission antennas and transmitting the data stream a full-diversity full-rate (FDFR) code, a linear dispersion code (LDC), a vertical-bell lab layered space-time (VBLAST) or a diagonal-BLAST (D-BLAST) may be used.
  • FDFR full-diversity full-rate
  • LDC linear dispersion code
  • VBLAST vertical-bell lab layered space-time
  • D-BLAST diagonal-BLAST
  • the frame builder 160 inserts the pre-coded signal into a pilot signal at a predetermined position of a frame and builds a frame defined in the transmitting/receiving system.
  • the frame builder 160 may place a data symbol interval and a pilot symbol interval, which is a preamble of the data symbol interval, in the frame. Accordingly, hereinafter the frame builder 160 may be called a pilot symbol inserter.
  • the frame builder 160 may place pilot carriers, of which positions are temporally shifted and dispersed, in a data carrier interval.
  • the frame builder may place continuation pilot carriers, of which positions are temporally fixed, in the data carrier interval.
  • the modulator 170 modulates the data by an orthogonal frequency division multiplex
  • OFDM OFDM
  • the modulator 170 inserts a guard interval into the modulated data.
  • the transmitter 180 converts the digital signal having the guard interval and the data interval, which is output from the modulator 170, into an analog signal and transmits the analog signal.
  • FIG. 2 is a schematic block diagram showing the FEC encoder shown in FIG. 1.
  • FEC encoder includes a Bose-chaudhuri-Hocquenghem (BCH) encoder 102 and a low density parity check (LDPC) encoder 104 as an outer encoder and an inner encoder, respectively.
  • BCH Bose-chaudhuri-Hocquenghem
  • LDPC low density parity check
  • a LDPC code is an error correction code which can reduce a probability that data information is lost.
  • the LDPC encoder 104 encodes the signal in a state in which the length of an encoding block is large such that the transmitted data is robust against a transmission error.
  • the density of the parity bit is decreased so as to dec rease the complexity of the encoder.
  • BCH encoder 102 is concatenated in front of the LDPC encoder 104 as the additional outer encoder. If an ignorable error floor occurs even when only the LDPC encoder 104 is used, the BCH encoder 102 may not be used. Alternatively, other encoders may be used as the outer encoder, instead of the BCH encoder.
  • parity check bits for the BCH encoding are added to the input data frame and parity check bits (LDPC parity check bits) for the LDPC encoding is added to the BCH parity check bits.
  • the length of the BCH parity check bits added to the encoded data frame may vary according to the length of a LDPC codeword and a LDPC code rate.
  • the data which is FEC-encoded by the BCH encoder 102 and the LDPC encoder 104 is output to the first interleaver 110.
  • FIG. 3 is a view showing the first (second) interleaver shown in FIG. 1. As the first
  • (second) interleaver of FIG. 3 for example, a block interleaver may be used.
  • the interleaver of FIG. 3 stores input data in a matrix-shaped memory space in a predetermined pattern and reads and outputs the data in a pattern different from the pattern used for storing the data.
  • the interleaver of FIG. 3 has an NrxNc memory space composed of Nr rows and Nc columns and the data input to the interleaver is filled from a position corresponding to a first row and a first column of the memory space.
  • the data is stored from the first row and the first column to an Nr row and the first column and, if the first column is filled up, is then stored from the first row to the th
  • Nr row of a next column (second column).
  • the data may be stored up to the Nr row of an Nc column (i.e. the data are stored column- wise).
  • the data is read and output from the first row and the first column to the first row and the Nc column. If all the data of the first row is read, the data is read and output from the first column of a next row (second row) in the column direction. In this sequence, the data may be read and output up to the Ncth column of the Nr row (i.e. the data are read out row-wise). At this time, the position of a most significant bit (MSB) of the data block is a left uppermost side and the position of a least significant bit (LSB) thereof is a right lowermost side.
  • MSB most significant bit
  • LSB least significant bit
  • the size of the memory block, the storage pattern and the read pattern of the in- terleaver are only exemplary and may be changed according to implementation embodiments.
  • the size of the memory block of the first interleaver may vary according to the size of the FEC-encoding block.
  • the sizes of the row Nr and the column Nc of the block, which decide the size of the block interleaved by the first interleaver may vary according to the length of the LDPC code block. If the length of the LDPC code block is increased, the length of the block (e.g., the length of the row of the block) may be increased.
  • FIG. 4 is a schematic block diagram showing the linear pre-coder of FIG. 1.
  • the linear pre-coder 130 may include a serial/parallel converter 132, an encoder 134 and a parallel/serial converter 136.
  • the serial/parallel converter 132 converts the input data into parallel data.
  • the encoder 134 disperses the values of the converted parallel data into several pieces of data via the operation of an encoding matrix.
  • An encoding matrix is designed by comparing an transmission symbol with an reception symbol such that a pairwise error probability (PEP) that the two symbols are different from each other is minimized. If the encoding matrix is designed such that the PEP is minimized, a diversity gain and a coding gain obtained via the linear pre-coding are maximized.
  • PEP pairwise error probability
  • FIG. 5 is a view showing an example of the encoding matrix used by the encoder
  • FIG. 6 shows an example of the encoding matrix for dispersing the input data into several pieces of output data, which is also called a vanderMonde matrix.
  • the input data may be arranged in parallel by the length of the number (L) of output data.
  • ⁇ of the matrix may be expressed by the following equation and may be defined by other methods. If the vanderMonde matrix is used as the encoding matrix, a matrix element may be determined according to Math Figure 1.
  • FIG. 6 shows another example of the encoding matrix.
  • FIG. 6 shows another example of the encoding matrix for dispersing the input data into several pieces of output data, which is also called a Hadamard matrix.
  • the matrix of FIG. 6 is a matrix having a general form, in which L is expanded by 2 .
  • L denotes the number of output symbols into which the input symbols will be dispersed.
  • the output symbols of the matrix of FIG. 6 can be obtained by a sum and a difference among L input symbols.
  • the input symbols may be dispersed into the L output symbols, respectively.
  • FIG. 7 shows another example of the encoding matrix for dispersing the input data.
  • FIG. 7 shows another example of the encoding matrix for dispersing the input data into several pieces of output data, which is also called a Golden code.
  • the Golden code is a 4x matrix having a special form. Alternatively, two different 2x2 matrixes may be alternately used.
  • C of FIG. 7 denotes a code matrix of the Golden code and xl, x2, x3 and x4 in the code matrix denote symbol data which can be input to the encoder 134 of FIG. 5 in parallel.
  • Constants in the code matrix may decide the characteristics of the code matri x, and the values of the rows and the columns computed by the constants of the code matrix and the input symbol data may be expressed by the output symbol data.
  • the output sequence of the symbol data may vary according to the implementation em- bodiments. Accordingly, in this case, the parallel/serial converter 136 of FIG. 4 may convert the parallel data into the serial data according to the position sequence of the data in a parallel data set output from the encoder 134 and output the serial data.
  • FIG. 8 is a view showing a structure of a transfer frame of the data channel-coded by the above-described embodiments of FIGs. 1 to 7.
  • the transfer frame formed according to the present embodiment may include a pilot symbol including pilot carrier information and a data symbol including data information.
  • a frame includes M (M is a natural number) intervals and is divided into M- 1 data symbol intervals and a pilot symbol interval which is used as a preamble.
  • M is a natural number
  • Each symbol interval includes carrier information by the number of OFDM subcarriers.
  • the pilot carrier information of the pilot symbol interval is composed of random data in order to decrease a peak- to- average power ratio (PAPR).
  • An autocorrelation value of the pilot carrier information has an impulse shape in a frequency domain. The correlation value between file carrier symbols may be close to 0.
  • the pilot symbol interval used as the preamble allows the receiver to quickly recognize the signal frame of FIG. 8 and may be used for correcting and synchronizing a frequency offset. Since the pilot symbol interval represents the start of the signal frame, a system transmission parameter for allowing the received signal to be quickly synchronized may be set.
  • the frame builder builds the data symbol intervals and inserts the pilot symbol interval in front of the data symbol intervals, thereby building a transfer frame.
  • the pilot carrier information may not be included in the data symbol intervals. Accordingly, it is possible to increase a data capacity.
  • the DVB for example, since a percentage of pilot carriers in all the valid carriers is about 10%, the increasing rate of the data capacity is expressed by Math Figure 3.
  • Math Figure 3 denotes the increasing rate and M denotes the number of intervals included in a frame.
  • FIG. 9 is a block diagram showing a signal transmitting apparatus, which processes signals using a plurality of transmission paths, according to another embodiment of the present invention.
  • the number of transmission paths is two.
  • FIG. 9 includes a forward error correction (FEC) encoder 700, a first interleaver 710, a symbol mapper 720, a linear pre-coder 730, a second interleaver 740, a multi-input/output encoder 750, a first frame builder 760, a second frame builder 765, a first modulator 770, a second modulator 775, a first transmitter 780, and a second transmitter 785.
  • FEC forward error correction
  • the FEC encoder 700, the first interleaver 710, the symbol mapper 720, the linear pre-coder 730, the second interleaver 740, and the multi-input/output encoder 750 perform the same functions as those of FIG. 1.
  • the FEC encoder 700 includes a BCH encoder and a LDPC encoder.
  • the FEC encoder 700 FEC-encodes input data and outputs the encoded data.
  • the output data is interleaved by the first interleaver 710 such that the sequence of the data stream is changed.
  • a convolution interleaver or a block interleaver may be used as the first interleaver 710.
  • the symbol mapper 720 maps the transmitted signal to a symbol according to the
  • QAM or QPSK scheme in consideration of a transmission parameter signal and a pilot signal according to a transmission mode. For example, if the signal is mapped to the symbol to generate 128QAM, 7-bit data may be included in a symbol and, if the signal is mapped to the symbol to generate 256QAM, 8-bit data may be included in a symbol.
  • the linear pre-coder 730 includes a serial/parallel converter, an encoder and a parallel/serial converter. A code matrix encoded by the linear pre-coder 730 is shown in FIGs. 10 to 14.
  • the second interleaver 740 interleaves the symbol data output from the linear pre- coder 730.
  • a convolution interleaver or a block interleaver may be used as the second interlever 740.
  • the second interleaver 740 interleaves the symbol data such that the symbol data which is dispersed into the data output from the linear pre-coder 730 is not subjected to the same frequency selective fading.
  • the interleaving method may vary according to the implementation embodiments.
  • the length of the interleaver may vary according to the implementation embodiments. If the length of the interleaver is smaller than or equal to that of the OFDM symbol, the interleaving is performed only in one OFDM symbol and, if the length of the interleaver is larger than that of the OFDM symbol, the interleaving may be performed over several symbols.
  • FIGs. 15 and 16 show the interleaving method in detail.
  • the interleaved data is output to the multi-input/output encoder 750 and the multi- input/output encoder 750 encodes the input symbol data and outputs the encoded data such that the data is transmitted via a plurality of transmission antennas. For example, if two transmission paths exist, the multi-input/output encoder 750 outputs the pre- coded data to the first frame builder 760 or the second frame builder 765.
  • the data having the same information is output to the first frame builder 760 and the second frame builder 765. If the encoding is performed by the spatial multiplexing method, different data is output to the first frame builder
  • the first frame builder 760 and the second frame builder 765 build frames, into which the pilot signals are inserted, such that the received signals are modulated by the
  • the frame includes one pilot symbol interval and M-I (M is a natural number) data symbol intervals. If the transmitting system of FIG. 9 performs the multi- input/output encoding using the plurality of antennas, the structure of the pilot symbol may be decided such that the receiver distinguishes between the transmission paths. [108] The example of the multi-input/output encoder 750 of FIG. 9 is shown in FIGs. 18 and 19. [109] The first modulator 770 and the second modulator 775 modulate the data output from the first frame builder 760 and the second frame builder 865 such that the modulated data is transmitted in the OFDM subcarriers, respectively.
  • FIGs. 10 to 14 are views showing an example of a 22 code matrix for dispersing input symbols as an example of the encoding matrix of the linear pre-coder.
  • the code matrixes of FIGs. 10 to 14 disperse two pieces of data input to the encoding unit of the linear pre-decoder 730 to two pieces of output data.
  • the matrix of FIG. 10 is an example of the vanderMonde matrix described with reference to FIG. 5, in which L is 2. In the matrix of FIG. 10, first input data and second input data, of which phase is rotated by 45 degrees (
  • first input data and second input data of which phase is rotated by 225 degrees
  • the output data is divided by so as to be scaled.
  • the code matrix of FIG. 11 is an example of the Hadamard matrix. [114] In the matrix of FIG. 11, first input data and second input data of the two pieces of input data are added and first output data is output. Then, second input data are subtracted from first input data and second output data is output. The output data is divided by so as to be scaled. [115] FIG. 12 shows another example of the code matrix for dispersing the input symbols.
  • the matrix of FIG. 12 is an example of a code matrix different from the matrix described with reference to FIGs. 5, 6 and 7. [116] In the matrix of FIG. 12, first input data, of which phase is rotated by 45 degrees (
  • FIG. 13 is a view showing another example of the code matrix for dispersing the input symbols.
  • the matrix of FIG. 13 is different from the matrixes shown in FIGs. 5,
  • the output data is divided by
  • FIG. 14 shows another example of the code matrix for dispersing the input symbols.
  • the matrix of FIG. 14 is an example of a code matrix different from the matrix described with reference to FIGs. 5, 6 and 7. * of FIG. 14 denotes a complex conjugate of the input data.
  • FIG. 15 is a view showing an example of an interleaving method of the interleaver.
  • the interleaving method of FIG. 15 is an example of the interleaver of the OFDM system having a symbol length N, which can be used in the second interleaver 740 of the transmitting apparatus shown in FIG. 9.
  • N denotes the length of the interleaver and i has a value corresponding to the length of the interleaver, that is, an integer from 0 to N-I.
  • n denotes the number of valid transmission carriers in a transmitting system.
  • FI(i) denotes a permutation obtained by a modulo-N operation
  • dn has a FI(i) value which is located in a valid transmission carrier area excluding a value N/2 in sequence
  • k denotes an index value of an actual transmission carrier.
  • N/2 is subtracted from dn such that the center of the transmission bandwidth becomes DC.
  • P denotes a permutation constant which may vary according to implementation embodiments.
  • FIG. 16 is a view showing a variable which varies according to the interleaving method of FIG. 15.
  • the length of the OFDM symbol and the length N of the interleaver are set to 2048 and the number of valid transmission carriers are set to 1536 (1792-256).
  • i is an integer from 0 to 2047 and n is an integer from 0 to 1535.
  • dn denotes a permutation obtained by a modulo-2048 operation
  • dn has a (i) value with respect to a value 256 ⁇ FI(i) ⁇ 1792 excluding a value 1024(N/2) in sequence
  • k denotes a value obtained by subtracting 1024 from dn.
  • P has a value of 13.
  • data corresponding to the sequence i of the input data may be changed to the sequence k of the interleaved data with respect to the length N of the interleaver.
  • FIG. 17 is a view showing an example of the encoding method of the multi- input/output encoder.
  • the embodiment of FIG. 17 is the STBC which is one of the multi-input/output encoding methods and may be used in the transmitting apparatus shown in FIG. 9.
  • T denotes a symbol transmission period
  • s denotes an input symbol to be transmitted
  • y denotes an output symbol
  • * denotes a complex conjugate
  • a first antenna (Tx #1) and a second antenna (Tx #2) denote a first transmission antenna and a second transmission antenna 2, respectively.
  • the first antenna Tx #1 transmits sO and the second antenna Tx #2 transmits si.
  • the first antenna Tx #1 transmits - si* and the second antenna Tx #2 transmits sO*.
  • the transmission antennas transmit data having the same information of sO and si in the transmission period. Accordingly, the receiver can obtain spatial diversity effect using the signals output from the multi- input/output encoder according to the method shown in FIG. 17.
  • the signals transmitted by the first antenna and the second antenna shown in FIG. 17 are examples of the multi-input/output encoded signals.
  • the signals transmitted by the first antenna and the second antenna may be transmitted by a multi-input single-output method.
  • FIG. 17 shows a simplest example using two antennas. The signals may be transmitted according to the method shown in FIG. 17 using more antennas.
  • the consecutive first and second symbols are multi- input and a minus of a complex conjugate of the second symbol and a complex conjugate of the first symbol are simultaneously output.
  • the multi-input symbols may be encoded according to an Alamouti algorithm and the encoded symbols may be output.
  • the multi- input/output encoder may transmit the signals which are interleaved by the second interleaver in the frequency domain, by the multi-input single-output method.
  • the multi-input/output (including the multi-input single-output) shown in FIG. 17 may be not applied to the pilot symbol interval shown in FIGs. 18 and 19 and may be applied to only the data symbol interval.
  • FIG. 18 is a view showing a structure of the pilot carriers in the pilot symbol intervals built by the first and second frame builders of FIG. 9.
  • the pilot symbol intervals built by the frame builders of FIG. 9 may be output as shown in FIG. 8.
  • FIG. 18 shows the respective pilot symbols built by the first and second frame builders as the signals output from the first and second antennas.
  • an even-numbered pilot carrier and an odd-numbered pilot carrier are respectively interleaved as shown in FIG. 18 and the interleaved carriers may be output to the first and second antennas #1 and #2.
  • pilot symbol interval built by the first frame builder For example, only the even-numbered pilot carrier information of the generated pilot carriers is included in the pilot symbol interval built by the first frame builder and is transmitted via the first antenna #1. Only the odd- numbered pilot carrier information of the generated pilot carriers is included in the pilot symbol interval built by the second frame builder and is transmitted via the second antenna. Accordingly, the receiver can distinguish between the transmission paths using the carrier indexes of the pilot symbol intervals received via the two signal paths.
  • the structure of the pilot symbol interval of FIG. 18 may be used when the multi-input/output encoding is performed so as to have the two transmission paths as shown in FIG. 11.
  • a channel corresponding to a subcarrier of a half of a frame may be estimated from a symbol. Accordingly, high channel estimation performance can be obtained with respect to a transmission channel having a short coherence time.
  • FIG. 19 is a view showing another structure of the pilot carriers in the pilot symbol intervals built by the first and second frame builders of FIG. 9. Even in the example of FIG. 19, different pilot carriers are transmitted to the pilot symbol intervals with respect to the paths according to the multi-input/output encoding method.
  • Hadamard conversion is performed in the unit of a symbol interval in order to distinguish between the two transmission paths. For example, pilot carriers obtained by adding the two pieces of pilot carrier information for the transmission paths are transmitted to the even-numbered symbol interval and a difference between the two pieces of pilot carrier information is transmitted to the odd-numbered symbol interval.
  • antenna #0 and #1 transmit the same pilot carriers, respectively and in odd- numbered intervals, antenna #0 and #1 transmit the pilot carriers of which phases are opposite each other.
  • the receiver can use sum and difference of the pilot carriers respectively transmitted through two paths.
  • a channel corresponding to all subcarriers can be estimated and the estimation length of delay spread of the channel which can be processed by each transmission path can be extended by a symbol length.
  • FIG. 19 The example of FIG. 19 is shown for facilitating the distinguishment between the two pieces of pilot carrier information and shows both the two pieces of pilot carrier information in the frequency domain.
  • impulses of the two pieces of pilot carrier information are located at the same frequency point.
  • FIGs. 18 and 19 are examples of having two transmission paths. If the number of transmission paths is larger than 2, the pilot carrier information may be divided so as to be distinguished by the number of transmission paths similar to FIG. 18 or may be subjected to Hadamard conversion in the unit of a symbol interval and the converted information may be transmitted similar to FIG. 19.
  • FIG. 20 is a block diagram showing an apparatus for receiving a signal according to another embodiment of the present invention.
  • the apparatus for transmitting/receiving the signal may be a system for transmitting/receiving a broadcasting signal according to a DVB system.
  • the embodiment of FIG. 20 includes a receiver 1300, a synchronizer 1310, a demodulator 1320, a frame parser 1330, a multi-input/output decoder 1340, a first dein- terleaver 1350, a linear pre-coding decoder 1360, a symbol demapper 1370, a second deinterleaver 1380, and a forward error correction (FEC) decoder 1390.
  • FEC forward error correction
  • the receiver 1300 down-converts the frequency band of a received RF signal, converts the signal into a digital signal, and outputs the digital signal.
  • the synchronizer 1310 acquires synchronization of the received signal output from the receiver 1300 in a frequency domain and a time domain and outputs the synchronization.
  • the synchronizer 1310 may use an offset result of the data output from the demodulator 1320 in the frequency domain, for acquiring the synchronization of the signal in the frequency domain.
  • the demodulator 1320 demodulates the received data output from the synchronizer 1310 and removes the guard interval.
  • the demodulator 1320 may convert the reception data into the frequency domain and obtain data values dispersed into the subcarriers.
  • the frame parser 1330 may output symbol data of the data symbol interval excluding the pilot symbol according the frame structure of the signal demodulated by the demodulator 1320.
  • the frame parser 1330 may parse the frame using at least one of a scatter pilot carrier of which position is temporally shifted in the data carrier interval and a continuation pilot carrier of which position is temporally fixed in the data carrier interval.
  • the multi- input/output decoder 1340 receives the data output from the frame parser 1330, decodes the data, and outputs a data stream.
  • the multi- input/output decoder 1340 decodes the data stream received via the plurality of transmission antennas according to a method corresponding to the transmitting method of the multi- input/output encoder shown in FIG. 1 and outputs a data stream.
  • the first deinterleaver 1350 deinterleaves the data stream output from the multi- input/output decoder 1340 and decodes the data into the sequence of the data before interleaving.
  • the first deinterleaver 1350 deinterleaves the data stream according to a method corresponding to the interleaving method of the second interleaver shown in FIG. 1 and restores the sequence of the data stream.
  • the linear pre-coding decoder 1360 performs an inverse process of the process of dispersing the data in the apparatus for transmitting the signal. Accordingly, the data dispersed according to the linear pre-coding may be restored to the data before dispersing.
  • the embodiment of the linear pre-coding decoder 1360 is shown in FIGs. 21 to 22.
  • the symbol demapper 1370 may restore the coded symbol data output from the linear pre-coding decoder 1360 into a bit stream.
  • the symbol demapper 1370 performs the inverse process of the symbol mapping process using the symbol mapper.
  • the second deinterleaver 1380 deinterleaves the data stream output from the symbol mapper 1370 and restores the data into the sequence of the data before interleaving.
  • the second deinterleaver 1380 deinterleaves the data according to a method corresponding to the interleaving method of the first interleaver 110 shown in FIG. 1 and restores the sequence of the data stream.
  • the FEC decoder 1390 FEC-decodes the data, in which the sequence of the data stream is restored, detects an error which occurs in the received data, and corrects the error.
  • the example of the FEC decoder 1390 is shown in FIG. 26.
  • FIG. 21 is a schematic block diagram showing an example of the linear pre-coding decoder of FIG. 11.
  • the linear pre-coding decoder 1360 includes a serial/parallel converter 1362, a first decoder 1364 and a parallel/serial converter 1366.
  • the serial/parallel converter 1362 converts the input data into parallel data.
  • the first decoder 1364 may restore the data, which is linearly pre-coded and is dispersed into the parallel data, as the original data via a decoding matrix.
  • the decoding matrix for performing decoding becomes an inverse matrix of the encoding matrix of the apparatus for transmitting the signal. For example, when the apparatus for transmitting the signal performs the encoding operation using the vanderMonde matrix, the Hadamard matrix and the Golden code shown in FIGs. 5, 6 and 7, the first decoder 1364 restores the dispersed data as the original data using the inverse matrixes of the matrixes.
  • the parallel/serial converter 1366 converts the parallel data received by the first decoder 1364 into the serial data and outputs the serial data.
  • FIG. 22 is a schematic block diagram showing another example of the linear pre- coding decoder.
  • the linear pre-coding decoder 1360 includes a serial/parallel converter 1361, a second decoder 1363 and a parallel/serial converter 1365.
  • the serial/parallel converter 1361 converts the input data into parallel data
  • the parallel/serial converter 1365 converts the parallel data received from the second decoder 1363 into serial data and outputs the serial data.
  • the second decoder 1363 may restore the original data, which is linearly pre-coded and is dispersed into the parallel data output from the serial/parallel converter 1361, using maximum likelihood (ML) decoding.
  • ML maximum likelihood
  • the second decoder 1363 is the ML decoder for decoding the data according to the transmitting method of the transmitter.
  • the second decoder 1363 ML-decodes the received symbol data according to the transmitting method and restores the data dispersed in the parallel data to the original data. That is, the ML decoder ML-decodes the received symbol data according to the encoding method of the transmitter.
  • FIGs. 23 to 25 are views showing examples of a 22 code matrix for restoring the dispersed symbols.
  • the code matrixes of FIGs. 23 to 25 show inverse matrixes corresponding to the 22 encoding matrixes of FIGs. 12 to 14. According to FIGs. 23 to 25, the code matrixes restore data which is dispersed into two pieces of data input to the decoding unit of the linear pre-coding decoder 1360 and output the restored data.
  • the 2x2 code matrix of FIG. 23 is a decoding matrix corresponding to the encoding matrix of FIG. 12.
  • FIG. 24 shows another example of the 2x2 code matrix.
  • the matrix of FIG. 24 is a decoding matrix corresponding to the encoding matrix of FIG. 13.
  • first input data which is multiplied by 0.5 and second input data are added and first output data is output.
  • second input data which is multiplied by 0.5 is subtracted from first input data and second output data is output.
  • the output data is divided by
  • FIG. 25 shows another example of the 22 code matrix.
  • the matrix of FIG. 25 is a decoding matrix corresponding to the encoding matrix of FIG. 14. * of FIG. 25 denotes a complex conjugate of the input data.
  • FIG. 25 shows another example of the 22 code matrix.
  • the matrix of FIG. 25 is a decoding matrix corresponding to the encoding matrix of FIG. 14. * of FIG. 25 denotes a complex conjugate of the input data.
  • FIG. 26 is a schematic block diagram showing the FEC decoder.
  • the FEC decoder 1390 corresponds to the FEC encoder 100 of FIG. 1.
  • a LDPC decoder 1392 and a BCH decoder 1394 are included, respectively.
  • the LDPC decoder 1392 detects a transmission error which occurs in a channel and corrects the error, and the BCH decoder 1394 corrects the remaining error of the data decoded by the LDPC decoder 1392 and removes an error floor.
  • FIG. 27 is a block diagram showing a signal receiving apparatus according to another embodiment of the signal receiving apparatus.
  • the number of reception paths is two will be described.
  • the embodiment of FIG. 27 includes a first receiver 1700, a second receiver 1705, a first synchronizer 1710, a second synchronizer 1715, a first demodulator 1720, a second demodulator 1725, a first frame parser 1730, a second frame parser 1735, a multi-input/output decoder 1740, a third deinterleaver 1750, a linear pre-coding decoder 1760, a symbol demapper 1770, a fourth deinterleaver 1780 and a FEC decoder 1790.
  • the first receiver 1700 and the second receiver 1705 receive RF signals, down- convert frequency bands, convert the signals into digital signals, and output the digital signals, respectively.
  • the first synchronizer 1710 and the second synchronizer 1715 acquire synchronizations of the received signals output from the first receiver 1700 and the second receiver 1705 in the frequency domain and the time domain and output the synchronizations, respectively.
  • the first synchronizer 1710 and the second synchronizer 1715 may use offset results of the data output from the first demodulator 1720 and the second demodulator 1725 in the frequency domain, for acquiring the synchronizations of the signal in the frequency domain, respectively.
  • the first demodulator 1720 demodulates the received data output from the first synchronizer 1710.
  • the first demodulator 1720 converts the received data into the frequency domain and decodes the data dispersed in the subcarriers to the data allocated to the subcarriers.
  • the second demodulator 1725 demodulates the received data output from the second synchronizer 1715.
  • the first frame parser 1730 and the second frame parser 1735 distinguish between the reception paths according to the frame structures of the signals demodulated by the first demodulator 1720 and the second demodulator 1725 and output symbol data of the data symbol interval excluding the pilot symbol, respectively.
  • the multi- input/output decoder 1740 receives the data output from the first frame parser 1730 and the second frame parser 1735, decodes the data, and outputs a data stream.
  • the signal processing of the linear pre-coding decoder 1760, the symbol demapper 1770, the fourth deinterleaver 1780 and the FEC decoder 1790 is equal to that of FIG. 20.
  • FIG. 28 is a view showing an example of a decoding method of the multi- input/output decoder. That is, FIG. 28 shows a decoding example of the receiver when the transmitter multi-input/output encodes data by the STBC method and transmits the encoded data.
  • the transmitter may use two transmission antennas. This is only exemplary and another multi-input/output method may be applied.
  • r(k), h(k), s(k) and n(k) represent a symbol received by the receiver, a channel response, a symbol value transmitted by the transmitter, and channel noise, respectively.
  • Subscripts s, i, 0 and 1 represent a s' transmission symbol, an i reception antenna, 0 transmission antenna and 1 st transmission antenna, respectively.
  • * represents a complex conjugate.
  • h (k) represents a response of a channel experienced by the transmitted symbol when a s symbol transmitted via the first transmission antenna is received by the i reception antenna.
  • R (k) represents a s+l,i s+1 reception symbol received by the i reception antenna.
  • r (k) which is a s reception symbol received by the ith reception antenna becomes a value obtained by adding the sth symbol value transmitted from the 0 transmission antenna to the i reception antenna via the channel, the s symbol value transmitted from the 1 st transmission antenna to the i reception antenna via the channel and a sum n (k) of the channel noises of the channels.
  • r (k) which is the s+1 reception symbol received by the ith reception antenna becomes a value obtained by adding the s+l'h symbol value h transmitted from the 0' transmission antenna to the i th reception antenna via the channel, the s+1 symbol value h s+1, l,i transmitted from the 1 st transmission antenna to the i reception antenna via the channel and a sum n s+1 (k) of the channel noises of the channels.
  • FIG. 29 is a view showing a detailed example of the reception symbol FIG. 28.
  • FIG. 29 shows a decoding example when the transmitter multi- input/output encodes data by the STBC method and transmits the encoded data, that is, shows an equation which can obtain the received symbol when the data is transmitted using two transmission antennas and the data transmitted via the two transmission data is received using one antenna.
  • the transmitter transmits a signal using two transmission antennas and the receiver receives the signal using one transmission antenna, the number of transmission channels may be two.
  • hO and sO respectively represent a transmission channel response from the ⁇ ' transmission antenna to the reception antenna and a symbol transmitted from the Oth transmission antenna
  • hi and si respectively represent a transmission channel response from the 1st transmission antenna to the reception antenna and a symbol transmitted from the 1 st transmission antenna.
  • "*" represents a complex conjugate and sO' and si' of the following equation represent restored symbols.
  • r and r respectively represent a symbol by the reception antenna at a time t and a symbol received by the reception antenna at a time t+T after a transmission period T is elapsed, and n and n represent values of sums of channel noises of the transmission paths at reception times.
  • the signals r and r received by the reception antenna may be represented by values obtained by adding the signals transmitted by the transmission antennas and values distorted by the transmission channels.
  • the restored symbols s ⁇ ' and si' are calculated using the received signals r and r and the channel response values h and h .
  • FIG. 30 is a schematic block diagram showing another example of the apparatus for transmitting the signal.
  • FIG. 31 shows a signal receiving apparatus which receives the signal transmitted from the signal transmitting apparatus of FIG. 30.
  • FIGs. 30 and 31 show examples of applying a single-input single-output (SISO) method to the system.
  • SISO single-input single-output
  • the signal transmitting apparatus of FIG. 30 includes a FEC error correction encoder 2000, a first interleaver 2010, a symbol mapper 2020, a linear pre-coder 2030, a second interleaver 2040, a frame builder 2050, a modulator 2060 and a transmitter 2070.
  • the description of this embodiment may refer to the embodiments described in FIGs. 1 and 20. That is, in the embodiment of FIG. 30, the signal processing similar to that of the embodiments of FIGs. 1 and 20 is performed. However, the signal transmitting apparatus of FIG. 30 processes the signal by the SISO method without including the multi-input/output encoder.
  • the symbol data which is subjected to the linear pre-coding and interleaving so as to become robust against the frequency selective fading of the channel is input to the frame builder 2050 and the frame builder 2050 builds a data interval no including a pilot carrier and a pilot symbol interval including the pilot carrier as shown in FIG. 8 on the basis of the input symbol data and outputs the built data interval and the pilot symbol interval.
  • the SISO method it is unnecessary to distinguish the transmission paths according to the multi-input/output of FIGs. 18 and 19.
  • the signal receiving apparatus of FIG. 31 includes a receiver 2100, a synchronizer
  • the embodiment of the signal receiving apparatus may refer to the embodiments described in FIGs. 20 and 27. However, in the embodiment of FIG. 31, since the signal transmitting apparatus of FIG. 31 processes the signal by the SISO method, the multi-input/output decoder is not included.
  • the symbol data parsed by the frame parser 2130 is output to the first deinterleaver 2140 such that the inverse process of the data processing of the transmitting apparatus so as to become robust against the frequency selective fading of the channel is performed.
  • FIG. 32 is a view showing another embodiment of the apparatus for receiving the signal. The embodiment of the apparatus for receiving the signal will be described with reference to FIG. 32.
  • the embodiment of FIG. 32 includes a forward error correction (FEC) encoder 3100, a first interleaver 3110, a symbol mapper 3120, a linear pre-coder 3130, a second in- terleaver 3140, a frame builder 3160, a modulator 3170, and a transmitter 3180.
  • FEC forward error correction
  • the FEC encoder 3100 FEC-encodes input data and outputs the FEC-encoded data.
  • the FEC encoder 3100 may have a structure in which an outer encoder and an inner encoder are concatenated. The example of the FEC encoder 3100 is shown in FIG. 2.
  • the FEC encoder 3100 can FEC-encodes the input data at two or more code rates.
  • the method of encoding the input data at two or more code rates by the FEC encoder 3100 is called a hybrid coding method.
  • the code rate indicates a ratio of the size of data having information to the size of encoded data.
  • the input data may be divided into sections and the sections may be FEC-encoded at a low code rate and a high code rate.
  • the FEC encoder 3100 can obtain a SNR gain with respect to data corresponding to a relatively low code rate and obtain a capacity gain with respect to data corresponding to a high code rate using the hybrid coding method.
  • the FEC-encoder 3100 may encode the input data at two or more code rates (e.g., 2/3 code rate and 1/2 code rate) with respect to one FEC encoding method (e.g., LDPC).
  • the first interleaver 3110 mixes the FEC-encoded data so as to be robust against a burst error generated in the transmitted data.
  • the example of the first interleaver 3110 is shown in FIG. 3.
  • the first interleaver 3110 may not be included in the case where the FEC encoder 3100 encodes the input data by the hybrid coding method.
  • the symbol mapper 3120 may map the data interleaved by the first interleaver 3110 to symbols.
  • the symbol mapper 3120 maps the symbols to subcarriers to be modulated using a plurality of M-ary modulation methods.
  • mapping of the symbols by the symbol mapper 3120 according to the plurality of modulation methods is called a hybrid modulation method.
  • the hybrid modulation method may use at least two of a quadrature amplitude modulation (QAM), a phase shift keying (PSK), an amplitude phase shift keying (APSK) and a pulse amplitude modulation (PAM).
  • QAM quadrature amplitude modulation
  • PSK phase shift keying
  • APSK amplitude phase shift keying
  • PAM pulse amplitude modulation
  • the hybrid modulation method includes a method of mixing a higher order modulation or a lower order modulation (e.g., 256-QAM and 64-QAM) according to the size of information which can be allocated to the symbols and converting bit data into symbols although the modulation methods are identical.
  • a higher order modulation or a lower order modulation e.g., 256-QAM and 64-QAM
  • the detailed example of the symbol mapper 3120 is shown in FIG. 33.
  • the data transfer rate may vary according to the modulation methods and a signal-to-noise ratio (SNR) may vary according to the modulation methods. Accordingly, if one modulation method is used, the reception performance such as the SNR of the transmitting/ receiving system may be decided by the modulation method. If the symbol is mapped according to the hybrid modulation method as shown in the example of FIG. 32, a flexible system capable of adjusting the transfer rate and the SNR can be manufactured. Accordingly, system parameters associated with the transmission/reception performance can be more freely decided. For example, in consideration of a minimum SNR required by the system, the symbols may be mapped according to a first modulation method.
  • Symbols mapped according to a second modulation method may be transmitted by subcarriers other than the subcarriers for transmitting the symbols according to the first modulation method.
  • the FEC-encoding process is not further performed, it is possible to obtain a SNR gain. That is, if the hybrid modulation method is used, a SNR gain can be obtained from symbols mapped to a small-size constellation and a capacity gain can be obtained from symbols using a large-sized constellation. Accordingly, if a mixing ratio is adjusted, it is possible to adjust the minimum SNR and the capacity increment.
  • the linear pre-coder 3130 may disperse the mapped symbol data into several pieces of output symbol data.
  • the detailed example of the linear pre-coder 3130 is shown in FIGs. 4 to 7.
  • the second interleaver 3140 interleaves the pre-coded symbol data in the frequency domain again.
  • a convolution interleaver or a block interleaver may be used as the second interleaver 3140.
  • the frame builder 3160 inserts the pre-coded signal at a predetermined position of a frame as a pilot signal and builds a frame defined in a transmitting/receiving system.
  • the frame built by the frame builder 3160 may include a data symbol interval and a preamble interval including the pilot signal.
  • the frame builder may arrange dispersed pilot carriers, of which the locations are temporally shifted, in the data carrier interval.
  • the frame builder may arrange consecutive pilot carriers, of which the locations are temporally fixed, in the data carrier interval.
  • the modulator 3170 modulates the data output from the frame builder 3160 by an orthogonal frequency division multiplex (OFDM) method and inserts a guard interval between the modulated symbols.
  • OFDM orthogonal frequency division multiplex
  • the transmitter 3180 converts the digital signal including the guard interval and the data interval, which is output from the modulator 3170, into an analog signal and transmits the analog signal.
  • the hybrid coding method of the FEC encoder 3100 and the hybrid modulating method of the symbol mapper 3120 may be simultaneously applied.
  • the FEC encoder 3100 encodes the input data at the low code rate and the symbol mapper 3120 maps the symbols by the lower order modulation (the input data is mapped to the symbols with respect to a relatively small-sized constellation)
  • the SNR gain can be maximized.
  • the FEC encoder 3100 encodes the input data at the high code rate and the symbol mapper 3120 maps the symbols by the higher order modulation (the input data is mapped to the symbols with respect to a relatively large-sized constellation)
  • the capacity gain of the system can be maximized.
  • the transmitted data is modulated by the hybrid modulation method according to the 256QAM and 64QAM
  • the 256QAM becomes the higher order modulation
  • the 64QAM becomes the lower order modulation.
  • the symbol mapper 3120 modulates the input data by the hybrid modulation method
  • the lower order modulation since the lower order modulation has a minimum SNR which is relatively smaller than that of the higher order modulation, the symbols of the lower order modulation can be used like the pilot symbol in the relationship with the receiving apparatus and thus the capacity can be increased. Accordingly, the frame builder 250 may not generate and arrange a separate pilot symbol.
  • the frame builder 250 may not generate and arrange a separate pilot symbol.
  • the capacity of the information transmitted/ received by the transmitting/receiving system can be increased. In this case, the operation of the receiving apparatus is shown in FIG. 34.
  • the symbol mapper 3120 may mix the hybrid modulation method for mapping the symbols. In this case, if the symbol stream mapped by the symbol mapper 3120 is arranged at the position where the pilot symbol will be arranged by the frame builder 250, the transmission/reception capacity of the system can be further increased.
  • FIG. 33 is a view showing an example of the symbol mapper of FIG. 32.
  • the embodiment of the symbol mapper will be described with reference to FIG. 33.
  • the symbol mapper 3120 includes a bit parser 3121, a mapper 3123 for mapping symbols according to a plurality of M-ary methods, and a symbol merger 3125.
  • the bit parser 3121 parses an input bit stream into a plurality of bit streams.
  • the mapper 3123 may include a plurality of symbol mapping units which respectively maps the plurality of bit streams to symbols by different methods. For example, a first symbol mapping unit maps the symbols by the 256-QAM method and the second symbol mapping unit maps the symbols by the 64-QAM method.
  • the mapper 3123 may map the parsed bit streams to the symbols by symbol mapping methods other than the above-described methods.
  • the symbol merger 3125 may receive the mapped symbols from the plurality of symbol mapping units, merge the received symbols and output a symbol stream.
  • FIG. 34 is a view showing another example of the apparatus for receiving the signal.
  • the embodiment of the apparatus for receiving the signal will be described with reference to FIG. 34.
  • the example of the apparatus for receiving the signal of FIG. 34 can receive and process the signal transmitted by the embodiment of the apparatus for transmitting the signal of FIG. 32.
  • the embodiment of FIG. 34 includes a receiver 3300, a synchronizer 3310, a demodulator 3320, a frame parser 3330, a first deinterleaver 3350, a linear pre-coding decoder 3360, a symbol demapper 3370, a second deinterleaver 3380 and a FEC decoder 3390.
  • the receiver 3300 down-converts the frequency band of the received RF signal, converts the signal into a digital signal, and outputs the digital signal.
  • the synchronizer 3310 acquires synchronization of the received signal output from the receiver 3300 in a frequency domain and a time domain and outputs the synchronization.
  • the demodulator 3320 demodulates the received data output from the synchronizer 3310 in the frequency domain and removes the guard interval.
  • the demodulator 3320 may obtain data values dispersed in the subcarriers.
  • the frame parser 3330 may output symbol data of the data symbol interval excluding the pilot symbol according to the frame structure of the signal demodulated by the demodulator 3320.
  • the frame parser 3330 may differently parse a pilot symbol included in a frame, a data symbol used as a pilot symbol and a general data symbol, even in the case where the data symbol modulated by the lower order modulation is used as the pilot symbol according to the hybrid method.
  • the first deinterleaver 3350 deinterleaves the data stream output from the frame parser 3330.
  • the linear pre-coding decoder 3360 may restore the data dispersed in the apparatus for transmitting the signal.
  • the embodiment of the linear pre-coding decoder 3360 is shown in FIGs. 21 to 22.
  • the symbol demapper 3370 may restore the symbols modulated by the hybrid method to the bit data.
  • the example of the symbol demapper 3370 is shown in FIG. 35.
  • the second deinterleaver 3380 may deinterleave the data stream output from the symbol demapper 3370.
  • the embodiment of the apparatus for receiving the signal may not include the second deinterleaver 3380 in the case where the data is transmitted by the hybrid modulation method and the hybrid coding method.
  • the FEC decoder 3390 may FEC-decode the data interleaved by the second deinterleaver 3380.
  • the FEC decoder 3390 may decode the data according to the hybrid coding method. For example, the FEC decoder 3390 may decode the input data, which is encoded at different code rates according to the data stream, at the corresponding code rates.
  • the embodiment of the apparatus for receiving the signal may include an equalizer (not shown) for performing channel equalization before the symbol demapper 3370 demaps the symbols.
  • the equalizer may perform channel equalization with respect to the received data using the pilot symbol.
  • the equalizer may channel equalization with respect to the received data symbols using the data symbols.
  • the equalizer may perform decision with respect to the symbols modulated by the lower order modulation among the data symbols according to the hybrid modulation method and perform channel equalization with respect to the data which is subjected to the decision process.
  • the channel can be estimated by a decision-directed channel estimation (DDCE) method with respect to the symbols modulated by the lower order modulation.
  • DDCE decision-directed channel estimation
  • the reliability used in the decision may be decided using a log-likelihood ratio (LLR), the SNR of the estimated channel and the channel state information.
  • the equalizer may update the channel estimation with respect to the symbol stream with high reliability according to an interpolation method and perform channel estimation of the overall symbol stream.
  • the equalizer may initialize the channel estimation with respect to the pilot symbol stream received periodically and update the channel estimation with respect to the overall symbol stream using only the channel estimated from the data symbol stream with high reliability. In this case, if the pilot symbol is located in the pilot symbol interval as shown in FIG. 8, the equalizer may use the pilot symbol.
  • FIG. 35 is a view showing an example of the symbol demapper of FIG. 34.
  • the symbol demapper 3370 includes a symbol parser 3371, a demapper 3373 and a bit merger 3375.
  • the symbol parser 3371 parses and outputs symbol data streams input to the symbol demapper 3370.
  • the symbol parser 3371 may parse the symbols mapped according to the same modulation method in the symbol data streams mapped according to the plurality of modulation methods.
  • the process of dividing the symbol data streams by the symbol parser 3371 is performed by the process inverse to the process of merging the symbols by the symbol merger 3125 of FIG. 33.
  • the demapper 3373 may demap the symbols mapped by the hybrid modulation method, that is, the plurality of modulation methods, according to the corresponding modulation methods.
  • the demapper 3373 may include symbol demapping units which demap the parsed symbol data streams according to the modulation methods of the data streams.
  • the demapper 3373 may include a first symbol demapping unit for demapping the symbols modulated by the 256-QAM to bit data and a second symbol demapping unit for demapping the symbols modulated by the 64-QAM to bit data.
  • the bit merger 3375 may merge the bit data demapped by the demapper 3373 and output a bit data stream.
  • FIG. 36 is a view showing an experimental result of the reception performance in the case where the signals transmitted by the examples of FIGs. 32 and 34 are received.
  • FIG. 36 shows the reception performance of the signals transmitted using the hybrid modulation method of the 256-QAM/64-QAM and a single modulation method of the 256-QAM in the case where the LDPC method is included as the FEC encoding method. If the percentage of the symbols modulated by the 64-QAM in one OFDM symbol by the hybrid modulation method of the 256-QAM/64-QAM is increased, the transfer rate is decreased, but the SNR gain is increased.
  • SNR gain of about at least 0.5 dB can be obtained according to the code rates of the LDPC even when the symbol modulation method is changed. Accordingly, the information transfer rate and the SNR gain can be adjusted by adjusting the symbol modulation method and the code rate using the hybrid method and the flexibility of the system can be increased.
  • FIG. 37 is a flowchart illustrating a method of transmitting a signal according to an embodiment of the present invention.
  • Input data is FEC-encoded such that a transmission error of transmitted data is found and corrected (S2200).
  • a BCH encoding method may be used as an outer encoder for preventing error floor.
  • an LDPC encoding method may be performed after the BCH encoding method is performed.
  • the FEC encoding method such as the LDPC may be used and the input data may be encoded at a plurality of coding rates. That is, the data which is FEC-coded by the hybrid method may be output.
  • the encoded data is interleaved so as to be robust against a burst error of a transmission channel, and the interleaved data is mapped to symbols according to the hybrid method (S2202).
  • symbol mapping a plurality of symbol mapping methods such as a QAM and a QPSK may be used.
  • the method of mapping the symbols according to the hybrid method may be performed by the symbol mapper shown in FIG. 33.
  • the symbol data mapped according to the plurality of symbol mapping methods is pre-coded so as to be dispersed in the frequency domain (S2204) and the pre-coded symbol data is interleaved (S2206).
  • the interleaved symbol data is multi-input/output encoded so as to be transmitted via a plurality of antennas (S2208).
  • the number of data transmission paths may be decided by the number of antennas.
  • data having the same information is transmitted via the paths and, in the spatial multiplexing method, different data is transmitted via the paths.
  • the encoded data is converted into a transfer frame according to the number of the multi-input/output transmission paths, the transfer frame is modulated, and the modulated frame is transmitted (S2210).
  • the transfer frame includes a pilot carrier symbol interval and a data symbol interval, and the pilot carrier symbol interval may have information for distinguishing between the transmission paths. For example, if the signal is transmitted via two antennas, even-numbered pilot carriers and odd- numbered pilot carriers of the pilot carrier may be transmitted via the respective antennas. Alternatively, if the signal is transmitted via two antennas, a sum of pilot carriers is transmitted at an even-numbered symbol position and a difference between the pilot carriers is transmitted at an odd-numbered symbol position such that the diversity effect can be obtained. In the case where the signal transmitting/receiving system uses the SISO method instead of the multi-input/output method, the step S2208 of multi-input/output encoding the symbol is not performed and the modulated signal is transmitted via one antenna.
  • FIG. 38 is a flowchart illustrating an embodiment of a method of receiving a signal.
  • the signals received via the transmission paths are synchronized and the synchronized signals are demodulated (S2300).
  • the demodulated data frame is parsed, the parsed signals are decoded according to the multi-input/output decoding method so as to obtain symbol data streams (S2302).
  • the symbol data which is interleaved so as to be robust against the frequency selective fading of the channel is deinterleaved in a manner inverse to the interleaving method (S2304).
  • the data streams restored by the deinterleaving process are decoded in a manner inverse to the pre-coding method so as to be restored to original symbol data dispersed in several pieces of symbol data in the frequency domain (S2306).
  • the restored symbol data is demapped according to the plurality of symbol mapping methods so as to be restored to bit data, and the bit data is deinterleaved so as to be restored to the original order (S2308).
  • the method of demapping the symbol according to the hybrid method may be performed by the symbol demapper shown in FIG. 35.
  • the symbols may be demapped by the hybrid method after the channel is estimated and compensated for.
  • the channel estimation method may be performed with the symbols on the basis of DDCE method. Since the above-described symbols have high reliability at the time of compensating for the channel, the channel estimation can be updated using the interpolation method with respect to the symbols.
  • the restored data is FEC-decoded so as to correct the transmission error (S2310).
  • the LDPC decoding method may be used.
  • the BCH decoding method may be performed after the LDPC decoding method is performed.
  • the data can be decoded at the code rates of the data intervals.
  • the channel can be estimated using only the symbol streams with high SNR gain according to the modulation method or the coding method.
  • the compensation of the estimated channel can be performed with respect to overall symbol stream.
  • step S2302 of multi-input/output decoding the symbol is not performed and the signal received via one transmission path can be processed.

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Abstract

La présente invention concerne un procédé d'émission/réception d'un signal et un appareil utilisé pour émettre/recevoir un signal. Des données d'entrées sont codées avec un code de correction aval des erreurs (FEC) de sorte qu'une erreur de données soit détectée et corrigée, puis ces données sont converties en symboles de données en fonction d'une pluralité de procédés de mappage de symboles afin de moduler les données transmises. Ainsi, il est possible d'assurer la commutation d'un système d'émission/réception du signal au moyen du réseau d'émission/réception du signal. De plus, il est possible d'améliorer un débit de transfert de données et d'accroître la distance de transmission du signal. Ainsi, on peut améliorer l'efficacité d'émission/réception du signal du système d'émission/réception.
PCT/KR2008/002327 2007-04-25 2008-04-24 Procédé d'émission et de réception d'un signal et appareil d'émission et de réception d'un signal WO2008133437A1 (fr)

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US11575394B2 (en) 2014-02-19 2023-02-07 Samsung Electronics Co., Ltd. Transmitting apparatus and interleaving method thereof
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CN113228578A (zh) * 2018-11-06 2021-08-06 外交和联邦事务大臣通过外交和联邦事务部行事 用于多个调制方案的改进解调制的设备和方法

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