WO2008130160A1 - Procédé et un appareil d'émission et de réception d'un signal - Google Patents

Procédé et un appareil d'émission et de réception d'un signal Download PDF

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Publication number
WO2008130160A1
WO2008130160A1 PCT/KR2008/002218 KR2008002218W WO2008130160A1 WO 2008130160 A1 WO2008130160 A1 WO 2008130160A1 KR 2008002218 W KR2008002218 W KR 2008002218W WO 2008130160 A1 WO2008130160 A1 WO 2008130160A1
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Prior art keywords
data
output
signal
input
decoder
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PCT/KR2008/002218
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English (en)
Inventor
Woo Suk Ko
Sang Chul Moon
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Lg Electronics Inc.
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Publication of WO2008130160A1 publication Critical patent/WO2008130160A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/256—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with trellis coding, e.g. with convolutional codes and TCM
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H03M13/296—Particular turbo code structure
    • H03M13/2972—Serial concatenation using convolutional component codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4138—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors soft-output Viterbi algorithm based decoding, i.e. Viterbi decoding with weighted decisions
    • H03M13/4146—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors soft-output Viterbi algorithm based decoding, i.e. Viterbi decoding with weighted decisions soft-output Viterbi decoding according to Battail and Hagenauer in which the soft-output is determined using path metric differences along the maximum-likelihood path, i.e. "SOVA" decoding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/85—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression
    • H04N19/89—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving methods or arrangements for detection of transmission errors at the decoder

Definitions

  • the present invention relates to a method of transmitting/receiving a signal and an apparatus for transmitting/receiving a signal, and more particularly to a method of transmitting/receiving a signal and an apparatus for transmitting/receiving a signal, which are capable of increasing a data transfer rate.
  • An object of the present invention is to provide a method of transmitting/receiving a signal and an apparatus for transmitting/receiving a signal, which are capable of increasing a data transfer rate and using the existing network for transmitting/receiving the signal.
  • This invetion provides an apparatus for transmitting a signal including a forward error correction (FEC) encoder which FEC-encodes input data by a turbo coding method, a first interleaver which mixes and interleaves the FEC-encoded data, a symbol mapper which converts the interleaved data into symbols such that a minimum Euclidean distance between symbols becomes a maximum, a second interleaver which interleaves the symbols in a frequency domain, an encoder which encodes the signal output from the second interleaver by a multi-input/output method, a frame builder which builds a frame including a data carrier interval in which the encoded signal is arranged and a preamble interval in which a pilot carrier signal is arranged, a modulator which modulates the built frame by an orthogonal frequency division multiplexing (OFDM) method and a transmitter which transmits the modulated signal, and a method thereof.
  • FEC forward error correction
  • the FEC encoder may include a first encoder which convolutionally encodes the input data, a turbo interleaver which interleaves any one of the input data and the data encoded by the first encoder and a second encoder which convolutionally encodes the data interleaved by the turbo interleaver.
  • the turbo interleaver may include a first bit selector which selects most significant bits of a bit stream of the input data, a bit reversing unit which reverses least significant bits excluding the most significant bits of the bit stream of the input data and outputs the reversed bits, a lookup table which stores correspondence bits corresponding to the least significant bits, a second bit selector which selects any one of the correspondence bits stored in the lookup table and the bits output from the first bit selector and outputs the selected bits and a rearrangement unit which arranges the bits output from the bit reserving unit as the most significant bits and arranges the bits output from the second bit selector as the least significant bits.
  • this invention provides an apparatus for receiving a signal including a receiver which receives a signal including a preamble interval in which a pilot carrier is arranged and a data carrier interval in which a data carrier is arranged, a synchronizer which acquires synchronization of the received signal, a demodulator which demodulates the signal, of which the synchronization is acquired, in a manner inverse to an orthogonal frequency division multiplexing (OFDM) method, and outputs the demodulated signal, a frame parser which parses the demodulated signal frame, a decoder which decodes the parsed data by a multi-input/output method and outputs symbols, a first deinterleaver which deinterleaves the decoded symbols, a symbol demapper which demaps the deinterleaved symbols to bit data according to a trellis coded decoding method, a second deinterleaver which deinterleaves the bit data according to a method of storing and reading the data
  • OFDM orthogon
  • the FEC decoder may include a second maximum a posteriori algorithm (MAP) decoder which MAP-decodes the data deinterleaved by the second deinterleaver, a deinterleaver which deinterleaves data according to a difference between the decoded data and the interleaved data, a first MAP decoder which MAP-decodes the deinterleaved data, an interleaver which outputs data according to a difference between the data deinterleaved by the deinterleaver and the data decoded by the first MAP decoder as the interleaved data and a decision unit which outputs data decided according to the data decoded by the first MAP decoder.
  • MAP maximum a posteriori algorithm
  • the FEC decoder may include a serial/parallel converter which outputs the data dein- terleaved by the second deinterleaver in parallel, a fourth maximum a posteriori algorithm (MAP) decoder which MAP-decodes the data output from the serial/parallel converter, a third MAP decoder which MAP-decodes the deinterleaved data and the data output from the serial/parallel converter, a deinterleaver which deinterleaves data according to a difference between the data decoded by the fourth MAP decoder and the interleaved data, an interleaver which outputs the interleaved data according to a difference between the deinterleaved data and the data decoded by the third MAP decoder and a decision unit which outputs data decided according to the data decoded by the third MAP decoder.
  • MAP maximum a posteriori algorithm
  • the symbol demapper may include an equalizer which compensates for channel distortion of symbol data and a trellis decoder which decodes the symbol data compensated for by the equalizer according to a trellis coding method.
  • FIG. 1 is a schematic block diagram showing an apparatus for transmitting a signal according to an embodiment of the present invention.
  • FIG. 2 is a schematic block diagram showing a forward error correction encoder according to the embodiment of the present invention.
  • FIG. 3 is a schematic block diagram showing another forward error correction encoder according to the embodiment of the present invention.
  • FIG. 4 is a schematic block diagram showing a turbo interleaver according to the embodiment of the present invention.
  • FIG. 5 is a view showing an interleaver for interleaving input data according to the embodiment of the present invention.
  • FIG. 6 is a schematic block diagram showing a trellis coded modulator according to the embodiment of the present invention. [21] FIG.
  • FIG. 7 is a schematic block diagram showing a linear pre-coder according to the embodiment of the present invention.
  • FIGs. 8 to 10 are views showing code matrixes for dispersing input data according to the embodiment of the present invention.
  • FIG. 11 is a view showing a structure of a transfer frame according to the embodiment of the present invention.
  • FIG. 12 is a schematic block diagram showing an apparatus for transmitting a signal with a plurality of transmission paths according to the embodiment of the present invention.
  • FIGs. 13 to 17 are views showing examples of 2x2 code matrixes for dispersing input symbols according to the embodiment of the present invention.
  • FIG. 18 is a view showing an example of the interleaver according to the embodiment of the present invention. [27] FIG.
  • FIG. 19 is a view showing a detailed example of the interleaver of FIG. 11 according to the embodiment of the present invention.
  • FIG. 20 is a view showing an example of a multi-input/output encoding method according to the embodiment of the present invention.
  • FIG. 21 is a view showing a structure of a pilot symbol interval according to the embodiment of the present invention.
  • FIG. 22 is a view showing another structure of the pilot symbol interval according to the embodiment of the present invention.
  • FIG. 23 is a schematic block diagram showing an apparatus for receiving a signal according to an embodiment of the present invention.
  • FIG. 24 is a schematic block diagram showing an example of a linear pre-coding decoder according to the embodiment of the present invention.
  • FIG. 25 is a schematic block diagram showing another example of the linear pre- coding decoder according to the embodiment of the present invention.
  • FIGs. 26 to 28 are views showing examples of a 2x2 code matrix for restoring the dispersed symbols according to the embodiment of the present invention.
  • FIG. 29 is a schematic block diagram showing a trellis coded modulation decoder according to the embodiment of the present invention.
  • FIG. 30 is a schematic block diagram showing a forward error correction decoder according to the embodiment of the present invention.
  • FIG. 31 is a schematic block diagram showing another forward error correction decoder according to the embodiment of the present invention.
  • FIG. 38 is a schematic block diagram showing another forward error correction decoder according to the embodiment of the present invention.
  • FIG. 32 is a schematic block diagram showing an apparatus for receiving a signal with a plurality of reception paths according to the embodiment of the present invention.
  • FIG. 33 is a view showing an example of a multi-input/output decoding method according to the embodiment of the present invention.
  • FIG. 34 is a view showing a detailed example of FIG. 19 according to the embodiment of the present invention.
  • FIG. 35 is a schematic block diagram showing another example of the apparatus for transmitting the signal according to the embodiment of the present invention.
  • FIG. 36 is a schematic block diagram showing another example of the apparatus for receiving the signal according to the embodiment of the present invention.
  • FIG. 37 is a flowchart showing a method of transmitting a signal according to an embodiment of the present invention.
  • FIG. 38 is a flowchart showing a method of receiving a signal according to an embodiment of the present invention.
  • FIG. 1 is a schematic block diagram showing an apparatus for transmitting a signal according to an embodiment of the present invention.
  • the apparatus for transmitting the signal of FIG. 1 may be a broadcasting signal transmitting system for transmitting a broadcasting signal including video data and so on.
  • a signal transmitting system according to a digital video broadcasting (DVB) system will now be described.
  • the signal transmitting system will be described, concentrating on an operation for processing a signal.
  • FIG. 1 The embodiment of FIG.
  • the FEC encoder 100 encodes an input signal and outputs the encoded signal such that an error generated in transmitted data is detected and corrected by a receiving apparatus.
  • the data encoded by the FEC encoder 100 is input to the first interleaver
  • the first interleaver 110 mixes a data stream output from the FEC encoder 100 and disperses the data stream at random locations so as to be robust against a burst error generated in data at the time of transmission of data.
  • a convolution interleaver or a block interleaver may be used, which may be changed according to a transmission system.
  • the embodiment of the first interleaver is shown in FIG. 3 in detail.
  • the detailed example of the first interleaver 110 will be described in detail with reference to FIG. 3.
  • the data interleaved by the first interleaver 110 is input to the trellis coded modulator
  • the trellis coded modulator 120 may convert the input data into coded symbol data. That is, the trellis coded modulator 120 encodes the transmitted signal and maps the encoded signal to symbols according to a quadrature amplitude modulation (QAM) or quadrature phase-shift keying (QPSK) scheme.
  • QAM quadrature amplitude modulation
  • QPSK quadrature phase-shift keying
  • the linear pre-coder 130 disperses input symbol data into several pieces of output symbol data such that a probability that all information is lost by fading when experiencing a frequency- selective fading channel is reduced.
  • the detailed example of the linear pre-coder 130 will be described with reference to FIGs. 7 to 10.
  • the second interleaver 140 interleaves the symbol data output from the linear pre- coder 130 again. That is, if the second interleaver 140 performs interleaving, it is possible to correct an error generated when the symbol data experiences the same frequency- selective fading at a specific location.
  • a convolution interleaver or a block interleaver may be used as the second interleaver 140.
  • the linear pre-coder 130 and the second interleaver 140 process data to be transmitted so as to be robust against the frequency-selective fading of the channel, and may be collectively called a frequency-selective fading coder.
  • the multi- input/output encoder 150 encodes the data interleaved by the second interleaver 140 so as to be transmitted via a plurality of transmission antennas.
  • the apparatus for transmitting/receiving the signal can process the signal according to the multi-input/output method.
  • the multi-input/output method includes a multi-input multi-output (MIMO) method, a single-input multi-output (SIMO) and a multi-input single-output (MISO) method.
  • the multi-input/output encoding method may include a spatial multiplexing method and a spatial diversity method.
  • the spatial multiplexing method different data is simultaneously transmitted using multiple antennas of a transmitter and a receiver such that the data can be rapidly transmitted without increasing the bandwidth of the system.
  • the spatial diversity method data having the same information is transmitted via multiple transmission antennas such that the diversity effect can be obtained.
  • a space-time block code STBC
  • SFBC space-frequency block code
  • STTC space-time trellis code
  • a method of dividing the data stream by the number of transmission antennas and transmitting the data stream a full-diversity full-rate (FDFR) code, a linear dispersion code (LDC), a vertical-bell lab layered space-time (V-BLAST), or a diagonal-BLAST (D-BLAST) may be used.
  • FDFR full-diversity full-rate
  • LDC linear dispersion code
  • V-BLAST vertical-bell lab layered space-time
  • D-BLAST diagonal-BLAST
  • the frame builder 160 inserts the precoded pilot signal into a predetermined location of a frame and builds the frame defined in the transmission/reception system.
  • the frame builder 160 may arrange a data symbol interval and a pilot symbol interval, which is a preamble of the data symbol interval, in the frame.
  • the frame builder may arrange dispersed pilot carriers, of which the locations are temporally shifted, in a data carrier interval.
  • the frame builder may arrange consecutive pilot carriers, of which the locations are temporally fixed, in the data carrier interval.
  • the modulator 170 carries the data output from the frame builder 160 in orthogonal frequency division multiplex (OFDM) subcarriers so as to perform the OFDM modulation and inserts a guard interval between the modulated symbols.
  • OFDM orthogonal frequency division multiplex
  • the transmitter 180 converts a digital signal having the guard interval and the data interval, which is output from the modulator 170, into an analog signal and transmits the analog signal.
  • FIG. 2 is a block diagram showing an example of the FEC encoder.
  • a turbo code encoder may be used.
  • the turbo code encoder includes at least two configuration encoders and a turbo interleaver and may be divided into a parallel concatenated convolutional code (PCCC) and a serially concatenated con- volutional code (SCCC) according to the concatenation method of the configuration encoders.
  • PCCC parallel concatenated convolutional code
  • SCCC serially concatenated con- volutional code
  • the configuration encoders the same type of encoder may be used or double encoding may be performed using different types of encoders.
  • the example of FIG. 2 is the SCCC in which convolution encoders are used as the configuration encoders.
  • the turbo code encoder includes a first convolution encoder 102, a turbo interleaver 104 and a second convolution encoder 106.
  • the first convolution encoder 102 convolutionally encodes input data and outputs the encoded data
  • the turbo interleaver 104 interleaves the output data and mixes the data.
  • the second convolution encoder 106 convolutionally encodes the interleaved data and outputs the encoded data.
  • the input data is doubly encoded using the first convolution encoder and the second convolution encoder.
  • FIG. 3 is a block diagram showing another example of the FEC encoder.
  • the example of FIG. 3 is the PCCC in which the convolution encoders are used as the configuration encoders.
  • the turbo code encoder includes a third convolution encoder 101, a turbo interleaver 103, a fourth convolution encoder 105 and a parallel/serial converter 107.
  • the third convolution encoder 101 convolutionally encodes input data in sequence and outputs the encoded data
  • the fourth convolution encoder 105 convolutionally encodes the data, which is interleaved and mixed by the turbo interleaver 103, and outputs the encoded data.
  • the parallel/serial converter 107 punctures the data encoded by the third convolution encoder 101 and the fourth convolution encoder 105 and outputs a data stream.
  • FIG. 4 is a block diagram showing an example of the turbo interleaver.
  • a helical interleaver an odd-even interleaver, a PN interleaver, a random interleaver, a S -random interleaver, a nonuniform interleaver, or a Galois field interleaver may be used.
  • the example of FIG. 4 is an interleaver such as a block interleaver, which includes a first LSB selector 300, a lookup table 310, a bit reversing unit 320, a second LSB selector 330 and a rearrangement unit 340.
  • a block interleaver which includes a first LSB selector 300, a lookup table 310, a bit reversing unit 320, a second LSB selector 330 and a rearrangement unit 340.
  • MSBs most sig °nificant bits (MSBs) of the n+5 bits (1 n+4 , 1 n+3 , 1 n+2 , ..., 15 , 14 , 13 , 12 , 11 , 10 ) are input to the first LSB selector 300 and five (1 , 1 , 1 , 1 , 1 ) least significant bits (LSBs) are input to the lookup table 310 and the bit reversing unit 320.
  • MSBs most sig °nificant bits
  • the first LSB selector 300 adds one bit to the input data bits and selects and outputs n LSBs.
  • the lookup table 310 outputs n bits which are previously stored in correspondence with the five input bits, and the bit reversing unit 320 reverses the order of five input bits and outputs the reversely-ordered bits.
  • the second LSB selector 330 multiplies the n bits output from the first LSB selector
  • the rearrangement unit 340 arranges the five reversely-ordered bits (1 , 1 , 1 , 1 , 1 )
  • 0 1 output from the bit reversing unit 320 as the MSBs, arranges the n bits (t , t , t , ..., n-l n-2 n-3 t , t , t ) as the LSBs and outputs the n+5 bits (1 , 1 , 1 , 1 , 1 , 1 , t , t , t , ..., t , t , t ).
  • the rearrangement unit 340 discards an output value if the input is equal to or larger than the block length (input ⁇ N ).
  • the data which is FEC-encoded by the FEC encoder 100 is output to the first interleaver 110.
  • FIG. 5 is a view showing the first (second) interleaver shown in FIG. 1. As the first
  • (second) interleaver of FIG. 5 for example, a block interleaver may be used.
  • the interleaver of FIG. 5 stores input data in a matrix-shaped memory space in a predetermined pattern and reads and outputs the data in a pattern different from the pattern used for storing the data.
  • the interleaver of FIG. 5 has an NrxNc memory space composed of Nr rows and Nc columns and the data input to the interleaver is filled from a position corresponding to a first row and a first column of the memory space.
  • the data is stored from the first row and the first column to an Nrthrow and the first column and, if the first column is filled up, is then stored from the first row to the Nr row of a next column (second column).
  • the data may be stored up to the Nr row of an Nc column (i.e. the data are stored column- wise).
  • the data is read and output from the first row and the first column to the first row and the Nc column. If all the data of the first row is read, the data is read and output from the first column of a next row (second row) in the column direction. In this sequence, the data may be read and output up to the Ncth column of the Nr row (i.e. the data are read out row- wise).
  • the position of a most significant bit (MSB) of the data block is a left uppermost side and the position of a least significant bit (LSB) thereof is a right lowermost side.
  • the size of the memory block, the storage pattern and the read pattern of the interleaver are only exemplary and may be changed according to implementation embodiments.
  • the size of the memory block of the first interleaver may vary according to the size of the FEC-encoding block.
  • FIG. 6 is a schematic block diagram showing an example of the trellis coded modulator.
  • the trellis coded modulator 120 includes a delay element and a bitwise operator.
  • a delay element 122 and a second delay element 124 two delay elements (a first delay element 122 and a second delay element 124) and a bitwise adder 126 are used. That is, the numbers of delay elements and bitwise operators may vary according to the number of states or the number of input bits to be trellis -encoded.
  • n bits X i to X input to the trellis coded modulator 120 are output via a regular code path as n (Y to Y ) MSBs.
  • An output Y and an output Y which is an additional trellis-encoded bit are output by the input LSB X .
  • the bitwise adder 126 adds the input value X and the value output from the first delay element 122 in bitwise units and outputs the added value.
  • the second delay element 124 delays the value output from the bitwise adder 126 and outputs Y .
  • the value output from the second delay element 124 is fed back to the first delay unit 122.
  • bits Y and Y are used for selecting a coset which is
  • the trellis coded modulator 120 can decrease an error of a bit for selecting the coset in the case where the number of states is increased or the number of input bits to be trellis-encoded is increased.
  • the linear pre-coder 130 disperses the input symbol data into several pieces of output symbol data such that a probability that all information is lost by fading when experiencing the frequency-selective fading channel is reduced.
  • FIG. 7 is a schematic block diagram showing the linear pre-coder of FIG. 1.
  • the linear pre-coder 130 may include a serial/parallel converter 132, an encoder 134 and a parallel/serial converter 136.
  • the serial/parallel converter 132 converts the input data into parallel data.
  • the encoder 134 disperses the values of the converted parallel data into several pieces of data via the operation of an encoding matrix.
  • FIG. 8 is a schematic block diagram showing the linear pre-coder of FIG. 1.
  • the linear pre-coder 130 may include a serial/parallel converter 132, an encoder 134 and a parallel/serial converter 136.
  • the serial/parallel converter 132 converts the input data into parallel data.
  • the encoder 134 disperses the values of the converted parallel data into several pieces of data via the operation of an encoding matrix.
  • FIG. 9 is a view showing an example of the encoding matrix used by the encoder
  • FIG. 6 shows an example of the encoding matrix for dispersing the input data into several pieces of output data, which is also called a vanderMonde matrix.
  • the input data may be arranged in parallel by the length of the number (L) of output data.
  • ⁇ of the matrix may be expressed by the following equation and may be defined by other methods. If the vanderMonde matrix is used as the encoding matrix, a matrix element may be determined according to Math Figure 1.
  • the encoding matrix of Math Figure 1 rotates the input data by the phase of Equation
  • FIG. 9 shows another example of the encoding matrix.
  • FIG. 9 shows another example of the encoding matrix for dispersing the input data into severalpieces of output data, which is also called a Hadamard matrix.
  • the matrix of FIG. 9 is a matrix having a general form, in which L is expanded by 2 .
  • L denotes the number of output symbols into which the input symbols will be dispersed.
  • the output symbols of the matrixof FIG. 9 can be obtained by a sum and a difference among L input symbols.
  • the input symbols may be dispersed into the L output symbols, respectively.
  • FIG. 10 shows another example of the encoding matrix for dispersing the input data.
  • FIG. 10 shows another example of the encoding matrix for dispersing the input data into severalpieces of output data, which is also called a Golden code.
  • the Golden code is a 4x4 matrix having a special form. Alternatively, two different 2x2 matrixes may be alternately used.
  • [I l l] C of FIG. 10 denotes a code matrix of the Golden code and xl, x2, x3 and x4 in the code matrix denote symbol data which can be input to the encoder 134 of FIG. 8 in parallel.
  • Constants in the code matrix may decide the characteristics of the code matrix, and the values of the rows and the columns computed by the constants of the code matrix and the input symbol data may be expressed by the output symbol data.
  • the output sequence of the symbol data may vary according to the implementation embodiments. Accordingly, in this case, the parallel/serial converter 136 of FIG. 7 may convert the paralleldata into the serial data according to the position sequence of the data in a parallel data set output from the encoder 134 and output the serial data.
  • FIG. 11 is a view showing a structure of a transfer frame of the data channel-coded by the above-described embodiments.
  • the transfer frame formed according to the present embodiment may include a pilot symbol including pilot carrier information and a data symbol including data information.
  • a frame includes M (M is a natural number) intervals and is divided into M- 1 data symbol intervals and a pilot symbol interval which is used as a preamble.
  • M is a natural number
  • Each symbol interval includes carrier information by the number of OFDM subcarriers.
  • the pilot carrier information of the pilot symbol interval is composed of random data in order to decrease a peak- to- average power ratio (PAPR).
  • An autocorrelation value of the pilot carrier information has an impulse shape in a frequency domain. The correlation value between file carrier symbols may be close to 0.
  • the pilot symbol interval used as the preamble allows the receiver to quickly recognize the signal frame of FIG. 11 and may be used for correcting and synchronizing a frequency offset. Since the pilot symbol interval representsthe start of the signal frame, a system transmission parameter for allowing the received signal to be quickly synchronized may be set.
  • the frame builder builds the data symbol intervals and inserts the pilot symbol interval in front of the data symbol intervals, thereby building a transfer frame.
  • pilot carrier information may not be included in the data symbol intervals. Accordingly, it is possible to increase a data capacity.
  • the DVB for example, since a percentage of pilot carriers in all the valid carriers is about 10%, the increasing rate of the data capacity is expressed by Math Figure 3 .
  • Math Figure 3 denotes the increasing rate and M denotes the number of intervals included in a frame.
  • FIG. 12 is a schematic block diagram showing another example of the apparatus for transmitting the signal in the case where the apparatus for transmitting the signal has a plurality of transmission paths according to the embodiment of the present invention.
  • the number of transmission paths is two.
  • FIG. 12 includes a FEC encoder 900, a first interleaver 910, a trellis coded modulator 920, a linear pre-coder 930, a second interleaver 940, a multi- input/output encoder 950, a first frame builder 960, a second frame builder 965, a first modulator 970, a second modulator 975, a first transmitter 980 and a second transmitter 985.
  • the FEC encoder 900 includes a BCH encoder and an LDPC encoder, FEC-encodes input data, and outputs the encoded data.
  • the output data is interleaved by the first interleaver 910 such that the data stream are mixed.
  • a convolution interleaver or a block interleaver may be used as the first interleaver 910.
  • the trellis coded modulator 920 converts the input data into coded symbol data. That is, the trellis coded modulator 820 codes the transmitted signal and maps the coded signal to symbols according to the QAM or QPSK scheme. For example, 7-bit data may be included in one symbol in the case where the signal is mapped to the symbols by 128QAM and 8-bit data may be included in one symbol in the case where the signal is mapped to the symbols by 256QAM.
  • the linear pre-coder 930 includes a serial/parallel converter, an encoder and a parallel/serial converter.
  • An example of a coding matrix used by the encoder of the linear pre-coder 930 is shown in FIGs. 12 to 16.
  • the second interleaver 940 interleaves the symbol data output from the linear pre- coder 930 again.
  • a convolution interleaver or a block interleaver may be used as the second interleaver 940.
  • the second interleaver 940 mixes the symbol data such that the symbol data dispersed in the data output from the linear pre-coder 930 does not experience the frequency- selective fading at a specific location of a frame.
  • the interleaving method may vary according to the implementation examples of the transmission/reception system.
  • the length of the interleaver may vary according to the implementation examples. If the length of the interleaver is equal to or smaller than the length of an OFDM symbol, interleaving is performed only with respect to one OFDM symbol and, if the length of the interleaver is larger than the length of the OFDM symbol, interleaving may be performed with respect to several symbols.
  • FIGs. 18 and 19 show the interleaving method in detail.
  • the interleaved data is output to the multi-input/output encoder 950.
  • the multi- input/output encoder 950 encodes the input symbol data so as to be transmitted via the plurality of transmission antennas and outputs the encoded data. For example, if two transmission paths are included, the multi-input/output encoder 950 outputs the pre- coded data to the first frame builder 960 or the second frame builder 965.
  • the data having the same information is output to the first frame builder 960 and the second frame builder 965. If encoding is performed by the spatial multiplexing method, different data is output to the first frame builder 960 and the second frame builder 965.
  • the first frame builder 960 and the second frame builder 965 build frames, into which a pilot signal is inserted, such that the received signals are modulated by the OFDM method.
  • the frame includes one pilot symbol interval and M-I data symbol intervals.
  • the structure of the pilot symbol may be decided such that the transmission paths are distinguished by the receiving apparatus.
  • FIGs. 21 and 22 The example of the multi-input/output encoder 950 of FIG. 12 is shown in FIGs. 21 and 22.
  • the first modulator 970 and the second modulator 975 modulate the data output from the first frame builder 960 and the second frame builder 965 so as to be transmitted by the OFDM subcarriers.
  • the first transmitter 980 and the second transmitter 985 respectively convert the digital signals having the guard interval and the data interval, which are output from the first modulator 970 and the second modulator 975, into analog signals and transmit the converted analog signals.
  • FIGs. 13 to 17 are views showing an example of a 22 code matrix for dispersing input symbols as an example of the encoding matrix of the linear pre-coder.
  • the code matrixes of FIGs. 13 to 17 disperse twopieces of data input to the encoding unit of the linear pre-decoder 730 to two pieces of output data.
  • the matrix of FIG. 13 is an example of the vanderMonde matrix described with reference to FIG. 8, in which L is 2.
  • first inputdata and second input data, of which phase is rotated by 45 degrees are rotated by 45 degrees
  • first input data and second input data of which phase is rotated by 225 degrees
  • the code matrix of FIG. 14 is an example of the Hadamard matrix.
  • FIG. 15 shows another example of the code matrix for dispersing the input symbols.
  • the matrix of FIG. 15 is an example of a code matrix different from the matrix described with reference to FIGs. 8, 9 and 10. [142] In the matrix of FIG. 15, first input data, of which phase is rotated by 45 degrees (
  • FIG. 16 showsanother example of the code matrix for dispersing the input symbols.
  • the matrix of FIG. 16 is an example of a code matrix different from the matrix described with reference to FIGs. 8, 9 and 10. [144] In the matrix of FIG. 16, first input data which is multiplied by 0.5 and second input data are added and first output data is output. Then, second input data which is mul- tipliedby 0.5 is subtracted from first input data and second output data is output. The output data is divided by
  • FIG. 17 shows another example of the code matrix for dispersing the input symbols.
  • the matrix of FIG. 17 is an example of a code matrix different from the matrix described with reference to FIGs. 8, 9 and 10.
  • "*" of FIG. 14 denotes a complex conjugate of the input data.
  • FIG. 18 is a view showing an example of an interleaving method of the interleaver.
  • the interleaving method of FIG. 18 is an example of the interleaver of the OFDM system having a symbol length N, which can be used in the second interleaver 740 of the transmitting apparatus shown in FIG. 9.
  • N denotes the length of the interleaver and i has a value corresponding to the length of the interleaver, that is, an integer from 0 to N-I.
  • n denotes the number of valid transmission carriers in a transmitting system.
  • FI(i) denotes a permutation obtained by a modulo-N operation
  • dn has a FI(i) value which is located in a valid transmission carrier area excluding a value N/2 in sequence
  • k denotes an index value of an actual transmission carrier.
  • N/2 is subtracted from dn such that the center of the transmission bandwidth becomes DC.
  • P denotes a permutation constant which may vary according to implementation embodiments.
  • FIG. 19 is a view showing a variable which varies according to the interleaving method of FIG. 18.
  • the length of the OFDM symbol and the length N of the interleaver are set to 2048 and the number of valid transmission carriers are set to 1536 (1792-256).
  • i is an integer from 0 to 2047 and n is aninteger from 0 to 1535.
  • dn denotes a permutation obtained by a modulo-2048 operation
  • dn has a FI(i) value with respect to a value 256 ⁇ FI(i) ⁇ 1792 excluding a value 1024(N/2) in sequence
  • k denotes a value obtained by subtracting 1024 from dn.
  • P has a value of 13.
  • data corresponding to the sequence i of the input data may be changed to the sequence k of the interleaved data with respect to the length N of the interleaver.
  • FIG. 20 is a view showing an example of the encoding method of the multi- input/output encoder.
  • the embodiment of FIG. 20 is the STBC which is one of the multi-input/output encoding methods and may be used in the transmitting apparatus shown in FIG. 10.
  • T denotes a symbol transmission period
  • s denotes an input symbol to be transmitted
  • y denotes an output symbol
  • * denotes a complex conjugate
  • a first antenna (Tx #1) and a second antenna (Tx #2) denote a first transmission antenna and a second transmission antenna 2, respectively.
  • the first antenna Tx #1 transmits s0 and the second antenna Tx #2 transmits si.
  • the first antenna Tx #1 transmits - si* and the second antenna Tx #2 transmits s ⁇ *.
  • the transmission antennas transmit data having the same information of s0 and si in the transmission period. Accordingly, the receiver can obtain spatial diversity effect using the signals output from the multi- input/output encoder according to the method shown in FIG. 18.
  • the signals transmitted by the first antenna and the second antenna shown in FIG. 20 are examples of the multi-input/output encoded signals.
  • the signals transmitted by the first antenna and the second antenna may be transmitted by a multi-input single-output method.
  • FIG. 20 shows a simplest example using two antennas. The signals may be transmitted according to the method shown in FIG. 20 using more antennas.
  • the consecutive first and second symbols are multi- input and a minus of a complex conjugateof the second symbol and a complex conjugate of the first symbol are simultaneously output.
  • the multi-input symbols may be encoded according to an Alamouti algorithm and the encoded symbols may be output.
  • the multi-input/output encoder may transmit the signals which are interleaved by the second interleaver in the frequency domain, by the multi-input single-output method.
  • the multi-input/output (including the multi-input single-output) shown in FIG. 20 may be not applied to the pilot symbol interval shown in FIGs. 21 and 22 and may be applied to only the data symbol interval.
  • FIG. 21 is a view showing a structure of the pilot carriers in the pilot symbol intervals built by the first and second frame builders of FIG. 12.
  • the pilot symbol intervals built by the frame builders of FIG. 12 may be output as shown in FIG. 21.
  • FIG. 21 shows the respective pilot symbols built by the first and second frame builders as the signals output from the first and second antennas.
  • an even-numbered pilot carrier and an odd- numbered pilot carrier are respectively interleaved as shown in FIG. 21 and the interleaved carriers may be output to the first and second antennas #1 and #2.
  • the receiver can distinguish between the transmission paths using the carrier indexes of the pilot symbol intervals received via the two signal paths.
  • the structure of the pilot symbol interval of FIG. 21 may be used when the multi-input/output encoding is performed so as to have the two transmission paths as shown in FIG. 14.
  • a channel corresponding to a subcarrier of a half of a frame may be estimated from a symbol. Accordingly, high channel estimation performance can be obtained with respect to a transmission channel having a short coherence time.
  • FIG. 22 is a view showing another structure of the pilot carriers in the pilot symbol intervals built by the first and second frame builders of FIG. 12. Even in the example of FIG. 22, different pilot carriers are transmitted by the pilot symbol intervals via the paths according to the multi-input/output encoding method.
  • Hadamard conversion is performed in the unit of a symbol interval in order to distinguish between the two transmission paths. For example, pilot carriers obtained by adding the two pieces of pilot carrier information of the transmission paths are transmitted by the even-numbered symbol interval and a difference between the two pieces of pilot carrier information is transmitted by the odd-numbered symbol interval.
  • the pilot symbol interval includes even-numbered intervals and odd-numbered intervals which are arranged with time.
  • the even-numbered symbols of the pilot carriers are transmitted via a first path (first antenna (denoted by antenna #0)) and a second path (second antenna (denoted by antenna #1)). Accordingly, the receiver can use the pilot carriers obtained by adding the pilot carriers transmitted via the two paths.
  • the odd-numbered symbols of the pilot carriers are transmitted via the first path (first antenna (denoted by antenna #0)) and the pilot carriers having a phase difference of 180 degrees are transmitted via the second path (second antenna (denoted by antenna #1)). Accordingly, the receiving apparatus can recognize the sum of or difference between the two pieces of pilot carrier information via a received pilot index and distinguish between the transmission paths.
  • a channel corresponding to all subcarriers can be estimated and the estimation length of delay spread of the channel which can be processed by each transmission path can be extended by a symbol length.
  • FIG. 22 The example of FIG. 22 is shown for facilitating the distinguishment between the two pieces of pilot carrier information and shows both the two pieces of pilot carrier information in the frequency domain.
  • impulses of the two pieces of pilot carrier information are located at the same frequency point.
  • FIGs. 21 and 22 are examples in which the number of transmission paths is two. If the number of transmission paths is larger than 2, the pilot carrier information may be divided so as to be distinguished by the number of transmission paths similarly to FIG. 21. Alternatively, the pilot carrier information may be subjected to Hadamard conversion in the unit of a symbol interval and the converted information may be transmitted similarly to FIG. 22.
  • FIG. 23 is a block diagram showing an apparatus for receiving a signal according to another embodiment of the present invention.
  • the apparatus for transmitting/receiving the signal may be a system for transmitting/receiving a broadcasting signal according to a DVB system.
  • the embodiment of FIG. 23 includes a receiver 1500, a synchronizer 1510, a demodulator 1520, a frame parser 1530, a multi-input/output decoder 1540, a first dein- terleaver 1550, a linear pre-coding decoder 1560, a trellis coded modulation decoder 1570, a second deinterleaver 1580, and a FEC decoder 1590.
  • the embodiment of FIG. 23 will be described concentrating on a procedure of processing the signal by the signal receiving system.
  • the receiver 1500 down-converts the frequency band of a received RF signal, converts the signal into a digital signal, and outputs the digital signal.
  • the synchronizer 1510 acquires synchronization of the received signal output from the receiver 1500 in a frequency domain and a time domain and outputs the synchronization.
  • the synchronizer 1510 may use an offset result of the data output from the demodulator 1520 in the frequency domain, for acquiring the synchronization of the signal in the frequency domain.
  • the demodulator 1520 demodulates the received data output from the synchronizer 1510 and removes the guard interval.
  • the demodulator 1520 may convert the received data into the frequency domain and obtain data values dispersed into the subcarriers.
  • the frame parser 1530 may output symbol data of the data symbol interval excluding the pilot symbol according to the frame structure of the signal demodulated by the demodulator 1520.
  • the frame parser 1530 may parse the frame using at least one of a dispersion pilot carrier of which the location is temporally shifted in the data carrier interval and a consecutive pilot carrier of which the location is temporally fixed in the data carrier interval.
  • the multi-input/output decoder 1540 receives the data output from the frame parser 1530, decodes the data, and outputs a data stream.
  • the multi- input/output decoder 1540 decodes the data stream received via the plurality of transmission antennas according to a method corresponding to the transmitting method of the multi- input/output encoder shown in FIG. 1 and outputs the data stream.
  • the first deinterleaver 1550 deinterleaves the data stream output from the multi- input/output decoder 1540 and restores the data into the order of the data before interleaving.
  • the first deinterleaver 1550 deinterleaves the data stream according to a method corresponding to the interleaving method of the second interleaver 140 shown in FIG. 1 and restores the order of the data stream.
  • the linear pre-coding decoder 1560 performs an inverse process of the process of dispersing the data in the apparatus for transmitting the signal. Accordingly, the data dispersed according to the linear pre-coding may be restored to the data before dispersing.
  • the embodiment of the linear pre-coding decoder 1560 is shown in FIGs. 24 to 26.
  • the trellis coded modulation decoder 1570 may restore the coded symbol data output from the linear pre-coding decoder 1560 into a bit stream.
  • the second deinterleaver 1580 deinterleaves the data stream output from the trellis coded modulation decoder 1570 and restores the data into the order of the data before interleaving.
  • the second deinterleaver 1580 deinterleaves the data according to a method corresponding to the interleaving method of the first interleaver 110 shown in FIG. 1 and restores the order of the data stream.
  • the FEC decoder 1590 FEC-decodes the data, in which the order of the data stream is restored, detects an error generated in the received data, and corrects the error.
  • the example of the FEC decoder 1590 is shown in FIGs. 30 and 31.
  • FIG. 24 is a schematic block diagram showing an example of the linear pre-coding decoder of FIG. 12.
  • the linear pre-coding decoder 1560 includes a serial/parallel converter 1562, a first decoder 1564 and a parallel/serial converter 1566.
  • the serial/parallel converter 1562 converts the input data into parallel data.
  • the first decoder 1564 may restore the data, which is linearly pre-coded and is dispersed into the parallel data, as the original data via a decoding matrix.
  • the decoding matrix for performing decoding becomes an inverse matrix of the encoding matrix of theapparatus for transmitting the signal. For example, when the apparatus for transmitting the signal performs the encoding operation using the vanderMonde matrix, the Hadamard matrix and the Golden code shown in FIGs. 8, 9 and 10, the first decoder 1564 restores the dispersed data as the original data using the inverse matrixes of the matrixes.
  • the parallel/serial converter 1566 converts the parallel data received by the first decoder 1564 into the serial data and outputs the serial data.
  • FIG. 25 is a schematic block diagram showing another example of the linear pre- coding decoder.
  • the linear pre-coding decoder 1560 includes a serial/parallel converter 1561, a second decoder 1563 and a parallel/serial converter 1565.
  • the serial/parallel converter 1561 converts the input data into parallel data
  • the parallel/serial converter 1565 converts the parallel data received from the second decoder 1563 into serial data and outputs the serial data.
  • the second decoder 1563 may restore the original data, which is linearly pre-coded and is dispersed into the parallel data output from the serial/parallel converter 1561, using maximum likelihood (ML) decoding.
  • ML maximum likelihood
  • the second decoder 1563 is the ML decoder for decoding the data according to the transmitting method of the transmitter.
  • the second decoder 1463 ML-decodes the received symbol data according to the transmitting method and restores the data dispersed in the parallel data to the original data. That is, the ML decoder ML-decodes the received symbol data according to the encoding method of the transmitter.
  • FIGs. 26 to 28 are views showing examples of a 22 code matrix for restoring the dispersed symbols.
  • the code matrixes of FIGs. 26 to 28 show inverse matrixes corresponding to the 22 encoding matrixes of FIGs. 15 to 14.
  • the code matrixes restore data which is dispersed into two pieces of data input to the decoding unit of the linear pre-coding decoder 1560 and output the restored data.
  • the 2x2 code matrix of FIG. 26 is a decoding matrix corresponding to the encoding matrix of FIG. 15.
  • FIG. 27 shows another example of the 2x2 code matrix.
  • the matrix of FIG. 27 is a decoding matrix corresponding to the encoding matrix of FIG. 13.
  • first input data which is multiplied by 0.5 and second input data are added and first output data is output.
  • second input data which is multipliedby 0.5 is subtracted from first input data and second output data is output.
  • the output data is divided by
  • FIG. 28 shows another example of the 22 code matrix.
  • the matrix of FIG. 28 is a decoding matrix corresponding to the encoding matrix of FIG. 17.
  • "*"of FIG. 28 denotes a complex conjugate of the input data.
  • FIG. 29 is a block diagram showing an example of the trellis coded modulation decoder.
  • the trellis coded modulation decoder 1570 includes an equalizer 1572, a soft- output viterbi algorithm (SOVA) trellis decoder 1574.
  • SOVA soft- output viterbi algorithm
  • the equalizer 1572 compensates for the distortion due to the transmission channel and outputs the symbol data.
  • the equalization at the symbol level is not limited to the above location.
  • the symbol data which is pre-coding decoded by the linear pre-coding decoder 1560 may be equalized and the equalization may be performed at the output location of the first deinterleaver 1550, the output location of the multi- input/output decoder 1540 and the output location of the frame parser 1530.
  • the location of the equalizer 1572 may vary according to the implementation examples.
  • the equalized symbol data is input to the SOVA trellis decoder 1574.
  • the SOVA trellis decoder 1574 trellis-decodes the input symbol data, decodes the transmitted symbol data, and demaps the decoded data to bit data. If the LDPC code is used as the FEC code, the SOVA trellis decoder 1574 outputs a log likelihood ratio (LLR) of the output bits, for ensuring the LDPC decoding performance.
  • LLR log likelihood ratio
  • the SOVA decoder may be used as the example of FIG. 29 or a trellis decoder of a hard decision method may be used in consideration of complexity.
  • FIG. 30 is a block diagram showing an example of the FEC decoder.
  • the FEC decoder of FIG. 30 can decode the SCCC turbo code generated by the embodiment of FIG. 2.
  • the FEC decoder includes a second maximum a posteriori (MAP) decoder 1902, a first operator 1904, a deinterleaver 1906, a first MAP decoder 1908, a second operator 1912 and a decision unit 1914.
  • MAP maximum a posteriori
  • a soft output iterative decoding method may be used and an MAP algorithm may be used as a decoding algorithm using the soft output iterative decoding method.
  • the first MAP decoder 1908 and the second MAP decoder 1902 of FIG. 30 are soft- in soft-out decoders which receive reliability information of an input symbol of the encoder and reliability information of an output symbol and output the respective reliability information which can be estimated at the output side, respectively.
  • the first MAP decoder 1908 and the second MAP decoder 1902 respectively correspond to the first convolution encoder 102 and the second convolution encoder 106 of FIG. 2, and decode the data in the manner inverse to the encoding method of the first convolution encoder 102 and the second convolution encoder 106 and output the decoded data.
  • the first MAP decoder 1908 receives and decodes the data output from the second deinterleaver 1580 and the data output from the interleaver 1912 according to the MAP algorithm and outputs the decoded data.
  • the first operator 1904 subtracts the data output from the interleaver 1912 from the data output from the first MAP decoder 1908 and outputs the subtracted data to the deinterleaver 1906.
  • the deinterleaver 1906 deinterleaves input data, mixes the input data, and outputs the data to the first MAP decoder 1908 and the second operator 1910.
  • the second operator 1910 subtracts the data output from the deinterleaver 1906 from the data output from the first MAP decoder 1908 and feeds back the subtracted data to the interleaver 1912.
  • the first MAP decoder 1908 decodes the input data according to the MAP algorithm and outputs the decoded data to the decision unit 1914.
  • the decision unit 1914 obtains a decision value of the symbol input to the decision unit 1914 with respect to a final reliability value and outputs the decision value.
  • FIG. 31 is a block diagram showing another example of the FEC decoder.
  • the FEC decoder of FIG. 31 can decode the PCCC turbo code of FIG. 3.
  • the FEC decoder includes a serial/parallel converter 1901, a fourth MAP decoder 1903, a third operator 1905, a deinterleaver 1907, a third MAP decoder 1909, a fourth operator 1911, an interleaver 1913 and a decision unit 1915.
  • the FEC decoder of FIG. 31 operates similarly to the FEC decoder of FIG. 30. Unlike the FEC decoder of FIG. 30, in the FEC decoder of FIG. 31, the third MAP decoder 1909 may receive the data output from the second deinterleaver 1580 via the serial/parallel converter 1901 and decode the received data according to the MAP algorithm. Accordingly, the reliability values which are transmitted in parallel according to the characteristics of the PCCC method can be calculated.
  • the serial/parallel converter 1901 selects the data output from the second dein- terleaver 1580 in the manner inverse to the method selected by the parallel/serial converter 107 of FIG. 3 and outputs the data to the fourth MAP decoder 1903 and the third MAP decoder 1909.
  • FIG. 32 is a block diagram of another embodiment of the apparatus for receiving the signal. Hereinafter, for convenience of description, it is assumed that the number of reception paths is two.
  • the embodiment of FIG. 32 includes a first receiver 2000, a second receiver 2005, a first synchronizer 2010, a second synchronizer 2015, a first demodulator 2020, a second demodulator 2015, a first frame parser 2030, a second parser 2035, a multi- input/output decoder 2040, a third deinterleaver 2050, a linear pre-coding decoder 2060, a trellis coded modulation decoder 2070, a fourth deinterleaver 2080, and a FEC decoder 2090.
  • the first receiver 2000 and the second receiver 2005 receive respective RF signals, down-converts the frequency bands, converts the signals into digital signals, and outputs the converted digital signals.
  • the first synchronizer 2010 and the second synchronizer 2015 acquire synchronizations of the received signals output from the first receiver 2000 and the second receiver 2005 in a frequency domain and a time domain and outputs the synchronizations.
  • the first synchronizer 2010 and the second synchronizer 2015 may use an offset result of the data output from the first demodulator 2020 and the second demodulator 2025 in the frequency domain, for acquiring the synchronizations of the signals in the frequency domain.
  • the first demodulator 2020 demodulates the received data output from the first synchronizer 2010 .
  • the first demodulator 2020 converts the received data into the frequency domain and decodes the data values dispersed into the subcarriers to values allocated to the subcarriers.
  • the second modulatoer 2025 demodulates the received data output from the second synchronizer 2015.
  • the first frame parser 2030 and the second frame parser 2035 may distinguish between the reception paths according to the frame structures of the signals demodulated by the first demodulator 2020 and the second demodulator 2025 and output the symbol data of the data symbol interval excluding the pilot symbol.
  • the multi-input/output decoder 2040 receives the data output from the first frame parser 2030 and the second parser 2035 and decodes the received data streams such that one data stream is output.
  • the signal processing procedure of the linear pre-coding decoder 2060, the trellis coded modulation decoder 2070, the fourth deinterleaver 2080 and the FEC decoder 2090 is equal to that of the corresponding components shown in FIG. 23.
  • FIG. 33 is a view showing an example of a decoding method of the multi- input/output decoder. That is, FIG. 33 shows a decoding example of the receiver when the transmitter multi-input/output encodes data by the STBC method and transmits the encoded data.
  • the transmitter may use two transmission antennas. This is only exemplary and another multi-input/output method may be applied.
  • r(k), h(k), s(k) and n(k) represent a symbol received bythe receiver, a channel response, a symbol value transmitted by the transmitter, and channel noise, respectively.
  • Subscripts s, i, 0 and 1 represent a s transmission symbol, an i reception antenna, 0 transmission antenna and 1 st transmission antenna, respectively.
  • h (k) represents a response of a channel experienced by the transmitted symbol when a sthsymbol transmitted via the first transmission antenna is received by the i reception antenna
  • r (k) represents a s+1 reception symbol received by the i reception antenna.
  • r (k) which is a s reception symbol received by the i reception antenna becomes a value obtained by adding the s symbol value transmitted from the 0 transmission antenna to the i reception antenna via the channel, the s symbol value transmitted from the 1 st transmission antenna to the i reception antenna via the channel and a sum n (k) of the channel noises of the channels.
  • FIG. 34 shows a detailed example of the received symbol of FIG. 33.
  • FIG. 34 shows an example of decoding the data which is multi-input/output encoded and transmitted by the STBC method and shows the equation which can obtain the received symbol in the case where the data is transmitted using two transmission antennas and the data transmitted via the two antennas is received via one antenna.
  • the number of transmission channels may be two.
  • h and s respectively denote a transmission channel response from the ⁇ ' transmission antenna to the reception antenna and a symbol transmitted by the 0 transmission antenna
  • h and s respectively denote a transmission channel response from the 1 st transmission antenna to the reception antenna and a symbol transmitted by the 1 st transmission antenna.
  • “*" denotes the complex conjugate
  • s ' and s ' denote the restored symbols.
  • r and r respectively denote a symbol received by the reception antenna at a time t and a symbol received by the reception antena at a time t+T after the elapse of a transmission period T, and n and n denote the values including the channel noises of the transmission paths at reception times.
  • the signals r and r received by the reception antenna may be expressed by the values obtained by adding the values obtained when the signals transmitted from the transmission antennas are distorted by the transmission channels.
  • the restored symbols s ' and s ' are calculated using the received signals r
  • FIG. 35 is a schematic block diagram showing another example of the apparatus for transmitting the signal.
  • FIG. 36 shows the embodiment of the apparatus for receiving the signal transmitted by the apparatus for transmitting the signal shown in FIG. 35.
  • FIGs. 35 and 36 show the examples to which a SISO system is applied.
  • the embodiment of the apparatus for transmitting the signal of FIG. 35 includes a FEC encoder 2300, a first interleaver 2310, a trellis coded modulator 2320, a linear pre-coder 2330, a second interleaver 2340, a frame builder 2350, a modulator 2360 and a transmitter 2370.
  • the description of the components may refer to the description of FIGs. 1 and 22. That is, in the embodiment of FIG. 32, the signal processing similar to the embodiments described with reference to FIGs. 1 and 22 is performed.
  • the apparatus for transmitting the signal of FiG. 35 processes the signal according to the SISO method without including the multi-input/output encoder.
  • the symbol data which is linearly pre-coded and interleaved so as to be robust against the frequency-selective fading of the channel is input to the frame builder 2350.
  • the frame builder 2350 builds a data interval including no pilot carrier and a pilot symbol interval including the pilot carrier using the input symbol data and outputs the data interval and the pilot symbol interval as shown in FIG. 11.
  • the transmission paths do not need to be distinguished unlike the multi- input/output method shown in FIGs. 21 and 22.
  • FIG. 36 shows the embodiment of the apparatus for receiving the signal and includes a receiver 2400, a synchronizer 2410, a demodulator 2420, a frame parser 2430, a first deinterleaver 2440, a linear pre-coding decoder 2450, a trellis coded modulation decoder 2460, a second deinterleaver 2470 and a FEC decoder 2480.
  • the embodiment of the apparatus for receiving the signal of FIG. 36 may refer to the description of FIGs. 23 and 32. However, the apparatus for receiving the signal of FIG. 36 processes the SISO signal and thus does not include the multi-input/output decoder.
  • the symbol data parsed by the frame parser 2430 is output to the first deinterleaver 2440 such that the procedure inverse to the procedure of processing the data so as to be robust against the frequency- selective fading of the channel by the transmitting apparatus is performed.
  • FIG. 37 is a flowchart illustrating an embodiment of a method of transmitting a signal.
  • Input data is FEC-encoded such that a receiving apparatus finds and corrects a transmission error (S2500).
  • the FEC encoding method may use a turbo code.
  • the encoded data is interleaved so as to be robust against a burst error of a transmission channel and the interleaved data is converted into encoded symbol data according to a transmission/reception system (S2502).
  • a trellis coded modulation encoding method may be used for conversion into the encoded symbol data.
  • a symbol mapping method may vary according to modulation schemes such as QAM and QPSK.
  • the mapped symbol data is pre-coded so as to be dispersed into several output symbols in the frequency domain (S2504), and the pre-coded symbol data is interleaved (S2506).
  • a probability that all information is lost by the fading when experiencing the frequency-selective fading channel is reduced, and the dispersed symbol data is not subjected to the same frequency-selective fading.
  • a convolution interleaver or a block interleaver may be used, which can be selected according to the implementation examples.
  • the interleaved symbol data is multi-input/output encoded so as to be transmitted via a plurality of antennas (S2508).
  • the number of antennas may become the number of data transmission paths.
  • data having the same information is transmitted via the paths and, in the spatial multiplexing method, different data is transmitted via the paths.
  • the encoded data is converted into a transmission frame according to the number of multi-input/output transmission paths and the converted frame is modulated and transmitted (S2510).
  • the transmission frame includes a pilot carrier symbol interval and a data symbol interval.
  • the pilot carrier symbol interval may have a structure which can distinguish between the transmission paths.
  • step S2508 of multi-input/output encoding the symbol is not performed and the transmission paths do not need to be dis- tinguished.
  • FIG. 38 is a flowchart illustrating an embodiment of a method of receiving a signal.
  • the apparatus for receiving the signal receives, synchronizes and demodulates the signal transmitted by the transmitting apparatus according to the transmission paths (S2600).
  • the demodulated data frame is parsed and is decoded by the method corresponding to the multi-input/output encoding method so as to obtain a symbol data stream (S2602).
  • the symbol data stream is deinterleaved in the manner inverse to the interleaving method of the apparatus for transmitting the signal (S2604), and the data stream restored by the deinterleaving step is decoded in the manner inverse to the pre-coding method such that original symbol data dispersed into several symbol data in the frequency domain is restored (S2606).
  • the restored encoded symbol data is decoded and is demapped and the demapped bit data is deinterleaved and restored to the original order (S2608).
  • a trellis coded modulation decoding method may be used.
  • the equalization may be performed at a symbol level and an equalization location may vary at the symbol level according to implementation examples.
  • the restored symbol data is demapped and restored to the bit data and the bit data is deinterleaved and restored to the original order (S2608).
  • the restored data is FEC-encoded and a transmission error is found and corrected (S2610).
  • a turbo code may be used for FEC encoding.
  • step S2602 of multi-input/output decoding the symbol is not performed and the transmission paths do not need to be distinguished.
  • the method of transmitting/receiving the signal and the apparatus for transmitting/ receiving the signal are not limited to the above examples and are applicable to all signal transmission/reception systems for broadcast or communication. Mode for the Invention
  • a method of transmitting/receiving a signal and an apparatus for transmitting/ receiving a signal of the present invention can be used in broadcast and communication fields.

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  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

L'invention concerne un procédé et un appareil d'émission/réception d'un signal capables d'augmenter la vitesse de transfert de données par la combinaison d'un procédé de codage de correction d'erreurs sans circuit de retour et d'un procédé de concordance de symboles. Il est possible d'augmenter la vitesse de transfert de données et d'estimer un canal de transmission présentant des caractéristiques de défilement du temps de propagation long de façon à augmenter la distance de transmission du signal.
PCT/KR2008/002218 2007-04-19 2008-04-18 Procédé et un appareil d'émission et de réception d'un signal WO2008130160A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2007-0038307 2007-04-19
KR1020070038307A KR20080094193A (ko) 2007-04-19 2007-04-19 신호 송수신 방법 및 신호 송수신 장치

Publications (1)

Publication Number Publication Date
WO2008130160A1 true WO2008130160A1 (fr) 2008-10-30

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Application Number Title Priority Date Filing Date
PCT/KR2008/002218 WO2008130160A1 (fr) 2007-04-19 2008-04-18 Procédé et un appareil d'émission et de réception d'un signal

Country Status (2)

Country Link
KR (1) KR20080094193A (fr)
WO (1) WO2008130160A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8230313B2 (en) 2008-08-11 2012-07-24 Texas Instruments Incorporated Low-power predecoding based viterbi decoding

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040035297A (ko) * 2002-10-19 2004-04-29 삼성전자주식회사 복합적 오류정정 부호화 기능을 갖는 디지털방송 시스템의전송장치 및 방법
US20070076829A1 (en) * 2005-10-05 2007-04-05 Lg Electronics Inc. Digital television transmitter and method of coding data in digital television transmitter
US20070076584A1 (en) * 2005-10-05 2007-04-05 Kim Jin P Method of processing traffic information and digital broadcast system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040035297A (ko) * 2002-10-19 2004-04-29 삼성전자주식회사 복합적 오류정정 부호화 기능을 갖는 디지털방송 시스템의전송장치 및 방법
US20070076829A1 (en) * 2005-10-05 2007-04-05 Lg Electronics Inc. Digital television transmitter and method of coding data in digital television transmitter
US20070076584A1 (en) * 2005-10-05 2007-04-05 Kim Jin P Method of processing traffic information and digital broadcast system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8230313B2 (en) 2008-08-11 2012-07-24 Texas Instruments Incorporated Low-power predecoding based viterbi decoding

Also Published As

Publication number Publication date
KR20080094193A (ko) 2008-10-23

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