WO2008126239A1 - 半導体集積回路及びクロック制御方法 - Google Patents

半導体集積回路及びクロック制御方法 Download PDF

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Publication number
WO2008126239A1
WO2008126239A1 PCT/JP2007/057056 JP2007057056W WO2008126239A1 WO 2008126239 A1 WO2008126239 A1 WO 2008126239A1 JP 2007057056 W JP2007057056 W JP 2007057056W WO 2008126239 A1 WO2008126239 A1 WO 2008126239A1
Authority
WO
WIPO (PCT)
Prior art keywords
clocks
external
oscillation circuit
integrated circuit
control method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/057056
Other languages
English (en)
French (fr)
Inventor
Norihiko Miki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Fujitsu Electronics Inc
Original Assignee
Fujitsu Semiconductor Ltd
Fujitsu Electronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd, Fujitsu Electronics Inc filed Critical Fujitsu Semiconductor Ltd
Priority to PCT/JP2007/057056 priority Critical patent/WO2008126239A1/ja
Publication of WO2008126239A1 publication Critical patent/WO2008126239A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Oscillators With Electromechanical Resonators (AREA)

Abstract

　消費電力を抑える。 　外部発振回路の生成する外部クロック（１１）は、低速ＲＣ発振回路（１３）の生成する低速ＲＣクロックによって動作する外部クロック監視部（１４）によって監視される。制御回路（１６）は、外部クロック監視部（１４）によって外部クロック（１１）の入力が確認されるときは、動作クロック選択部（１５）に指示して外部クロック（１１）を選択させる。これにより、外部クロック（１１）が動作クロックとして用いられる。外部クロック監視部（１４）によって、外部クロック（１１）の入力が停止したことが検出されると、ＲＣ発振回路（１２）は、動作を開始し、制御回路（１６）は、動作クロック選択部（１５）に指示してＲＣ発振回路（１２）の出力を選択させる。これにより、動作クロックが、ＲＣ発振回路（１２）の生成するＲＣクロックに切り替わる。
PCT/JP2007/057056 2007-03-30 2007-03-30 半導体集積回路及びクロック制御方法 Ceased WO2008126239A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/057056 WO2008126239A1 (ja) 2007-03-30 2007-03-30 半導体集積回路及びクロック制御方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/057056 WO2008126239A1 (ja) 2007-03-30 2007-03-30 半導体集積回路及びクロック制御方法

Publications (1)

Publication Number Publication Date
WO2008126239A1 true WO2008126239A1 (ja) 2008-10-23

Family

ID=39863420

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/057056 Ceased WO2008126239A1 (ja) 2007-03-30 2007-03-30 半導体集積回路及びクロック制御方法

Country Status (1)

Country Link
WO (1) WO2008126239A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020071604A (ja) * 2018-10-30 2020-05-07 株式会社日立製作所 クロック生成回路、半導体集積回路、及び、同半導体集積回路を備えた装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0370314A (ja) * 1989-08-10 1991-03-26 Fujitsu Ltd クロック断検出回路
JPH04365110A (ja) * 1991-06-13 1992-12-17 Nec Corp クロック停止回路

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0370314A (ja) * 1989-08-10 1991-03-26 Fujitsu Ltd クロック断検出回路
JPH04365110A (ja) * 1991-06-13 1992-12-17 Nec Corp クロック停止回路

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020071604A (ja) * 2018-10-30 2020-05-07 株式会社日立製作所 クロック生成回路、半導体集積回路、及び、同半導体集積回路を備えた装置
JP7173833B2 (ja) 2018-10-30 2022-11-16 株式会社日立製作所 半導体集積回路、及び、同半導体集積回路を備えた装置

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