WO2008120369A1 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
WO2008120369A1
WO2008120369A1 PCT/JP2007/056921 JP2007056921W WO2008120369A1 WO 2008120369 A1 WO2008120369 A1 WO 2008120369A1 JP 2007056921 W JP2007056921 W JP 2007056921W WO 2008120369 A1 WO2008120369 A1 WO 2008120369A1
Authority
WO
WIPO (PCT)
Prior art keywords
insulating film
semiconductor device
interlayer insulating
manufacturing
same
Prior art date
Application number
PCT/JP2007/056921
Other languages
English (en)
French (fr)
Inventor
Hiroshi Kudo
Michio Oryoji
Original Assignee
Fujitsu Microelectronics Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Microelectronics Limited filed Critical Fujitsu Microelectronics Limited
Priority to PCT/JP2007/056921 priority Critical patent/WO2008120369A1/ja
Publication of WO2008120369A1 publication Critical patent/WO2008120369A1/ja

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

　半導体装置は、第１の層間絶縁膜と、前記第１の層間絶縁膜上に形成されたＳｉ，Ｏ，Ｃ，Ｈを基本構造として含む炭素含有無機絶縁膜（２３）で構成される第２の層間絶縁膜と、を有し、前記第１の層間絶縁膜は、前記第２の層間絶縁膜との界面に、Ｃ，Ｈ，Ｏを基本構造として含む炭化水素系の有機絶縁膜（２２）を有する。
PCT/JP2007/056921 2007-03-29 2007-03-29 半導体装置およびその製造方法 WO2008120369A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/056921 WO2008120369A1 (ja) 2007-03-29 2007-03-29 半導体装置およびその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/056921 WO2008120369A1 (ja) 2007-03-29 2007-03-29 半導体装置およびその製造方法

Publications (1)

Publication Number Publication Date
WO2008120369A1 true WO2008120369A1 (ja) 2008-10-09

Family

ID=39807962

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/056921 WO2008120369A1 (ja) 2007-03-29 2007-03-29 半導体装置およびその製造方法

Country Status (1)

Country Link
WO (1) WO2008120369A1 (ja)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000294633A (ja) * 1999-04-07 2000-10-20 Sony Corp 半導体装置およびその製造方法
JP2003243501A (ja) * 2002-02-22 2003-08-29 Sony Corp 半導体装置の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000294633A (ja) * 1999-04-07 2000-10-20 Sony Corp 半導体装置およびその製造方法
JP2003243501A (ja) * 2002-02-22 2003-08-29 Sony Corp 半導体装置の製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
STANDAERT T.E.F.M. ET AL.: "Etching of xerogel in high-density fluorocarbon plasmas", JOURNAL OF VACUUM SCIENCE & TECHNOLOGY A: VACUUM SURFACES, AND FILMS, vol. 18, no. 6, 2000, pages 2742 - 2748, XP012005373 *

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