WO2008120342A1 - 電子機器およびプリント基板ユニット - Google Patents

電子機器およびプリント基板ユニット Download PDF

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Publication number
WO2008120342A1
WO2008120342A1 PCT/JP2007/056802 JP2007056802W WO2008120342A1 WO 2008120342 A1 WO2008120342 A1 WO 2008120342A1 JP 2007056802 W JP2007056802 W JP 2007056802W WO 2008120342 A1 WO2008120342 A1 WO 2008120342A1
Authority
WO
WIPO (PCT)
Prior art keywords
terminal
electronic part
signal
transmitted
electronic device
Prior art date
Application number
PCT/JP2007/056802
Other languages
English (en)
French (fr)
Inventor
Rikizo Nakano
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2007/056802 priority Critical patent/WO2008120342A1/ja
Publication of WO2008120342A1 publication Critical patent/WO2008120342A1/ja

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/117—Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09254—Branched layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/0949—Pad close to a hole, not surrounding the hole
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/0979—Redundant conductors or connections, i.e. more than one current path between two points
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1572—Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Endoscopes (AREA)

Abstract

　第１電子部品（２３）および第２電子部品（２２）の間で信号がやり取りされる。例えば第１電子部品（２３）から第２電子部品（２２）に向かって信号が伝送される。第１電子部品（２３）から出力される信号は第１単線配線パターン（２９ａ）から第１複線配線パターン（２９ｂ）に伝送される。信号は第１端子（２５）から第２端子（２７）を介して第２複線配線パターン（２８ｂ）に出力される。その後、信号は第１単線配線パターン（２８ａ）を介して第２電子部品（２２）に伝送される。こうして信号は２組の第１端子（２５）および第２端子（２７）を介して並列に伝送される。たとえ一方の第１端子（２５）および第２端子（２７）の間で接触不良が発生しても、他方の第１端子（２５）および第２端子（２７）に基づき信号の伝送は継続される。電子機器（１１）では致命的なエラーの発生は抑制される。
PCT/JP2007/056802 2007-03-29 2007-03-29 電子機器およびプリント基板ユニット WO2008120342A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/056802 WO2008120342A1 (ja) 2007-03-29 2007-03-29 電子機器およびプリント基板ユニット

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/056802 WO2008120342A1 (ja) 2007-03-29 2007-03-29 電子機器およびプリント基板ユニット

Publications (1)

Publication Number Publication Date
WO2008120342A1 true WO2008120342A1 (ja) 2008-10-09

Family

ID=39807935

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/056802 WO2008120342A1 (ja) 2007-03-29 2007-03-29 電子機器およびプリント基板ユニット

Country Status (1)

Country Link
WO (1) WO2008120342A1 (ja)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0536455A (ja) * 1991-07-31 1993-02-12 Fujitsu Ten Ltd 電子回路基板のコネクタ接続機構
JP2002324959A (ja) * 2001-04-24 2002-11-08 Furukawa Electric Co Ltd:The 基板の端子接続構造
JP2004152131A (ja) * 2002-10-31 2004-05-27 Elpida Memory Inc メモリモジュール、メモリチップ、及びメモリシステム

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0536455A (ja) * 1991-07-31 1993-02-12 Fujitsu Ten Ltd 電子回路基板のコネクタ接続機構
JP2002324959A (ja) * 2001-04-24 2002-11-08 Furukawa Electric Co Ltd:The 基板の端子接続構造
JP2004152131A (ja) * 2002-10-31 2004-05-27 Elpida Memory Inc メモリモジュール、メモリチップ、及びメモリシステム

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