WO2008120323A1 - 半導体装置の製造方法および配線層形成システム - Google Patents

半導体装置の製造方法および配線層形成システム Download PDF

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Publication number
WO2008120323A1
WO2008120323A1 PCT/JP2007/056689 JP2007056689W WO2008120323A1 WO 2008120323 A1 WO2008120323 A1 WO 2008120323A1 JP 2007056689 W JP2007056689 W JP 2007056689W WO 2008120323 A1 WO2008120323 A1 WO 2008120323A1
Authority
WO
WIPO (PCT)
Prior art keywords
film
coating film
removal
wiring layer
generated
Prior art date
Application number
PCT/JP2007/056689
Other languages
English (en)
French (fr)
Inventor
Manabu Sakamoto
Naoki Idani
Toshiyuki Karasawa
Toshiyuki Isome
Ade Asneil Akbar
Tetsuya Shirasu
Fumihiko Akaboshi
Satoshi Takesako
Tsuyoshi Kanki
Original Assignee
Fujitsu Microelectronics Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Microelectronics Limited filed Critical Fujitsu Microelectronics Limited
Priority to PCT/JP2007/056689 priority Critical patent/WO2008120323A1/ja
Publication of WO2008120323A1 publication Critical patent/WO2008120323A1/ja

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

　層間絶縁膜に低誘電率膜を用いた場合におけるＣＭＰ工程での低誘電率膜の剥離を抑制する。 　基板上に低誘電率の塗布膜を形成し（ステップＳ１）、基板面内の研磨レートの分布を用いてその塗布膜を基板エッジから除去する幅を設定し、その幅を用いてその塗布膜を部分的に除去する（ステップＳ２）。その際は、研磨レートの極小値に対応する位置に、その除去後の塗布膜のエッジがくるように、除去幅を設定する。そして、その除去後の塗布膜のエッジを覆って絶縁膜を形成した後（ステップＳ３）、開口部形成と導電膜形成を経て（ステップＳ５，Ｓ６）、その導電膜をその絶縁膜まで研磨する（ステップＳ７）。これにより、導電膜の研磨時に、塗布膜の剥離が抑制され、信頼性の高い配線層が形成可能になる。
PCT/JP2007/056689 2007-03-28 2007-03-28 半導体装置の製造方法および配線層形成システム WO2008120323A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/056689 WO2008120323A1 (ja) 2007-03-28 2007-03-28 半導体装置の製造方法および配線層形成システム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/056689 WO2008120323A1 (ja) 2007-03-28 2007-03-28 半導体装置の製造方法および配線層形成システム

Publications (1)

Publication Number Publication Date
WO2008120323A1 true WO2008120323A1 (ja) 2008-10-09

Family

ID=39807916

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/056689 WO2008120323A1 (ja) 2007-03-28 2007-03-28 半導体装置の製造方法および配線層形成システム

Country Status (1)

Country Link
WO (1) WO2008120323A1 (ja)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10230455A (ja) * 1997-02-17 1998-09-02 Nec Corp 研磨装置
JPH11114806A (ja) * 1997-08-11 1999-04-27 Tokyo Seimitsu Co Ltd ウェーハ研磨装置
JP2001077113A (ja) * 1999-09-02 2001-03-23 Nec Corp 銅配線の形成方法および銅配線の形成された半導体ウエハ
JP2005217320A (ja) * 2004-01-30 2005-08-11 Renesas Technology Corp 配線形成方法、半導体装置の製造方法並びに半導体実装装置の製造方法
JP2005217319A (ja) * 2004-01-30 2005-08-11 Renesas Technology Corp 多層配線構造、半導体装置及び半導体実装装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10230455A (ja) * 1997-02-17 1998-09-02 Nec Corp 研磨装置
JPH11114806A (ja) * 1997-08-11 1999-04-27 Tokyo Seimitsu Co Ltd ウェーハ研磨装置
JP2001077113A (ja) * 1999-09-02 2001-03-23 Nec Corp 銅配線の形成方法および銅配線の形成された半導体ウエハ
JP2005217320A (ja) * 2004-01-30 2005-08-11 Renesas Technology Corp 配線形成方法、半導体装置の製造方法並びに半導体実装装置の製造方法
JP2005217319A (ja) * 2004-01-30 2005-08-11 Renesas Technology Corp 多層配線構造、半導体装置及び半導体実装装置

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