WO2008119221A1 - Procédé d'échange de paquets de données, dispositif et carte de circuits imprimés - Google Patents

Procédé d'échange de paquets de données, dispositif et carte de circuits imprimés Download PDF

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Publication number
WO2008119221A1
WO2008119221A1 PCT/CN2007/070413 CN2007070413W WO2008119221A1 WO 2008119221 A1 WO2008119221 A1 WO 2008119221A1 CN 2007070413 W CN2007070413 W CN 2007070413W WO 2008119221 A1 WO2008119221 A1 WO 2008119221A1
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WO
WIPO (PCT)
Prior art keywords
pcie
line card
switching device
data packet
unit
Prior art date
Application number
PCT/CN2007/070413
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English (en)
Chinese (zh)
Inventor
Wu Yang
Original Assignee
Hangzhou H3C Technologies Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN2007100909940A external-priority patent/CN101277196B/zh
Priority claimed from CN2007100909936A external-priority patent/CN101277195B/zh
Application filed by Hangzhou H3C Technologies Co., Ltd. filed Critical Hangzhou H3C Technologies Co., Ltd.
Publication of WO2008119221A1 publication Critical patent/WO2008119221A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Definitions

  • the present invention relates to network communication technologies, and in particular, to a data message exchange method, a device, and a line card board. Background of the invention
  • the performance requirements of packet switching devices such as routers, switches, and gateways are getting higher and higher, and the services that need to be processed are more and more complicated. Therefore, in the current packet switching device, the data channel and the control channel are separated, and the packet switching device can adopt the distributed data packet forwarding mode.
  • FIG. 1 is a schematic structural diagram of the inside of a message exchange device in the prior art.
  • the packet switching device includes a main control board, a switch, and a plurality of line card boards.
  • the dotted arrow is the control channel, and the control channel uses the point-to-point method to complete the exchange of control messages between the main control board and each line card.
  • the solid arrow is the data channel, and the main control board and each line card are exchanged.
  • the device exchanges data packets.
  • the switch on which the main control board and each line card exchange data packets is usually implemented by using an Ethernet switch chip. Because the Ethernet switch chip completes the data packet exchange according to the lookup table, the data packet transmission delay is large. In the case of large data traffic, congestion and packet loss will inevitably occur, and the Ethernet switch chip is not good. Supports QoS (Quality of Service) and flow control, which greatly reduces the reliability and performance of data packet exchange. Summary of the invention
  • a packet switching device includes: a main control board, a PCIE switching device, and at least two line card boards, where
  • the main control board is configured to allocate a corresponding PCIE address space for each line card board; each line card board is configured to send data packets to the PCIE switching device, or receive data packets sent by the PCIE switching device;
  • the PCIE switching device is configured to receive and send data packets according to the PCIE address space corresponding to each line card.
  • a line card board comprising:
  • control unit configured to receive and process a data packet sent by the PCIE interface adaptation unit, and send the data packet to the PCIE interface adaptation unit;
  • the PCIE interface adaptation unit is configured to send a data packet sent by the external PCIE switching device to the control unit, and send the data packet sent by the control unit to the external PCIE switching device.
  • a data packet exchange method the PCIE switching device is set, the method further includes: the main control board allocates a corresponding PCIE address space for each line card board; the source line card board sends the data packet to the PCIE switching device; the PCIE exchange The device sends the data packet to the target line card according to the PCIE address space corresponding to each line card.
  • the PCIE switching device is used to complete the exchange of data packets between the line card boards, because the PCIE switching device does not need to perform the Ethernet switch chip lookup table, the step-by-step transmission, and the encapsulation and solution in the prior art.
  • the process of encapsulation therefore, can greatly reduce the transmission delay of commands and data, can reduce congestion, and can also support QoS (Quality of Service), flow control, etc., thereby realizing data packet delivery. High performance and high reliability.
  • the PCIE switching device is inexpensive, the cost of the device is saved, and the large-scale implementation of the service is easy.
  • FIG. 1 is a schematic structural diagram of the inside of a message exchange device in the prior art.
  • Figure 2 is a block diagram showing the basic structure of a message exchange device in an embodiment of the present invention.
  • Figure 3 is a schematic diagram showing an optimized structure inside a message exchange device in an embodiment of the present invention.
  • FIG. 4 is a schematic view showing the internal structure of a main control board in one embodiment of the present invention.
  • Figure 5 is a first structural view showing the inside of a line card in one embodiment of the present invention.
  • Figure 6 is a schematic view showing the second structure inside the line card in one embodiment of the present invention.
  • Figure 7 is a schematic view showing the overall structure of the inside of the line card board in one embodiment of the present invention.
  • FIG. 8 is a schematic diagram of an optimized structure inside an uplink adaptation unit and a downlink adaptation unit in an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of message conversion in an embodiment of the present invention.
  • Figure 10 is a diagram showing the format of a data message transmitted by a control unit of a line card board in an embodiment of the present invention.
  • Figure 11 is a diagram showing a preferred configuration of the inside of a PCIE switching device in one embodiment of the present invention.
  • Figure 12 is a diagram showing the entry of different sources of messages into different queues in one embodiment of the present invention.
  • FIG. 13 is a schematic diagram of a data packet format of a PCIE protocol in an embodiment of the present invention.
  • Figure 14 is a flow diagram of data message exchange in a preferred embodiment of the present invention. Mode for carrying out the invention
  • PCI Express (PCIE) protocol can only integrate multiple channels, and has multiple levels of service quality and information processing and congestion avoidance mechanism.
  • PCIE protocol can only integrate multiple channels, and has multiple levels of service quality and information processing and congestion avoidance mechanism.
  • PCIE protocol packets only need to exchange according to PCIE address space. There is no need to perform lookup table, step-by-step transmission, and encapsulation and decapsulation in Ethernet. Therefore, the transmission delay of commands and data can be greatly reduced, data congestion can be avoided, QoS can be supported, and data packet exchange can be realized. Reliability and high performance.
  • FIG. 2 is a schematic diagram showing the basic structure of a message exchange device in an embodiment of the present invention.
  • a message exchange device implemented by the PCIE protocol mainly includes: a main control board, a PCIE switching device, and at least two line card boards, and the main control board is connected to the PCIE switching device through a PCIE interface.
  • Each line card board is also connected to the PCIE switching device through the PCIE interface, so that on the data plane, the main control board and each line card board are connected by a PCIE switching device, and
  • the main control board is configured to allocate a corresponding PCIE address space for each line card board; each line card board is configured to send data packets to the PCIE switching device, or receive data packets sent by the PCIE switching device;
  • the PCIE switching device is configured to receive and send data packets according to the PCIE address space corresponding to each line card.
  • the data plane of the packet switching device identifies the line card board by using the PCIE address space, so that the PCIE switching device can accurately exchange data packets between the online card boards.
  • the bearer mode of the control plane may be any one of the prior art, and preferably, the Ethernet switching device implemented by an embodiment of the present invention may also be used.
  • FIG. 3 is a schematic diagram of an optimized structure inside a message exchange device in an embodiment of the present invention.
  • the packet switching device may further include: an Ethernet switching device, and the main control board passes through an Ethernet interface. Connected to the Ethernet switching device, each line card board is also connected to the Ethernet switching device through the Ethernet interface. Thus, on the control plane, the main control board and each line card board are connected together through an Ethernet switching device.
  • the main control board and each line card board are connected together through an Ethernet switching device.
  • the main control board is further configured to send a control packet of each line card to the Ethernet switching device, where the Ethernet switching device is configured to send control messages of each line card to each line. Card board.
  • the main control board sends a control message through a control plane formed by the Ethernet switching device, thereby completing the configuration of the routing information of the line card board. And the maintenance and management functions of the routing and forwarding table, without forwarding data packets. In this way, the bandwidth required for the Ethernet switching device is relatively small.
  • the high-end packet switching device can be implemented by using a Gigabit Ethernet switching device. Of course, a Fast Ethernet switching device or a 10 Gigabit Ethernet switching device can also be used. achieve.
  • each line card directly exchanges data packets through the data plane formed by the PCIE switching device, without passing through the main control board.
  • the packet switching device shown in FIG. 3 can further implement mutual backup of the data plane bearer and the control plane bearer, thereby ensuring the data plane of the packet switching device when an abnormality occurs in the data plane bearer and the control plane bearer.
  • the control plane is still working.
  • the packet switching device when the data plane bearer is used to bear the control plane
  • the packet switching device further includes a fault detecting unit 1 and a switching unit 1 therein, where
  • the fault detection unit 1 is configured to detect whether a fault occurs in the control plane bearer, that is, whether the Ethernet connection between the Ethernet switching device and each line card board fails, and if yes, send an Ethernet connection failure notification to Switching unit 1;
  • the switching unit 1 is configured to send a control bearer switching indication to the PCIE switching device after receiving the Ethernet connection failure notification;
  • the PCIE switching device is further configured to: after receiving the control bearer switching indication, receive the control packet sent by the main control board to each line card, according to the PCIE address space corresponding to each line card board.
  • the control packet is sent to each line card board, so that when the control plane bearer fails, the data plane bearer formed by the PCIE switching device further forwards the forwarding of the control plane bearer.
  • the data plane service is prevented from being congested by the control plane service.
  • the traffic of the data plane can be restricted.
  • the packet switching device When the data plane bearer is backed up by the control plane bearer, the packet switching device further includes a fault detecting unit 2 and a switching unit 2, where
  • the fault detection unit 2 is configured to detect whether the data plane bearer is faulty, that is, whether the PCIE connection between the PCIE switching device and each line card board fails, and if yes, send a PCIE connection failure notification to the switching unit 2 ;
  • the switching unit 2 is configured to send a data bearer switching indication to the Ethernet switching device after receiving the PCIE connection failure notification;
  • the above-described failure detecting unit 1 and switching unit 1 may be provided inside the Ethernet switching device or independently of the Ethernet switching device.
  • the above-described fault detecting unit 2 and switching unit 2 may be provided inside the PCIE switching device or independently of the PCIE switching device.
  • the backup main control board can be added.
  • the backup main control board can assume the task of the main control board.
  • the PCIE switching device can provide multiple independent PCIE serial buses. These independent serial buses can be independently become one PCIE line, or multiple lines can be bundled on one logical serial line, each line card board. Need to connect to the PCIE switch through a logical serial line.
  • a 1-channel PCIE switching device can support 2.5 Gbps
  • a 4-channel PCIE switching device can support 10 Gbps
  • a 16-channel PCIE switching device can support 40 Gbps bandwidth
  • a channel PCIE switch can support 5Gbps
  • a 4-channel PCIE switch can support 20Gbps bandwidth.
  • the logical serial line can be designed according to user requirements. Therefore, in the message switching device of the embodiment of the present invention, the PCIE switching device of which specification can be selected can be determined according to the protocol specification and bandwidth capability of the PCIE switching device and the actual data traffic of the packet switching device.
  • the main control board internally includes: a central processing unit (CPU) And the PCIE interface unit, of course, as is well known to those skilled in the art, the main control board also includes RAM and FLASH, wherein
  • the CPU in the main control board is configured to divide a corresponding PCIE address space for each line card board, and send the PCIE address space information corresponding to each line card board to the PCIE interface unit; the PCIE interface unit is used by The PCIE address space information corresponding to each line card board is separately sent to the line card board through its own PCIE interface and the PCIE switching device.
  • the main control board may further include an Ethernet media control unit, so that the CPU in the main control board is further used. Generating control messages of the respective line cards and transmitting them to the Ethernet media control unit; the Ethernet media control unit in the main control board is configured to use each of the Ethernet interfaces and the Ethernet switching device The control packets of the line card are sent to the respective line cards.
  • the CPU, the PCIE interface unit, and the Ethernet media control unit in the main control board may be processed by a chip system (SoC) with a PCIE interface and an Ethernet interface.
  • SoC chip system
  • an SoC processor without a PCIE interface and without an Ethernet interface plus an external North Bridge device that provides a PCIE interface and an Ethernet interface.
  • the PCIE topology includes the PCIE root complex and multiple PCIE terminals connected to it.
  • the PCIE interface unit in Figure 4 implements the functionality of the PCIE root complex.
  • the internal structure of the line card board can be mainly divided into the following two implementation methods:
  • Method 1 The line card board uses the software forwarding mode of the CPU to implement data message exchange.
  • Figure 5 is a first structural view showing the inside of a line card in one embodiment of the present invention.
  • the line card board may include: a CPU, a PCIE interface adapter unit, and an external interface. Unit, of course, as is well known to those skilled in the art, the line card board also includes RAM and FLASH, wherein
  • the CPU in the line card board is configured to receive data packets sent by the PCIE interface adaptation unit or receive data packets sent by the external network device by using the external interface device.
  • the data packet is forwarded to another line card in the device according to the saved packet forwarding information, the data packet is sent to the PCIE interface adaptation unit, and determined according to the saved packet forwarding information.
  • the data packet is directly sent to the external network device, the data packet is sent to the external interface unit;
  • the PCIE interface adaptation unit is configured to send a data packet sent by the CPU to the PCIE switching device, so that the PCIE switching device exchanges data packets to another line card inside the device, and Transmitting, by the other line card, the data packet sent by the PCIE switching device to the CPU in the online card board;
  • the external interface unit is configured to send a data packet sent by the CPU in the online card to an external device, and send the data packet sent by the external device to the CPU in the online card board. .
  • the CPU can support the PCIE protocol, that is, the CPU can directly exchange PCIE format data packets with the PCIE interface adaptation unit.
  • PCIE protocol that is, the CPU can directly exchange PCIE format data packets with the PCIE interface adaptation unit.
  • a better processing method is: using the SoC processor with the PCIE interface to complete the functions of the CPU and PCIE interface adaptation unit.
  • the CPU may not support the PCIE protocol, that is, the CPU and the PCIE interface adaptation unit exchange data packets of the existing format of the CPU.
  • the PCIE interface adaptation unit needs to perform format adaptation processing on the data packet and then send the data packet to the CPU in the online card board.
  • the data packet needs to be converted into a PCIE format and then sent to the outside. PCIE switching device.
  • the line card no longer forwards data packets through the CPU, but uses the hardware forwarding mode of the message processing engine to exchange data packets.
  • Figure 6 is a schematic view showing the second structure inside the line card in one embodiment of the present invention.
  • the line card board may include: a CPU, a PCIE interface adaptation unit, and a message processing engine, where
  • the CPU in the line card board configured to send message forwarding information to the message processing engine
  • the PCIE interface adaptation unit is configured to send a data packet sent by the external PCIE switching device to the packet processing engine, and send the data sent by the packet processing engine to another line card board.
  • the message is sent to an external PCIE switching device;
  • the packet processing engine is configured to send the data packet sent by the PCIE interface adaptation unit to the external device according to the packet forwarding information, and send the data packet sent by the external device to the PCIE interface. With the unit.
  • the packet processing engine can support the PCIE protocol. That is, the packet processing engine can directly exchange PCIE format data packets with the PCIE interface adaptation unit.
  • the preferred processing method is: using a network processor (NP) with a PCIE interface or an ASIC with a PCIE interface to complete the functions of the message processing engine and the PCIE interface adaptation unit. .
  • the packet processing engine may not support the PCIE protocol, that is, the packet processing engine and the PCIE interface adaptation unit exchange the datagram of the existing format of the message processing engine. Text.
  • the PCIE interface adaptation unit needs to perform format adaptation processing on the data packet, and then send the data packet to the packet processing engine, and After receiving the data packet sent by the packet processing engine, the data packet needs to be converted into a PCIE format and then sent. Send to the external PCIE switching device.
  • the function of the message processing engine and the PCIE interface adaptation unit can be completed by using an NP without a PCIE interface or an ASIC without a PCIE interface.
  • the data packet between the line card and the external network device can be directly forwarded by the packet processing engine.
  • the method 2 It can further improve the forwarding speed of data packets and reduce the traffic load of the CPU.
  • the NP or the ASIC can be used as the message processing engine. Since the NP is programmable, the ASIC is not programmable. Therefore, when the NP is used as the message processing engine, the embodiment of the present invention can have more High business flexibility.
  • the line card board may further include an Ethernet media control unit, such that the CPU in the line card board Further, it is configured to receive a control packet sent by the Ethernet media control unit in the online card board, and generate packet forwarding information according to the control packet; the Ethernet media control unit in the line card board, Receiving a control message sent by the Ethernet switching device through its own Ethernet interface, and sending the control message to the CPU in the online card board.
  • the external interface unit in the line card board is used to connect other optional user interfaces, and may be an SPI4 interface controller, a 10GE Ethernet interface controller, etc., and various interfaces are provided according to user requirements.
  • the external interface of the line card can be converted to a physical interface of almost all communication devices by a dedicated ASIC or FPGA (Field Programmable Gate Array) chip, such as Ethernet, ATM, POS (Packet Over SONET/SDH, Interfaces such as grouping on SONET/SDH.
  • ASIC Field Programmable Gate Array
  • the PCIE topology includes a PCIE root complex and multiple PCIE terminals connected thereto.
  • the PCIE interface adaptation unit in FIG. 5 and FIG. 6 implements the function of the PCIE terminal.
  • the configuration and specific functions in the line card board described in the foregoing manners 1 and 2 are only preferred implementations in the embodiments of the present invention. In actual service implementation, the internal structure of the line card board can also be implemented in other manners. . Regardless of the structure of the line card board, in general, it can be divided into a control unit (equivalent to the CPU in the first mode or the message processing engine in the second mode) and a PCIE interface adaptation unit. 7.
  • control unit in the line card is implemented by using the CPU or the message processing engine in the second method, or by other methods, if the control unit does not support the PCIE protocol, then, for the control unit, The data packet sent and received is the data packet of the original support protocol.
  • the PCIE switching device is like a tunnel.
  • the control unit of the line card board does not care how the PCIE switching device implements flow control and quality of service guarantee. Then the processing of the control unit is completed.
  • the PCIE interface adapter unit inside the line card needs to perform data packets between the control unit and the PCIE switching device. Format conversion processing.
  • the internal portion thereof may be divided into an uplink adaptation unit and a downlink adaptation unit.
  • the uplink adaptation unit completes the message format conversion from the control unit of the line card to the external PCIE switching device, that is, the data packet sent by the control unit is converted into a PCIE format and then sent to the outside.
  • the PCIE switching device; the downlink adaptation unit completes the message format conversion from the external PCIE switching device to the control unit of the local line card, that is, the PCIE format data packet sent by the external PCIE switching device. After the format adaptation process is performed, it is sent to the control unit.
  • the length of the data packet in the PCIE protocol format is a variable and large range in the PCIE protocol.
  • the switch generally chooses no more than 128/256/512
  • the length of the byte, as usual is 256 bytes.
  • the control unit in the line card does not support the PCIE protocol
  • the length of the data packet sent and received is often different from the standard length of the data packet in the PCIE protocol format supported by the PCIE switching device.
  • the PCIE switching device is prevented from discarding the message.
  • the embodiment of the present invention corresponds to the uplink adaptation unit and the downlink adaptation unit of the PCIE switching device. Processing of data message splitting and assembly. A specific implementation can be as shown in Figure 8 below.
  • FIG. 8 is a schematic diagram of an optimized structure inside an uplink adaptation unit and a downlink adaptation unit in an embodiment of the present invention.
  • the uplink adaptation unit may be specifically divided into an information acquisition subunit, a disassembly molecular unit, and a PCIE header encapsulation subunit, where
  • An information obtaining subunit configured to receive a data packet sent by the control unit, obtain PICE address space information of the target line card from the data packet, and send the PICE address space information of the target line card to the PCIE.
  • the header encapsulation sub-unit deletes the PICE address space information of the target line card in the data packet and sends the information to the demolition unit;
  • the splitting unit is configured to split the received data packet into multiple data packets according to a preset PCIE packet length, for example, 256 bytes, and then send the data packet to the PCIE header encapsulating subunit;
  • the PCIE header encapsulation sub-unit is configured to encapsulate the PCIE header for each of the split data packets according to the received PICE address space information of the target line card, and then send the PCIE header to the external PCIE switching device.
  • a preferred implementation process for the PCIE header encapsulation sub-unit to encapsulate a PCIE header for each data packet after the split includes: a PCIE header encapsulation sub-unit according to the received PICE address space of the target line card.
  • Information The PICE address space information of the target line card and the standard length of the PCIE message multiplied by the split data number after the split data packet are decremented by one in the header of the currently split data packet.
  • the PCIE header encapsulation sub-unit in the uplink adaptation unit encapsulates the PCIE header of each of the split data packets, and directly encapsulates the PICE address space information of the target line card with the first data packet after the split.
  • AO + 256 X ( 1 - 1 ), which is the AO shown in Figure 9, directly encapsulates the PICE address space information AO + 256 ( 2 - 1 ) of the target line card for the split second data message. That is, A0 + 256 shown in FIG. 9 directly encapsulates the PICE address space information AO + 256 X ( 3 - 1 ) of the target line card for the split third data message, that is, as shown in FIG. AO + 512, and so on.
  • the length of the data packet sent from the control unit of the line card board can be ensured to meet the requirement of the PCIE data packet length of the external PCIE switching device.
  • the PCIE switching device can perform the hierarchical processing on the data packet sent by the line card, the format of the data packet that can be sent by the control unit in the embodiment of the present invention. Expand. As shown in FIG. 10, a PCIE address header and a reserved byte are added at the head of the data message.
  • the control unit in the line card can carry the PCIE address space information of the target line card in the PCIE address header of the sent data packet, and can further carry the traffic classification (TC) of the packet on the reserved byte.
  • the information (the control unit in the line card carries the PCIE address space information in the header of the sent data packet, and the data packet is a non-PCIE protocol packet.
  • the PCIE address space information is also It can be carried in other locations of the data message sent by the control unit).
  • the information acquiring subunit obtains PCIE address space information of the target line card from the PCIE address header of the data packet sent by the control unit, and further obtains the reserved byte of the data packet.
  • the TC information is sent to the PCIE header encapsulation subunit, and the TC information in the data packet is deleted and sent to the demolition unit; the PCIE header encapsulation subunit is further divided after each
  • the PCIE header of the data packet carries the TC information.
  • the PCIE switching device can internally log based on the TC information. According to the packet classification and scheduling process, a preferred structure of the PCIE switching device can be seen in FIG. 11 , including: a classification management unit, a channel management unit, and a data forwarding unit, where
  • a classification management unit configured to store correspondences between traffic classification TC, virtual channel VC, and line card information
  • the channel management unit is configured to maintain a plurality of VCs, and select a VC according to the correspondence stored in the classification management unit and the data packet carrying the TC information sent by any one of the line card boards, and send the data packet to the channel. Selected VC;
  • the data forwarding unit is configured to forward the data packets in each VC in turn according to the priorities of the VCs in the channel management unit.
  • the embodiment of the present invention encapsulates the routing layer data packet routing manner defined in the PCIE specification, and only needs to support the memory write. In this way, the PCIE bandwidth can be optimally utilized, and the message transmission for different line cards is in accordance with the address-based access addressing mode.
  • the processing layer data message sent by the control unit is not recognized, and only the message is processed as a payload (Payload), and forwarded to the control unit of another line card board, the PCIE switching device
  • the processing layer message is like a tunnel.
  • the downlink adaptation unit may be specifically divided into a PCIE header decapsulation subunit and a group subunit, where
  • the PCIE header decapsulation subunit is configured to remove the PCIE header in each split data packet sent by the PCIE switching device, and then send the split data packet to the framing subunit; the framing subunit And assembling the data packets corresponding to the split data packet, and performing the format adaptation processing on the assembled data packet, and then sending the data packet to the control unit.
  • a further framing detection sub-unit in the downlink adaptation unit is used for Receiving the split data packet sent by the external PCIE switching device, according to whether the address in the PCIE header of each data packet is consecutive after the splitting, and/or whether the packet length is less than a preset PCIE packet length, And/or whether the next split data packet is received within the preset time length, and/or the source address in the packet is the same, to determine the split data packet corresponding to a data packet.
  • the split data packets corresponding to one data packet form a same group of data packets and sent to the PCIE header decapsulation subunit; thus, the PCIE header decapsulation subunit and the framing frame
  • the subunit receives the same set of data packets as the split data packets corresponding to one data packet.
  • the group detection subunit includes a plurality of queues. Referring to FIG. 12, the number of queues is not less than the total number of line cards and main control boards minus one, and each queue corresponds to the source ID of one board.
  • the control unit in the source line card that sends the data message can carry the ID of the source line card in the source ID field in the PCIE address header of the transmitted data message, that is, the Requester ID field shown in FIG. (It can be composed of the bus number, device number and function number of the source line card).
  • the framing detection subunit in the target line card receives the split data packet, it is based on the message PCIE.
  • the ID of the source line card in the Requester ID field of the address header puts the split data packet into the corresponding queue, so that each split data packet in a queue can be determined to correspond to one. Data packets to ensure the correctness of subsequent framing.
  • the internal layer includes the physical layer in the inbound direction and the link layer subunit 1 and the physical layer in the outbound direction.
  • Link layer subunit 2 used to complete physical layer and link layer processing.
  • the control unit is SPI4 (System Packet Interface Level 4, system package interface 4th Level) interface
  • physical layer and link layer sub-units 1 and 2 complete the physical layer and link layer identification of SPI4 packets, extract protocol layer messages;
  • the control unit is XGMII interface (10G Media Independent Interface, 10G media independent) Interface
  • the physical layer and link layer sub-units 1 and 2 complete the physical layer and link layer processing of the 10GE Ethernet.
  • control unit and the uplink adaptation unit and the downlink adaptation unit can be independent of each other or integrated.
  • FIG. 14 is a flow diagram of data message exchange in a preferred embodiment of the present invention.
  • the data packet exchange process specifically includes the following steps:
  • Step 1401 Set up the PCIE switching device.
  • Step 1402 Set up an Ethernet switching device.
  • Step 1403 The main control board allocates a corresponding PCIE address space for each line card board.
  • Step 1404 The source line card sends the data packet to the PCIE switching device.
  • the process of the data line card sending the data packet to the PCIE switching device may include: the source line card board splits the data message into multiple lengths according to a preset PCIE message length, such as 256 bytes. For the 256-byte data packet, the PCIE header is encapsulated for each data packet after the split according to the PICE address space information of the target line card, and then sent to the PCIE switching device.
  • a preset PCIE message length such as 256 bytes.
  • the first data packet after the split can directly encapsulate the PICE address of the target line card.
  • the spatial information AO + 256 X ( 1 - 1 ), that is, the AO shown in Fig. 9, directly encapsulates the PICE address space information of the target line card AO + 256 ⁇ ( 2 - after the split second data message 1), that is, AO + 256 shown in FIG. 9,
  • the third data packet after splitting directly encapsulates the PICE address space information ⁇ 0 + 256 ⁇ ( 3 - 1 ) of the target line card, that is, in FIG. 9 A0 + 512 as shown, and so on.
  • Step 1405 The PCIE switching device sends the data packet to the target line card board according to the PCIE address space corresponding to each line card board.
  • the target line card After receiving the data packet, the target line card removes the PCIE header in each of the received split data packets, and then assembles the split data packets corresponding to one data packet. , restore the data packet sent by the source line card.
  • the method for determining, by the target line card board, the data packets corresponding to the split of one data packet includes:
  • the target line card board determines whether the address in the PCIE header of each data packet is consecutive after the splitting is received, and the data packets are successively split after the address is determined to be corresponding to the split data of one data packet.
  • the target line card board determines whether there is a first split data packet whose message length is less than a preset PCIE packet length, and if yes, the first split after the current split is received. After the data packet is split, each data packet and the first split data packet are determined as corresponding data packets corresponding to a data packet.
  • the target line card board determines whether the next split data message is not received within the preset time length in the current receiving, and if yes, the split received after the current receiving
  • the data message is determined to be a data message corresponding to the split of one data message
  • the target line card board determines whether the source address in each data packet after the splitting is received is the same, and if yes, the data packets with the same source address are determined to correspond to one Each data packet after the data message is split.
  • Step 1406 The main control board sends control packets of each line card to the Ethernet switching device.
  • Step 1407 The Ethernet switching device sends control packets of each line card to each line card board.
  • Step 1408 Detecting an Ethernet connection between the Ethernet switching device and each line card board is No failure occurs, and if yes, step 1409 is performed, otherwise, step 1406 is returned.
  • Step 1409 Forward the control packet sent by the main control board to each line card through the PCIE switching device.
  • Step 1410 Detect whether the PCIE connection between the PCIE switching device and each line card board fails. If yes, execute step 1411. Otherwise, return to step 1404.
  • Step 1411 Forward data packets between the line cards through the Ethernet switching device. It should be noted that the above steps in Fig. 14 are only different steps for convenience of description, and there is no strict execution order.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

L'invention concerne un dispositif d'échange de paquets, une carte de circuits imprimés et un procédé d'échange de paquets de données. Un dispositif d'échange de paquets comprend une carte de commande principale, un dispositif d'échange PCIE et de nombreuses cartes de circuits imprimés, associées, la carte de commande principale est utilisée pour chaque carte afin d'attribuer l'espace adresse PCIE correspondant; chaque carte de circuits imprimés est utilisée pour transmettre un paquet de données à un dispositif d'échange PCIE, ou recevoir un paquet de données transmis par le dispositif d'échange de paquets; le dispositif d'échange PCIE est utilisé pour recevoir et transmettre un paquet de données en fonction de l'espace adresse PCIE correspondant à chaque carte de circuits imprimés. L'invention permet d'obtenir des performances élevées et une fiabilité élevée de l'échange de paquets de données.
PCT/CN2007/070413 2007-03-30 2007-08-03 Procédé d'échange de paquets de données, dispositif et carte de circuits imprimés WO2008119221A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN2007100909940A CN101277196B (zh) 2007-03-30 2007-03-30 一种基于pcie交换网的通信系统、通信方法及线卡板
CN200710090994.0 2007-03-30
CN2007100909936A CN101277195B (zh) 2007-03-30 2007-03-30 一种交换网通信系统、实现方法及交换装置
CN200710090993.6 2007-03-30

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EP3158455A4 (fr) * 2014-06-23 2018-03-07 Liqid Inc. Matrice commutée modulaire pour des systèmes de stockage de données
US10503618B2 (en) 2014-06-23 2019-12-10 Liqid Inc. Modular switched fabric for data storage systems
CN109495278A (zh) * 2018-09-30 2019-03-19 天津市英贝特航天科技有限公司 一种基于xmc标准接口的网卡
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CN109347818A (zh) * 2018-10-12 2019-02-15 华东师范大学 一种协议可重构万兆通信的文件传输系统
CN111181872A (zh) * 2019-11-19 2020-05-19 视联动力信息技术股份有限公司 一种数据处理方法和装置
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WO2022095571A1 (fr) * 2020-11-03 2022-05-12 中兴通讯股份有限公司 Procédé et dispositif de transfert de message et support de stockage lisible par ordinateur
CN113050703A (zh) * 2021-02-05 2021-06-29 新华三技术有限公司 一种流量控制方法及设备
CN113050703B (zh) * 2021-02-05 2022-11-18 新华三技术有限公司 一种流量控制方法及设备
CN114090313A (zh) * 2021-10-31 2022-02-25 新华三技术有限公司合肥分公司 一种转发表生成方法及装置
CN114090313B (zh) * 2021-10-31 2024-04-12 新华三技术有限公司合肥分公司 一种转发表生成方法及装置

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