WO2008114167A2 - Extended drain transistor with resecced gate and method of producing the same - Google Patents

Extended drain transistor with resecced gate and method of producing the same Download PDF

Info

Publication number
WO2008114167A2
WO2008114167A2 PCT/IB2008/050893 IB2008050893W WO2008114167A2 WO 2008114167 A2 WO2008114167 A2 WO 2008114167A2 IB 2008050893 W IB2008050893 W IB 2008050893W WO 2008114167 A2 WO2008114167 A2 WO 2008114167A2
Authority
WO
WIPO (PCT)
Prior art keywords
region
control gate
forming
layer
channel
Prior art date
Application number
PCT/IB2008/050893
Other languages
French (fr)
Other versions
WO2008114167A3 (en
Inventor
Pierre Goarin
Original Assignee
Nxp B.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp B.V. filed Critical Nxp B.V.
Priority to CN2008800086433A priority Critical patent/CN101636844B/en
Priority to US12/531,578 priority patent/US8227857B2/en
Priority to EP08719651.5A priority patent/EP2140495B1/en
Publication of WO2008114167A2 publication Critical patent/WO2008114167A2/en
Publication of WO2008114167A3 publication Critical patent/WO2008114167A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66704—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Definitions

  • Fig. 7A transistor is schematically shown in Fig. 7.
  • Fig. 7A there is shown a NMOS transistor in a cross-sectional view along a longitudinal axis from source to drain.
  • the EDMOS transistor 700 of Fig. 7A comprises a substrate 701 having different regions formed thereon. From the left to the right in Fig. 7A a source region 702 formed by a highly doped region (N++) and connected to a source region contact 703 is shown. Next a channel region 704 is formed by a p-well on top of which a control gate 705 is formed which has a control gate contact 706 and which is insulated from the channel region 704 by a gate insulating layer 707.
  • the drift region will be extended or not and/or its doping will be lowered or increased. So for low breakdown voltages the length of this region is relatively small and its doping relatively high. However, this leads to the fact that the contribution to the overall resistance of the transistor or device is relatively limited and the overall resistance is caused mainly by the channel resistance.
  • a method of manufacturing a planar extended drain transistor comprises forming a semiconductor layer on a substrate, wherein the semiconductor layer has a first side which is in contact with the substrate and a second opposite side which forms a surface, and forming a trench into a first portion of the semiconductor layer by removing parts of the semiconductor layer in the first portion in such a way that at least a portion of the trench below the surface of the semiconductor layer is removed.
  • a control gate is formed in the trench and a planar extended drain transistor is formed by forming a drain region, a source region, a drift region, and a channel region in the semiconductor layer, wherein the channel region is formed in the first portion in such a way that at least a portion of the control gate is buried by the channel region.
  • a gate insulation layer may be formed in the trench before the control gate is formed.
  • the channel region may optionally be formed by remaining parts of the first portion of the semiconductor layer, i.e. from parts that were not removed in the forming of the trench.
  • the trench may have a trapezoid cross- section.
  • the substrate may be formed by any suitable substrate, e.g. by an SOI-substrate.
  • planar extended drain transistor planar EDMOS transistor
  • the process flow in the method according to an exemplary embodiment may stick as much as possible to the standard process flow, so that possibly only few additional process steps may be added compared to a conventional CMOS process flow.
  • the number of additional masks may be limited in a process flow according to an exemplary embodiment of the method.
  • the planar extended drain transistor may be formed as a NMOS or an PMOS device.
  • the planar extended drain transistor further comprises a plurality of control gates, wherein the plurality of control gates have a comb-like structure.
  • the comb-like structure may comprise or may be formed by a plurality of trenches, which may be formed in the channel layer or channel region.
  • the term "comb-like structure" may in particular denote a structure that - in a cross-sectional view - comprises a plurality of control gates and a plurality of channel regions which are arranged in a teeth-like structure, i.e. the control gates and the channel regions mesh into another.
  • the comb-like structure may increase the area of the channel regions, i.e. the area in which current may flow, since a larger area of the channel layer will be influenced by a state of the control gate.
  • SiGe may be etched with a higher etching rate as silicon.
  • the control gate may be formed in the trench and in the cavity. Forming the control gate as well in the cavity may lead to the fact that at least portions of a control gate are completely enclosed or surrounded by the channel region, i.e. completely buried under the channel region. This may lead to the fact that the channel region may be formed by a great area surrounding the control gate so that a greater current may flow through the channel region under the control of the switching of the control gate.
  • one exemplary aspect of the invention may be seen in the burying of at least one control gate into the semiconductor layer from which the channel region is formed to possibly increase the number of channels and/or the area of the channel for the same device area. In this manner it may be possible to multiply the number of current paths in order to have more channel resistance paths in parallel that may drastically reduce or decrease the channel resistance.
  • Fig. 4 schematically illustrates a process flow of a method of producing the planar extended drain transistor according to the first exemplary embodiment.
  • Fig. 7 schematically illustrates a conventional planar extended drain transistor.
  • Fig. 1 to 6 For the following illustration of the planar extended drain transistor and method of producing the same it is referred to Fig. 1 to 6. All exemplary embodiments are described for an NMOS device, however PMOS devices are of course also possible.
  • Fig. 2 schematically shows a planar extended drain transistor 200 according to a second exemplary embodiment.
  • the EDMOS transistor 200 of Fig. 2 is shown in a perspective view corresponding to Fig. IB.
  • the EDMOS transistor 200 comprises a substrate 201 onto or from which different regions are formed.
  • the planar extended drain transistor comprises a plurality of control gates 202, which are not shown in the upper part of the Fig. 2 and which may be contacted to a control gate contact, which is also not shown for clarity reasons.
  • Each of the plurality of control gates is formed by a tube-like structure.
  • Gate insulation layers 204 surround the control gates. As shown in Fig.
  • the control gates are partially formed in and underneath a source region 205 which is formed by a highly doped region (N++) and which may be connected to a source region contact.
  • a channel region 207 is formed by a p-well through which portions of the control gate 202 extend so that these portions are buried by the channel region 207.
  • a drift region 208 is formed in the substrate, which drift region is only lightly doped (N-).
  • a drain region 209 is formed by a highly doped region (N++), wherein the drain region 209 may be connected to a drain contact.
  • the arrows 211 schematically illustrate the current flows. In particular, it may be noted that a plurality of channel regions or current paths are formed, which are arranged in Fig. 2 below and above the portion of the control gate 102 which is buried in the channel region or channel layer.
  • Fig. 4 schematically illustrate a process flow of a method of producing the planar extended drain transistor according to the first exemplary embodiment which may be similar to conventional EDMOS process flow, however it may be different in that the process flow according to an exemplary embodiment may be suitable to bury a gate into silicon, e.g. channel region, and to connect it afterwards.
  • a silicon-germanium (SiGe) layer 412 may be formed in a first portion of a first sub layer 413 of a silicon substrate 401.
  • SiGe silicon-germanium
  • the digging may be performed by using a so-called STI (Shallow Trench Isolation) mask in an etching process.
  • the SiGe layer 412 is removed by etching, the result of which is shown in Fig. 4D. Because the etching rate of SiGe is higher than that one of the silicon of the substrate 401, the SiGe layer 412 can be selectively removed without attacking the silicon of the substrate 401. Thus, a cavity 415 in the silicon substrate 401 may be formed.
  • a gate oxide 404 i.e. a gate insulation layer formed by silicon oxide, for example, is grown or deposited in the trench 414 and the cavity 415.
  • each of the cavities 515 may be filled by a gate insulation layer 504 and a control gate 502 formed by silicon oxide and polysilicon, respectively, which is shown in Fig. 5 C.
  • the different parts of the planar extended drain transistor may be formed by implantation of the necessary doping material.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

A planar extended drain transistor (100) is provided which comprises a control gate (102), a drain region (109), a channel region (107), and a drift region (108), wherein the driftregion (108) is arrangedbetween the channel region (107) and the drain region (109). Furthermore, the control gate (102) is at least partially buried into the channel region (107) and the drift region (108) comprises a doping material density which is lower than the doping material density of the drain region (109).

Description

Planar extended drain transistor and method of producing the same
FIELD OF THE INVENTION The invention relates to a planar extended drain transistor.
Beyond this, the invention relates to a method of producing a planar extended drain transistor.
BACKGROUND OF THE INVENTION Extended drain MOS (EDMOS) transistors are one of the main devices used in the embedded power market. Their structure is similar to conventional MOSFETs. EDMOS transistors comprise a region between the drain region and the channel region that is called the drift region and that is lowly or lightly doped. This drift region is used to get higher breakdown voltage than the one of the p-n junction between channel and drain. Such a conventional EDMOS, which is similar to the one shown for example in
US 2004/002196, transistor is schematically shown in Fig. 7. In Fig. 7A there is shown a NMOS transistor in a cross-sectional view along a longitudinal axis from source to drain. The EDMOS transistor 700 of Fig. 7A comprises a substrate 701 having different regions formed thereon. From the left to the right in Fig. 7A a source region 702 formed by a highly doped region (N++) and connected to a source region contact 703 is shown. Next a channel region 704 is formed by a p-well on top of which a control gate 705 is formed which has a control gate contact 706 and which is insulated from the channel region 704 by a gate insulating layer 707. Next a drift region 708 is formed in the substrate, which drift region is only lightly doped (N-). A highly doped region (N++) forms a drain region 709, wherein the drain region 709 is connected to a drain contact 710. An arrow 711 schematically illustrates the current flow.
Fig. 7B shows a perspective view of the EDMOS transistor of Fig. 7A. For illustrative reasons a portion of the drain region 709 and the drift region 708 are cut away. Furthermore, the different regions are shown as simple cuboids.
Depending on the type of breakdown voltage wanted the drift region will be extended or not and/or its doping will be lowered or increased. So for low breakdown voltages the length of this region is relatively small and its doping relatively high. However, this leads to the fact that the contribution to the overall resistance of the transistor or device is relatively limited and the overall resistance is caused mainly by the channel resistance. OBJECT AND SUMMARY OF THE INVENTION
It is an object of the invention to provide a planar extended drain transistor and a method of producing the same, wherein the planar extended drain transistor may exhibit a lower resistance and thus may enable a greater current flow through the transistor while, preferably, at the same time does not occupy a greater area.
In order to achieve the object defined above, a planar extended drain transistor and a method of producing the same according to the independent claims are provided.
According to an exemplary embodiment a planar extended drain transistor is provided which comprises a control gate, a drain region, a channel region, and a drift region, wherein the drift region is arranged between the channel region and the drain region. Furthermore, the control gate is at least partially buried into the channel region and the drift region comprises a doping material density, which is lower than the doping material density of the drain region. In particular, the planar extended drain transistor may comprise precisely one drift region. That is, only one drift region is arranged between the drain region and the channel region, while no drift region is arranged between the source region and the channel region, i.e. the channel region and the source region are joined to each other. Furthermore, the control gate and the channel region may be insulated from each other by a gate insulation layer.
According to an exemplary embodiment a method of manufacturing a planar extended drain transistor is provided, wherein the method comprises forming a semiconductor layer on a substrate, wherein the semiconductor layer has a first side which is in contact with the substrate and a second opposite side which forms a surface, and forming a trench into a first portion of the semiconductor layer by removing parts of the semiconductor layer in the first portion in such a way that at least a portion of the trench below the surface of the semiconductor layer is removed. Furthermore, a control gate is formed in the trench and a planar extended drain transistor is formed by forming a drain region, a source region, a drift region, and a channel region in the semiconductor layer, wherein the channel region is formed in the first portion in such a way that at least a portion of the control gate is buried by the channel region. In particular, a gate insulation layer may be formed in the trench before the control gate is formed. Furthermore, the channel region may optionally be formed by remaining parts of the first portion of the semiconductor layer, i.e. from parts that were not removed in the forming of the trench. In particular, the trench may have a trapezoid cross- section. According to this exemplary embodiment, the substrate may be formed by any suitable substrate, e.g. by an SOI-substrate.
The term "planar" may in particular denote that the transistor is, relative to the extent of a substrate, horizontally arranged and may in particular be distinguished from a so- called vertical transistor. The term "buried" may in particular denote that at least a portion of a first layer, e.g. the control gate, is arranged below the surface of a second layer, e.g. the channel region. For example, the first layer may be completely enclosed by the second layer or the first layer may be formed in a trench that is formed in the second layer. Thus, leading to an arrangement in which at least a part of the control gate is positioned below a level formed by a surface level of the channel region. Optionally, there may be of course a third layer between the first layer and the second layer, e.g. a gate insulation layer.
The term "drift region" may in particular denote a region between the drain region and the channel region that that is lowly or lightly doped. In particular, this drift region may be doped by the same doping material as the drain region but will be doped less dense, i.e. less ions may be implemented in the drift region than in the drain region. This drift region may be used to get higher breakdown voltage than the one of the p-n junction between channel and drain.
By a planar extended drain transistor (planar EDMOS transistor) according to the above described exemplary embodiment it may possible to provide more than one channel region, since at least parts of the control gate are arranged buried into the channel region. In particular, there may be formed two channel regions or current paths, wherein one is formed below the control gate and the other one is above the gate. This may lead to the fact that the resistance of the channel region may be reduced, since a greater area of the channel region may be influenced by the control gate, so that it may be possible that a higher current flows through the channel region without increasing the total area of the planar EDMOS transistor. In particular, it may not be necessary to increase the width of the channel region to increase the possible current, as it would be in a common EDMOS, since in an EDMOS transistor according to the exemplary embodiment there is more than one possible current path. By burying at least a part of the control gate into the channel region which is arranged between the source region and the drift region it may be possible to achieve a straight current flow from the source region through the channel region and the drift region to the drain region, while possibly providing several current paths.
It may be seen as a gist of an exemplary embodiment to bury or to recess at least one control gate into the semiconductor layer the channel region is formed from to possibly increase the number of channels and/or the area of the channel for the same device area. That way it may be possible to multiply the number of current paths in order to have more channel resistance paths in parallel which may drastically reduce or decrease the channel resistance. In an illustrative way it may be said that the control gate density may be increased. For producing the buried control gate a trench may be dig into the channel region, wherein the trench may have a trapezoid or tubular shape in cross-section, for example. In particular, the process flow in the method according to an exemplary embodiment may stick as much as possible to the standard process flow, so that possibly only few additional process steps may be added compared to a conventional CMOS process flow. In particular, the number of additional masks may be limited in a process flow according to an exemplary embodiment of the method. According to an exemplary embodiment the planar extended drain transistor may be formed as a NMOS or an PMOS device.
Next, further exemplary embodiments of the planar extended drain transistor are described. However, these embodiments also apply to the method of producing the same.
According to another exemplary embodiment the planar extended drain transistor further comprises a control gate contact and a source region, wherein the control gate contact is electrically connected to the control gate, and wherein the source region is at least partially arranged between the channel region and the control gate contact. That is, the control gate contact may be arranged farther away from the channel region than the source region. In particular a portion of the control gate may be arranged buried under the source region and/or the channel region. In particular, a gate insulation layer may be further arranged between the source region and the control gate contact and/or the control gate.
The arrangement of portions of the control gate buried into the channel layer or arranged below the surface of the channel layer may lead to the fact that more than one channel region is formed, which may lead to the fact that a greater current may flow between the source region and the drain region. The term "channel layer" may in particular denote the whole layer which forms the channel, e.g. a layer which is formed as a single layer of the same material, if necessary a doped material. The term "channel region" may in particular denote the portions of the channel layer which are causing the current flow between a source region and a drain region, i.e. the portions of the channel layer which provide the functionality of the channel of a transistor.
According to another exemplary embodiment of the planar extended drain transistor the control gate is formed by a layer. In particular, at least portions of the control gate may have a plate shaped form. Furthermore a plurality of control gates may be formed by a plurality of plate shaped layers, which may be arranged in a sandwiched manner, i.e. in an alternating way in which a plate shaped control gate is followed by a channel region which is again followed by a plate shaped control gate and so on. In particular, at least one plate shaped control gate may be buried completely in the channel layer. That is, a multilayered sandwich structure may be formed in a first portion of the transistor, namely in the channel region, which is arranged between the source region and the drift region. This sandwich structure may form a plurality of control gates and a plurality of channel regions providing a plurality of current flow paths.
According to another exemplary embodiment the planar extended drain transistor further comprises a plurality of control gates, wherein the control gates have a substantially circular cross section. In particular, the control gates may have a longitudinal axis extending between the source region and the drift region, wherein the cross section is taken perpendicular to the longitudinal axis. Thus, control gates may be formed having a substantially tubular shape. In particular, the tubular shaped control gates may be buried into the channel layer, e.g. may be completely embedded by the channel layer. The tubular shaped control gates may form a kind of layer, i.e. may be arranged horizontally in one plane in the coordinate system of the planar transistor. Optionally, a plurality of such control gate layers, each having a plurality of tubular shaped control gates, may be formed in the channel layer.
According to another exemplary embodiment the planar extended drain transistor further comprises a plurality of control gates, wherein the plurality of control gates have a comb-like structure. In particular, the comb-like structure may comprise or may be formed by a plurality of trenches, which may be formed in the channel layer or channel region. The term "comb-like structure" may in particular denote a structure that - in a cross-sectional view - comprises a plurality of control gates and a plurality of channel regions which are arranged in a teeth-like structure, i.e. the control gates and the channel regions mesh into another. The comb-like structure may increase the area of the channel regions, i.e. the area in which current may flow, since a larger area of the channel layer will be influenced by a state of the control gate.
According to another exemplary embodiment the planar extended drain transistor further comprises at least one control gate contact, and a source region, wherein the at least one control gate contact is electrically connected to at least one of the plurality of control gates, and wherein the at least one control gate contact is at least partially arranged between the drift region and the source region.
Such an arrangement may lead to the following sequence of regions. The first region is formed by the drain region, adjoining the drift region, adjoining the channel region in which the control gates are incorporated or embedded which channel region is adjoined by the source region.
Next, further exemplary embodiments of the method of producing the planar extended drain transistor are described. However, these embodiments also apply to the planar extended drain transistor. According to another exemplary embodiment the method further comprises forming an intermediate layer onto a second portion of the substrate, and forming the semiconductor layer onto the substrate and the intermediate layer in such a way that the first portion of the semiconductor layer is arranged on the intermediate layer. In particular, the semiconductor layer may cover the intermediate layer completely or partially. For example, the intermediate layer may comprise or may be formed by SiGe while the semiconductor layer may be formed by silicon.
This exemplary embodiment may not be limited to a manufacturing method of an EDMOS transistor but may also be used to manufacture an LDMOS or CMOS transistor.
In other words, the term "extended drain" in "planar extended drain transistor" is purely optional. That is, in particular no forming of a drift region is necessary on contrary for this exemplary embodiment the forming of the drift region is purely optional.
According to another exemplary embodiment the method further comprises that the forming of the trench is done in such a way that the trench contacts the intermediate layer. For example, the trench is formed so that the trench exposes parts of the intermediate layer, e.g. a top face of the intermediate layer or a side face of the intermediate layer. Thus, at least portions of the intermediate layer may be accessible from the outside, e.g. the surface of the semiconductor layer.
According to another exemplary embodiment the method further comprises forming a cavity by removing the intermediate layer before the control gate is formed. In particular, etching may do the removing. In case SiGe forms the intermediate layer and silicon forms the semiconductor layer, the intermediate layer may be easily removed by etching, since
SiGe may be etched with a higher etching rate as silicon. Furthermore, the control gate may be formed in the trench and in the cavity. Forming the control gate as well in the cavity may lead to the fact that at least portions of a control gate are completely enclosed or surrounded by the channel region, i.e. completely buried under the channel region. This may lead to the fact that the channel region may be formed by a great area surrounding the control gate so that a greater current may flow through the channel region under the control of the switching of the control gate.
According to another exemplary embodiment the method further comprises forming a control gate contact which connects the control gate formed in the trench, wherein the source region is formed at least partially between the channel region and the control gate contact. That is, the control gate contact may be formed farther away from the channel region as the source region. In particular, the source region may surround a part of the control gate that is contacted by the control gate contact.
This may result in a horizontal arrangement of the different regions of the planar extended drain transistor like drain region, drift region, channel region, source region, and control gate contact, wherein the control gate itself may be formed partially below or buried into the channel region and parts of the source region. That is, the source region may cover parts of the control gate.
According to another exemplary embodiment the method further comprises forming a plurality of trenches in the first portion of the semiconductor layer, and forming a plurality of control gates in the plurality of trenches. In particular, the trenches may be formed substantially parallel to each other, e.g. in a comb-like structure. For example, each of the trenches may have a trapezoid cross-section leading to the fact that a cross-section through the first portion of the semiconductor layer may looks like a teeth- like structure. Preferably, in each trench one control gate may be formed.
According to another exemplary embodiment the method further comprises forming one control gate contact contacting at least a number of the plurality of control gates in the first portion of the semiconductor. In particular, each control gate is connected to the control gate contact that may be arranged directly above the control gates formed in the trenches. That is, the control gate contact may be formed above the channel region of the transistor. According to another exemplary embodiment the method further comprises forming a plurality of tube-like cavities from the plurality of trenches, and forming a plurality of control gates in the plurality of tube-like cavities. In particular, this may be done by hydrogen annealing the semiconductor layer, e.g. formed by silicon, i.e. an annealing step which is performed under a hydrogen atmosphere at increased temperature.
This exemplary embodiment may not be limited to a manufacturing method of an EDMOS transistor but may also be used to manufacture an LDMOS or CMOS transistor. In other words, the term "extended drain" in "planar extended drain transistor" is purely optional. That is, in particular no forming of a drift region is necessary on contrary for this exemplary embodiment the forming of the drift region is purely optional.
According to another exemplary embodiment the method further comprises forming a further trench into the semiconductor layer in such a way that at least a portion of each of the cavities is exposed to the further trench. This further trench may subsequently be used to form a contact to the cavities, i.e. to the control gates formed in the cavities.
Summarizing, one exemplary aspect of the invention may be seen in the burying of at least one control gate into the semiconductor layer from which the channel region is formed to possibly increase the number of channels and/or the area of the channel for the same device area. In this manner it may be possible to multiply the number of current paths in order to have more channel resistance paths in parallel that may drastically reduce or decrease the channel resistance.
The aspects defined above and further aspects of the invention are apparent from the examples of embodiment to be described hereinafter and are explained with reference to these examples of embodiment. The aspects and exemplary embodiments described above may be combined, i.e. features explicitly described in connection with one exemplary embodiment may be combined with another described exemplary embodiment.
BRIEF DESCRIPTION OF THE DRAWINGS The invention will be described in more detail hereinafter with reference to examples of embodiment but to which the invention is not limited.
Fig. 1 schematically illustrates a planar extended drain transistor according to a first exemplary embodiment.
Fig. 2 schematically illustrates a planar extended drain transistor according to a second exemplary embodiment.
Fig. 3 schematically illustrates a planar extended drain transistor according to a third exemplary embodiment.
Fig. 4 schematically illustrates a process flow of a method of producing the planar extended drain transistor according to the first exemplary embodiment.
Fig. 5 schematically illustrates a process flow of a method of producing the planar extended drain transistor according to the second exemplary embodiment.
Fig. 6 schematically illustrates a process flow of a method of producing the planar extended drain transistor according to the third exemplary embodiment.
Fig. 7 schematically illustrates a conventional planar extended drain transistor.
DESCRIPTION OF EMBODIMENTS
The illustration in the drawing is schematically. In different drawings, similar or identical elements are provided with the similar or same reference signs.
For the following illustration of the planar extended drain transistor and method of producing the same it is referred to Fig. 1 to 6. All exemplary embodiments are described for an NMOS device, however PMOS devices are of course also possible.
Fig. 1 schematically shows a planar extended drain transistor (planar EDMOS Transistor) 100 according to a first exemplary embodiment. The EDMOS transistor 100 of Fig. IA comprises a substrate 101 onto or from which different regions are formed. From the left to the right in Fig. IA a control gate 102 connected to a control gate contact 103 and surrounded by a gate insulation layer 104. The control gate is partially formed in and underneath a source region 105 which is formed by a highly doped region (N++) and connected to a source region contact 106. A channel region 107 is formed by a p-well through which portions of the control gate 102 extend so that the channel region 107 buries these portions. Next a drift region 108 is formed in the substrate, which drift region is only lightly doped (N-). Next, a drain region 109 is formed by a highly doped region (N++), wherein the drain region 109 is connected to a drain contact 110. The arrows 111 schematically illustrate the current flows. In particular, it may be noted that two channel regions or current paths are formed, which are arranged in Fig. IA below and above the portion of the control gate 102 which is buried in the channel region or channel layer. Fig. IB shows a perspective view of the EDMOS transistor of Fig. IA. For illustrative reasons a portions of the drain region 109 and the drift region 108 are cut away and the different regions are shown as simple cuboids. Furthermore, the control gate contact and the contacts are omitted in Fig. IB for the sake of clarity.
Fig. 2 schematically shows a planar extended drain transistor 200 according to a second exemplary embodiment. The EDMOS transistor 200 of Fig. 2 is shown in a perspective view corresponding to Fig. IB. The EDMOS transistor 200 comprises a substrate 201 onto or from which different regions are formed. From the top right to the bottom left in Fig. 2 the planar extended drain transistor comprises a plurality of control gates 202, which are not shown in the upper part of the Fig. 2 and which may be contacted to a control gate contact, which is also not shown for clarity reasons. Each of the plurality of control gates is formed by a tube-like structure. Gate insulation layers 204 surround the control gates. As shown in Fig. 2A the control gates are partially formed in and underneath a source region 205 which is formed by a highly doped region (N++) and which may be connected to a source region contact. Next a channel region 207 is formed by a p-well through which portions of the control gate 202 extend so that these portions are buried by the channel region 207. Next a drift region 208 is formed in the substrate, which drift region is only lightly doped (N-). Next a drain region 209 is formed by a highly doped region (N++), wherein the drain region 209 may be connected to a drain contact. The arrows 211 schematically illustrate the current flows. In particular, it may be noted that a plurality of channel regions or current paths are formed, which are arranged in Fig. 2 below and above the portion of the control gate 102 which is buried in the channel region or channel layer.
Fig. 3 schematically shows a planar extended drain transistor 300 according to a third exemplary embodiment. The EDMOS transistor 300 of Fig. 3A is shown in a perspective view corresponding to Fig. 2. The EDMOS transistor 300 comprises a substrate 301 onto or from which different regions are formed. From the top right to the bottom left in Fig. 3A the planar extended drain transistor comprises a source region 305 which is formed by a highly doped region (N++) and which may be connected to a source region contact. Next a channel region 307 is formed by a p-well. Into the channel region 307 or channel layer a plurality of control gates 302 are embedded which may be contacted to a control gate contact, which is not shown for clarity reasons. Each of the plurality of control gates is formed by a comb-like structure. The control gates are surrounded by gate insulation layers 304 and are buried at least partially into the channel layer 307. That is, the control gates are build in trenches formed in the channel layer 307 so that side areas of the comb-like structure are in close contact with the channel layer 307 so that a plurality of channel regions or current paths are formed.
Next a drift region 308 is formed in the substrate, which drift region is only lightly doped (N-). Next a drain region 309 is formed by a highly doped region (N++), wherein the drain region 309 may be connected to a drain contact. The arrows 311 schematically illustrate the current flows.
Fig. 3B shows the planar extended drain transistor 300 of Fig. 3 A, wherein a control gate contact 303 is applied onto the plurality of comb-like control gates 302.
Fig. 4 schematically illustrate a process flow of a method of producing the planar extended drain transistor according to the first exemplary embodiment which may be similar to conventional EDMOS process flow, however it may be different in that the process flow according to an exemplary embodiment may be suitable to bury a gate into silicon, e.g. channel region, and to connect it afterwards. In a first process step, the result of which is shown in Fig. 4A, a silicon-germanium (SiGe) layer 412 may be formed in a first portion of a first sub layer 413 of a silicon substrate 401. In a next step, the result of which is shown in Fig. 4B, the SiGe layer 412 is buried by a second sub layer of the silicon substrate 401 which may be grown on the first sub layer by epitaxy, wherein the second sub layer has a predetermined thickness. Optionally, a plurality of intermediate layers and sub layers of a semiconductor material, e.g. silicon, may be formed, which may lead to a transistor having a plurality of control gates arranged in a sandwich structure. In a next step, the result of which is shown in Fig. 4C, a trench 414 is dig into the second sub layer, the SiGe layer 412, and optionally into the first sub layer 413 so that the buried SiGe layer 412 is reached. The digging may be performed by using a so-called STI (Shallow Trench Isolation) mask in an etching process. Afterwards, the SiGe layer 412 is removed by etching, the result of which is shown in Fig. 4D. Because the etching rate of SiGe is higher than that one of the silicon of the substrate 401, the SiGe layer 412 can be selectively removed without attacking the silicon of the substrate 401. Thus, a cavity 415 in the silicon substrate 401 may be formed. In a next step, the result of which is shown in Fig. 4E, a gate oxide 404, i.e. a gate insulation layer formed by silicon oxide, for example, is grown or deposited in the trench 414 and the cavity 415. Afterwards in a further step, the result of which is shown in Fig. 4F, the control gate 402 may be formed by depositing a electrically conductive material like polysilicon. In further steps, the result of which is shown in Fig. 4G, the different parts of the planar extended drain transistor 400 may be formed by implantation of the necessary doping material. Thus, a drain region 409, a drift region 408, a channel region 407, and a source region 405 is formed. Fig. 5 schematically illustrate a process flow of some steps of a method of producing the planar extended drain transistor according to the second exemplary embodiment which may be similar to the above described process flow, but which process relies on hydrogen annealing to create a plurality of cavities. Therefore, only the differences are described in greater detail. In particular, no SiGe layer is deposited. In a first shown step, the result of which is shown in Fig. 5 A, a plurality of trenches 514 are dig into a silicon substrate 501, e.g. by an etching process in which an STI mask is used. In a next step, the result of which is shown in Fig. 5B, the silicon of the silicon substrate 501 is exposed to a hydrogen atmosphere at high temperature. Under such conditions silicon atoms start to migrate and create tube-like cavities 515 in the silicon substrate 501 out of the trenches 514. Similar as described above each of the cavities 515 may be filled by a gate insulation layer 504 and a control gate 502 formed by silicon oxide and polysilicon, respectively, which is shown in Fig. 5 C. In further steps the different parts of the planar extended drain transistor may be formed by implantation of the necessary doping material.
Fig. 6 schematically illustrates some steps of a process flow of a method of producing the planar extended drain transistor according to the third exemplary embodiment. The process flow of the third exemplary embodiment may be similar to the above described process flow of the second exemplary embodiment. Therefore, only the differences are described greater detail. As in the second exemplary embodiment a plurality of trenches 614 are dig into a silicon substrate 601, e.g. by an etching process which applies an STI mask. However, according to the third exemplary embodiment no cavities are formed, but a gate insulation layer 604 is deposited in each trench 614. Afterwards the control gates 602 are formed, e.g. by depositing polysilicon onto the gate insulation layers 604. On top of the control gates 602 a control gate contact 603 is formed which electrically connects all control gates 602.
Finally, it should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be capable of designing many alternative embodiments without departing from the scope of the invention as defined by the appended claims. In the claims, any reference signs placed in parentheses shall not be construed as limiting the claims. The word "comprising" and "comprises", and the like, does not exclude the presence of elements or steps other than those listed in any claim or the specification as a whole. The singular reference of an element does not exclude the plural reference of such elements and vice-versa. In a device claim enumerating several means, several of these means may be embodied by one and the same item of software or hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

CLAIMS:
1. A planar extended drain transistor (100) comprising: a control gate (102); a drain region (109); a channel region (107); and a drift region (108), wherein the drift region (108) is arranged between the channel region (107) and the drain region (109); wherein the control gate (102) is at least partially buried into the channel region (107); and wherein the drift region (108) comprises a doping material density which is lower than the doping material density of the drain region (109).
2. The planar extended drain transistor according (100) to claim 1, further comprising: a control gate contact (103); and a source region (105), wherein the control gate contact (103) is electrically connected to the control gate (102) ; and wherein the source region (105) is at least partially arranged between the channel region (107) and the control gate contact (103).
3. The planar extended drain transistor (100) according claim 2, wherein the control gate (102) is formed by a layer, in particular, by a planar layer.
4. The planar extended drain transistor (200) according claim 2, further comprising: a plurality of control gates (202), wherein the control gates (202) have a substantially circular cross section.
5. The planar extended drain transistor (300) according claim 1, further comprising: a plurality of control gates (302), wherein the plurality of control gates (302) are arranged in a comb-like structure.
6. The planar extended drain transistor (300) according claim 5, further comprising: at least one control gate contact (303); and a source region (305), wherein the at least one control gate contact (303) is electrically connected to at least one of the plurality of control gates (302); and wherein the at least one control gate contact (303) is at least partially arranged between the drift region (307) and the source region (305).
7. A method of manufacturing a planar extended drain transistor (100), the method comprising: forming a semiconductor layer (413) on a substrate (401), wherein the semiconductor layer (413) has a first side which is in contact with the substrate and a second opposite side which forms a surface; forming a trench (414) into a first portion of the semiconductor layer (413) by removing parts of the semiconductor layer (413) in the first portion in such a way that at least a portion of the trench (414) below the surface of the semiconductor layer (413) is removed; forming a control gate (402) in the trench (414); forming a planar extended drain transistor (100) by forming a drain region, a source region, a drift region, and a channel region in the semiconductor layer, wherein the channel region is formed in the first portion in such a way that at least a portion of the control gate (402) is buried in the channel region.
8. The method according claim 7, further comprising: forming an intermediate layer (412) onto a second portion of the substrate (401); and forming the semiconductor layer (413) onto the substrate (401) and the intermediate layer (412) in such a way that the first portion of the semiconductor layer (413) is arranged on the intermediate layer (412).
9. The method according to claim 8, further comprising: forming of the trench (414) is done in such a way that the intermediate layer (412) is contacted by the trench (414).
10. The method according to claim 9, further comprising: forming a cavity by removing the intermediate layer (412) before the control gate (402) is formed.
11. The method according to claim 7, further comprising: forming a control gate contact which connects the control gate (402) formed in the trench (414), wherein the source region is formed at least partially between the channel region and the control gate contact.
12. The method according to claim 7, further comprising: forming a plurality of trenches (614) in the first portion of the semiconductor layer; and forming a plurality of control gates (602) in the plurality of trenches (614).
13. The method according to claim 12, further comprising: forming one control gate contact (603) contacting at least a number of the plurality of control gates (602) in the first portion of the semiconductor.
14. The method according to claim 12, further comprising: forming a plurality of tube-like cavities (515) from the plurality of trenches (514); and forming a plurality of control gates (502) in the plurality of tube-like cavities
15. The method according to claim 14, further comprising: forming a further trench into the semiconductor layer in such a way that at least a portion of each of the cavities (515) is exposed to the further trench.
PCT/IB2008/050893 2007-03-19 2008-03-12 Extended drain transistor with resecced gate and method of producing the same WO2008114167A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN2008800086433A CN101636844B (en) 2007-03-19 2008-03-12 Planar extended drain transistor and method of producing the same
US12/531,578 US8227857B2 (en) 2007-03-19 2008-03-12 Planar extended drain transistor and method of producing the same
EP08719651.5A EP2140495B1 (en) 2007-03-19 2008-03-12 Extended drain transistor with recessed gate and method of producing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP07104400 2007-03-19
EP07104400.2 2007-03-19

Publications (2)

Publication Number Publication Date
WO2008114167A2 true WO2008114167A2 (en) 2008-09-25
WO2008114167A3 WO2008114167A3 (en) 2009-03-12

Family

ID=39766562

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2008/050893 WO2008114167A2 (en) 2007-03-19 2008-03-12 Extended drain transistor with resecced gate and method of producing the same

Country Status (5)

Country Link
US (1) US8227857B2 (en)
EP (1) EP2140495B1 (en)
CN (1) CN101636844B (en)
TW (1) TW200849411A (en)
WO (1) WO2008114167A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8110470B2 (en) 2009-08-31 2012-02-07 Globalfoundries Singapore Pte. Ltd. Asymmetrical transistor device and method of fabrication

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7851857B2 (en) * 2008-07-30 2010-12-14 Freescale Semiconductor, Inc. Dual current path LDMOSFET with graded PBL for ultra high voltage smart power applications
US8816503B2 (en) * 2011-08-29 2014-08-26 Infineon Technologies Austria Ag Semiconductor device with buried electrode
EP2992026B1 (en) 2013-05-02 2019-04-03 Dow Global Technologies LLC Rapid drive away time adhesive for installing vehicle windows
US10833175B2 (en) * 2015-06-04 2020-11-10 International Business Machines Corporation Formation of dislocation-free SiGe finFET using porous silicon
CN110164958B (en) * 2019-04-25 2020-08-04 华东师范大学 Asymmetric reconfigurable field effect transistor
CN117276329A (en) * 2023-11-20 2023-12-22 深圳天狼芯半导体有限公司 LDMOS with trench gate and preparation method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040256693A1 (en) * 2003-05-07 2004-12-23 Tsutomu Sato Semiconductor device and method of manufacturing the same
WO2006082568A2 (en) * 2005-02-07 2006-08-10 Nxp B.V. Method of manufacturing a lateral semiconductor device
US20060261384A1 (en) * 2005-03-15 2006-11-23 Michael Rueb Lateral MISFET and method for fabricating it

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6118149A (en) * 1997-03-17 2000-09-12 Kabushiki Kaisha Toshiba Trench gate MOSFET
JP3405681B2 (en) * 1997-07-31 2003-05-12 株式会社東芝 Semiconductor device
KR100304717B1 (en) * 1998-08-18 2001-11-15 김덕중 Semiconductor device having a trench type gate and method for fabricating therefor
JP3356162B2 (en) * 1999-10-19 2002-12-09 株式会社デンソー Semiconductor device and manufacturing method thereof
US6642577B2 (en) * 2000-03-16 2003-11-04 Denso Corporation Semiconductor device including power MOSFET and peripheral device and method for manufacturing the same
JP3534084B2 (en) * 2001-04-18 2004-06-07 株式会社デンソー Semiconductor device and manufacturing method thereof
JP2003163225A (en) 2001-11-29 2003-06-06 Sony Corp Semiconductor device and manufacturing method therefor
KR100422393B1 (en) * 2002-01-17 2004-03-11 한국전자통신연구원 EDMOS device with the structure of lattice type drift region and method of manufacturing the same
KR100481209B1 (en) * 2002-10-01 2005-04-08 삼성전자주식회사 MOS Transistor having multiple channels and method of manufacturing the same
GB0225812D0 (en) * 2002-11-06 2002-12-11 Koninkl Philips Electronics Nv Semiconductor devices and methods of manufacturing thereof
DE10309400B4 (en) * 2003-03-04 2009-07-30 Infineon Technologies Ag Semiconductor device with increased dielectric strength and / or reduced on-resistance
DE10313712B4 (en) * 2003-03-27 2008-04-03 Infineon Technologies Ag Lateral field-controllable semiconductor device for RF applications
GB0314390D0 (en) * 2003-06-20 2003-07-23 Koninkl Philips Electronics Nv Trench field effect transistor structure
DE10339488B3 (en) * 2003-08-27 2005-04-14 Infineon Technologies Ag Lateral semiconductor component with at least one field electrode formed in drift zone extending laterally between doped terminal regions
KR100640616B1 (en) * 2004-12-21 2006-11-01 삼성전자주식회사 Field effect transistor structure comprising a buried gate pattern and method of manufacturing a semiconductor device comprising the field effect transistor structure
TWI283039B (en) * 2005-11-22 2007-06-21 Anpec Electronics Corp Gate contact structure of power device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040256693A1 (en) * 2003-05-07 2004-12-23 Tsutomu Sato Semiconductor device and method of manufacturing the same
WO2006082568A2 (en) * 2005-02-07 2006-08-10 Nxp B.V. Method of manufacturing a lateral semiconductor device
US20060261384A1 (en) * 2005-03-15 2006-11-23 Michael Rueb Lateral MISFET and method for fabricating it

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
NAKAGAWA A ET AL: "IMPROVED 20V LATERAL TRENCH GATE POWER MOSFETS WITH VERY LOW ON-RESISTANCE OF 7.8 MOHM.MM2" PROCEEDINGS OF THE 12TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD 2000), TOULOUSE, FR, MAY 22 - 25, 2000, 22 May 2000 (2000-05-22), - 25 May 2000 (2000-05-25) pages 47-50, XP000987831 IEEE, NEW YORK, NY, USA ISBN: 978-0-7803-6269-7 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8110470B2 (en) 2009-08-31 2012-02-07 Globalfoundries Singapore Pte. Ltd. Asymmetrical transistor device and method of fabrication
US8629503B2 (en) 2009-08-31 2014-01-14 Globalfoundries Singapore Pte. Ltd. Asymmetrical transistor device and method of fabrication

Also Published As

Publication number Publication date
EP2140495A2 (en) 2010-01-06
EP2140495B1 (en) 2017-11-08
US8227857B2 (en) 2012-07-24
CN101636844B (en) 2011-09-28
CN101636844A (en) 2010-01-27
TW200849411A (en) 2008-12-16
US20100096694A1 (en) 2010-04-22
WO2008114167A3 (en) 2009-03-12

Similar Documents

Publication Publication Date Title
JP6713453B2 (en) Method and apparatus for LDMOS devices with cascaded resurf injection and double buffer
US9024380B2 (en) Semiconductor device with floating RESURF region
US9257502B2 (en) Level shift power semiconductor device
US9601614B2 (en) Composite semiconductor device with different channel widths
US8227857B2 (en) Planar extended drain transistor and method of producing the same
US9165918B1 (en) Composite semiconductor device with multiple threshold voltages
JP2008182106A (en) Semiconductor device
US9728600B2 (en) Partially biased isolation in semiconductor devices
JP5432750B2 (en) Semiconductor device and manufacturing method of semiconductor device
KR20100079573A (en) Semiconductor device and method for manufacturing the same
EP3142150B1 (en) Partially biased isolation in semiconductor devices
CN104900700A (en) Semiconductor device
US9257517B2 (en) Vertical DMOS-field effect transistor
KR100684428B1 (en) High voltage transistor having low on-resistance and method for thereof
KR20110078621A (en) Semiconductor device, and fabricating method thereof
KR20060101262A (en) Semiconductor device and manufacturing method thereof
KR102374125B1 (en) Semiconductor Device having Vertical DMOS and Manufacturing Method Thereof
US10615079B2 (en) Semiconductor device and method for manufacturing the same
CN105793987A (en) Trench gate trench field plate semi-vertical semi-lateral MOSFET
KR100947941B1 (en) Semiconductor device and method for fabricating the same
JP2000260990A (en) High-voltage element and its manufacture
KR20100048061A (en) High-power semiconductor device having improved transconductance
US10062773B2 (en) Semiconductor device having a transistor and first and second embedded layers
JP2018011089A (en) Semiconductor device
KR102033445B1 (en) Power semiconductor device

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200880008643.3

Country of ref document: CN

WWE Wipo information: entry into national phase

Ref document number: 12531578

Country of ref document: US

REEP Request for entry into the european phase

Ref document number: 2008719651

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2008719651

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08719651

Country of ref document: EP

Kind code of ref document: A2