WO2008111171A1 - クロック冗長装置 - Google Patents
クロック冗長装置 Download PDFInfo
- Publication number
- WO2008111171A1 WO2008111171A1 PCT/JP2007/054947 JP2007054947W WO2008111171A1 WO 2008111171 A1 WO2008111171 A1 WO 2008111171A1 JP 2007054947 W JP2007054947 W JP 2007054947W WO 2008111171 A1 WO2008111171 A1 WO 2008111171A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- clock
- phase
- unit
- redundancy device
- clock redundancy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
入力クロックから冗長化されたクロックの位相をより正確に同期させるため、第1のユニットが、入力クロックを第1及び第2のクロックに分岐し、第2のユニットが、該第2のクロックを、該第1のユニットの影響を遮断するための第1の素子を経由して送出する。この際、該第1のユニットを構成する位相調整回路が、該第1のクロックの位相を、該第1の素子と同一の動作特性を有する第2の素子を通過する該第2のクロックの位相に合わせる。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2007/054947 WO2008111171A1 (ja) | 2007-03-13 | 2007-03-13 | クロック冗長装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2007/054947 WO2008111171A1 (ja) | 2007-03-13 | 2007-03-13 | クロック冗長装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2008111171A1 true WO2008111171A1 (ja) | 2008-09-18 |
Family
ID=39759122
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2007/054947 Ceased WO2008111171A1 (ja) | 2007-03-13 | 2007-03-13 | クロック冗長装置 |
Country Status (1)
| Country | Link |
|---|---|
| WO (1) | WO2008111171A1 (ja) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010206354A (ja) * | 2009-03-02 | 2010-09-16 | Furuno Electric Co Ltd | 基準周波数発生装置及び基準周波数発生システム |
| JP2010206355A (ja) * | 2009-03-02 | 2010-09-16 | Furuno Electric Co Ltd | 基準周波数発生システム及び基準周波数発生装置 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09214476A (ja) * | 1996-01-31 | 1997-08-15 | Nippon Telegr & Teleph Corp <Ntt> | 半導体集積回路 |
| JP2002135234A (ja) * | 2000-10-20 | 2002-05-10 | Mitsubishi Electric Corp | スキュー調整回路 |
-
2007
- 2007-03-13 WO PCT/JP2007/054947 patent/WO2008111171A1/ja not_active Ceased
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09214476A (ja) * | 1996-01-31 | 1997-08-15 | Nippon Telegr & Teleph Corp <Ntt> | 半導体集積回路 |
| JP2002135234A (ja) * | 2000-10-20 | 2002-05-10 | Mitsubishi Electric Corp | スキュー調整回路 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010206354A (ja) * | 2009-03-02 | 2010-09-16 | Furuno Electric Co Ltd | 基準周波数発生装置及び基準周波数発生システム |
| JP2010206355A (ja) * | 2009-03-02 | 2010-09-16 | Furuno Electric Co Ltd | 基準周波数発生システム及び基準周波数発生装置 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application |
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| 122 | Ep: pct application non-entry in european phase |
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