WO2008102558A1 - 多値検出回路 - Google Patents
多値検出回路 Download PDFInfo
- Publication number
- WO2008102558A1 WO2008102558A1 PCT/JP2008/000291 JP2008000291W WO2008102558A1 WO 2008102558 A1 WO2008102558 A1 WO 2008102558A1 JP 2008000291 W JP2008000291 W JP 2008000291W WO 2008102558 A1 WO2008102558 A1 WO 2008102558A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- input terminal
- output
- detecting circuit
- terminal
- value detecting
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M5/00—Conversion of the form of the representation of individual digits
- H03M5/02—Conversion to or from representation by pulses
- H03M5/16—Conversion to or from representation by pulses the pulses having three levels
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
- H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
- H03M1/362—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider
- H03M1/365—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider the voltage divider being a single resistor string
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Electronic Switches (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Logic Circuits (AREA)
- Manipulation Of Pulses (AREA)
Abstract
入力端子3に入力信号Inが入力され、電源端子1-入力端子3の間にスイッチ7と抵抗9が、接地端子2-入力端子3の間にスイッチ8と抵抗10が接続され、スイッチ7とスイッチ8との間に抵抗11~16が直列に接続され、入力端子3と抵抗11~16の各接続点はそれぞれ比較器17~21で比較され、各比較器17~21の出力はラッチ回路22によって符号化して出力される構成とすることにより、6値検出選択が可能であり、クロック信号に従った間欠動作により省電力の多値検出が可能となる。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007-041539 | 2007-02-22 | ||
JP2007041539A JP2008205976A (ja) | 2007-02-22 | 2007-02-22 | 多値検出回路 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2008102558A1 true WO2008102558A1 (ja) | 2008-08-28 |
Family
ID=39709838
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2008/000291 WO2008102558A1 (ja) | 2007-02-22 | 2008-02-21 | 多値検出回路 |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP2008205976A (ja) |
WO (1) | WO2008102558A1 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009094888A (ja) * | 2007-10-10 | 2009-04-30 | Rohm Co Ltd | 3値入力回路およびそれを用いた電源管理回路 |
JP2014135709A (ja) * | 2012-02-02 | 2014-07-24 | Toshiyasu Suzuki | 同期ラッチング機能を持つ多値論理手段、多値ハザード除去手段、多値even手段、多値neven手段、多値and手段、多値nand手段、多値or手段、多値nor手段、多値over手段、多値nover手段、多値and・over手段、多値nand・over手段、多値or・over手段、多値nor・over手段、多値under手段、多値nunder手段、多値and・under手段、多値nand・under手段、多値or・under手段、多値nor・under手段、多値and・nunder手段、多値nand・nunder手段、多値or・nunder手段、多値nor・nunder手段、多値and・nover手段、多値nand・nover手段、多値or・nover手段、多値nor・nover手段、多値in手段、多値nin手段、多値and・in手段、多値nand・in手段、多値or・in手段、多値nor・in手段、多値out手段、多値nout手段、多値and・out手段、多値nand・out手段、多値or・out手段、多値nor・out手段、値and・nin手段、多値nand・nin手段、多値or・nin手段、多値nor・nin手段、多値and・nout手段、多値nand・nout手段、多値or・nout手段、及び、多値nor・nout手段 |
JP2016091146A (ja) * | 2014-10-31 | 2016-05-23 | 京セラドキュメントソリューションズ株式会社 | 電子機器 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63312721A (ja) * | 1987-06-16 | 1988-12-21 | Sanyo Electric Co Ltd | 3値入力回路 |
JPH06152418A (ja) * | 1992-11-13 | 1994-05-31 | Kawasaki Steel Corp | 電圧分割回路 |
-
2007
- 2007-02-22 JP JP2007041539A patent/JP2008205976A/ja active Pending
-
2008
- 2008-02-21 WO PCT/JP2008/000291 patent/WO2008102558A1/ja active Application Filing
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63312721A (ja) * | 1987-06-16 | 1988-12-21 | Sanyo Electric Co Ltd | 3値入力回路 |
JPH06152418A (ja) * | 1992-11-13 | 1994-05-31 | Kawasaki Steel Corp | 電圧分割回路 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009094888A (ja) * | 2007-10-10 | 2009-04-30 | Rohm Co Ltd | 3値入力回路およびそれを用いた電源管理回路 |
JP2014135709A (ja) * | 2012-02-02 | 2014-07-24 | Toshiyasu Suzuki | 同期ラッチング機能を持つ多値論理手段、多値ハザード除去手段、多値even手段、多値neven手段、多値and手段、多値nand手段、多値or手段、多値nor手段、多値over手段、多値nover手段、多値and・over手段、多値nand・over手段、多値or・over手段、多値nor・over手段、多値under手段、多値nunder手段、多値and・under手段、多値nand・under手段、多値or・under手段、多値nor・under手段、多値and・nunder手段、多値nand・nunder手段、多値or・nunder手段、多値nor・nunder手段、多値and・nover手段、多値nand・nover手段、多値or・nover手段、多値nor・nover手段、多値in手段、多値nin手段、多値and・in手段、多値nand・in手段、多値or・in手段、多値nor・in手段、多値out手段、多値nout手段、多値and・out手段、多値nand・out手段、多値or・out手段、多値nor・out手段、値and・nin手段、多値nand・nin手段、多値or・nin手段、多値nor・nin手段、多値and・nout手段、多値nand・nout手段、多値or・nout手段、及び、多値nor・nout手段 |
JP2016091146A (ja) * | 2014-10-31 | 2016-05-23 | 京セラドキュメントソリューションズ株式会社 | 電子機器 |
Also Published As
Publication number | Publication date |
---|---|
JP2008205976A (ja) | 2008-09-04 |
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