WO2008096446A1 - 演算処理装置、情報処理装置、および演算方法 - Google Patents

演算処理装置、情報処理装置、および演算方法 Download PDF

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Publication number
WO2008096446A1
WO2008096446A1 PCT/JP2007/052396 JP2007052396W WO2008096446A1 WO 2008096446 A1 WO2008096446 A1 WO 2008096446A1 JP 2007052396 W JP2007052396 W JP 2007052396W WO 2008096446 A1 WO2008096446 A1 WO 2008096446A1
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WIPO (PCT)
Prior art keywords
rounding
region
outputs
carry
normalization
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Application number
PCT/JP2007/052396
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English (en)
French (fr)
Inventor
Kunihiko Tajiri
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to EP07714008.5A priority Critical patent/EP2110740B1/en
Priority to JP2008556965A priority patent/JP4806453B2/ja
Priority to PCT/JP2007/052396 priority patent/WO2008096446A1/ja
Publication of WO2008096446A1 publication Critical patent/WO2008096446A1/ja
Priority to US12/461,338 priority patent/US8554819B2/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G06F7/49947—Rounding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905—Exception handling
    • G06F7/4991—Overflow or underflow
    • G06F7/49915—Mantissa overflow or underflow in handling floating-point numbers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)

Abstract

　浮動小数点数の丸め処理に伴うキャリーアウトの発生を迅速に決定し、演算の高速化を図る。この課題を解決するため、ＬＺ予測器（１３０）は、絶対値加算器（１２０）による絶対値加算の演算結果から左シフト量を求め、左シフタ（１４０）および予測部（１６０）へ出力する。左シフタ（１４０）は、左シフト量だけ絶対値加算結果を左シフトし、正規化を行なう。予測部（１６０）は、領域１および領域２を構成する４ビット単位の各ブロックが、正規化後に丸め処理領域内に含まれるか否かを予測し、丸め処理領域内に含まれるビットすべてが１であるか否かを示す予測結果を出力する。ＣＯ検出部（１７０）は、予測部（１６０）による予測結果と左シフタ（１４０）による正規化結果の一部のビットとを用いて、丸め処理部（１５０）における丸め処理時のキャリーアウトの発生を検出し、キャリーアウトが発生する場合には１を出力する。
PCT/JP2007/052396 2007-02-09 2007-02-09 演算処理装置、情報処理装置、および演算方法 WO2008096446A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP07714008.5A EP2110740B1 (en) 2007-02-09 2007-02-09 Computation processor, information processor, and computing method
JP2008556965A JP4806453B2 (ja) 2007-02-09 2007-02-09 演算処理装置、情報処理装置、および演算方法
PCT/JP2007/052396 WO2008096446A1 (ja) 2007-02-09 2007-02-09 演算処理装置、情報処理装置、および演算方法
US12/461,338 US8554819B2 (en) 2007-02-09 2009-08-07 System to implement floating point adder using mantissa, rounding, and normalization

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/052396 WO2008096446A1 (ja) 2007-02-09 2007-02-09 演算処理装置、情報処理装置、および演算方法

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US12/461,338 Continuation US8554819B2 (en) 2007-02-09 2009-08-07 System to implement floating point adder using mantissa, rounding, and normalization

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WO2008096446A1 true WO2008096446A1 (ja) 2008-08-14

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Country Link
US (1) US8554819B2 (ja)
EP (1) EP2110740B1 (ja)
JP (1) JP4806453B2 (ja)
WO (1) WO2008096446A1 (ja)

Cited By (2)

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Publication number Priority date Publication date Assignee Title
JP2013543176A (ja) * 2010-09-24 2013-11-28 インテル コーポレイション Ｓｃａｌｅ、ｒｏｕｎｄ、ｇｅｔｅｘｐ、ｒｏｕｎｄ、ｇｅｔｍａｎｔ、ｒｅｄｕｃｅ、ｒａｎｇｅ及びｃｌａｓｓ命令を実行できる乗加算機能ユニット
JP2018097864A (ja) * 2016-12-06 2018-06-21 エイアールエム リミテッド リーディングゼロ予想

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US9929862B2 (en) 2013-12-23 2018-03-27 Nxp B.V. Optimized hardware architecture and method for ECC point doubling using Jacobian coordinates over short Weierstrass curves
US9900154B2 (en) 2013-12-23 2018-02-20 Nxp B.V. Optimized hardward architecture and method for ECC point addition using mixed affine-jacobian coordinates over short weierstrass curves
US9979543B2 (en) * 2013-12-23 2018-05-22 Nxp B.V. Optimized hardware architecture and method for ECC point doubling using jacobian coordinates over short weierstrass curves
US10489114B2 (en) 2014-06-27 2019-11-26 International Business Machines Corporation Shift amount correction for multiply-add

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JPH1040078A (ja) 1996-07-24 1998-02-13 Hitachi Ltd 先行０、１数予測回路、浮動小数点演算装置、マイクロプロセッサおよび情報処理装置
JP2005134965A (ja) * 2003-10-28 2005-05-26 Renesas Technology Corp 論理回路、および、それを使用した浮動小数点演算回路とマイクロプロセッサ

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JPH0695851A (ja) * 1991-08-30 1994-04-08 Weytec Corp 浮動小数点加算器用の正確な先行ゼロ予測のための方法及び装置
JPH1040078A (ja) 1996-07-24 1998-02-13 Hitachi Ltd 先行０、１数予測回路、浮動小数点演算装置、マイクロプロセッサおよび情報処理装置
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See also references of EP2110740A4

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013543176A (ja) * 2010-09-24 2013-11-28 インテル コーポレイション Ｓｃａｌｅ、ｒｏｕｎｄ、ｇｅｔｅｘｐ、ｒｏｕｎｄ、ｇｅｔｍａｎｔ、ｒｅｄｕｃｅ、ｒａｎｇｅ及びｃｌａｓｓ命令を実行できる乗加算機能ユニット
US8914430B2 (en) 2010-09-24 2014-12-16 Intel Corporation Multiply add functional unit capable of executing scale, round, GETEXP, round, GETMANT, reduce, range and class instructions
US9606770B2 (en) 2010-09-24 2017-03-28 Intel Corporation Multiply add functional unit capable of executing SCALE, ROUND, GETEXP, ROUND, GETMANT, REDUCE, RANGE and CLASS instructions
US10318244B2 (en) 2010-09-24 2019-06-11 Intel Corporation Multiply add functional unit capable of executing scale, round, getexp, round, getmant, reduce, range and class instructions
US10649733B2 (en) 2010-09-24 2020-05-12 Intel Corporation Multiply add functional unit capable of executing scale, round, getexp, round, getmant, reduce, range and class instructions
JP2018097864A (ja) * 2016-12-06 2018-06-21 エイアールエム リミテッド リーディングゼロ予想
JP7044528B2 (ja) 2016-12-06 2022-03-30 アーム・リミテッド リーディングゼロ予想

Also Published As

Publication number Publication date
EP2110740A1 (en) 2009-10-21
US20090300087A1 (en) 2009-12-03
EP2110740A4 (en) 2011-07-27
JP4806453B2 (ja) 2011-11-02
EP2110740B1 (en) 2013-05-29
JPWO2008096446A1 (ja) 2010-05-20
US8554819B2 (en) 2013-10-08

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