WO2008089725A3 - Elektrisches bauelement mit einem trägersubstrat und einem halbleiter-chip - Google Patents

Elektrisches bauelement mit einem trägersubstrat und einem halbleiter-chip Download PDF

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Publication number
WO2008089725A3
WO2008089725A3 PCT/DE2008/000065 DE2008000065W WO2008089725A3 WO 2008089725 A3 WO2008089725 A3 WO 2008089725A3 DE 2008000065 W DE2008000065 W DE 2008000065W WO 2008089725 A3 WO2008089725 A3 WO 2008089725A3
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WO
WIPO (PCT)
Prior art keywords
section
carrier substrate
semiconductor chip
electrical component
allocated
Prior art date
Application number
PCT/DE2008/000065
Other languages
English (en)
French (fr)
Other versions
WO2008089725A2 (de
Inventor
Peter Stoehr
Patric Heide
Johann Heyen
Kostyantyn Markov
Original Assignee
Epcos Ag
Peter Stoehr
Patric Heide
Johann Heyen
Kostyantyn Markov
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Epcos Ag, Peter Stoehr, Patric Heide, Johann Heyen, Kostyantyn Markov filed Critical Epcos Ag
Priority to JP2009545817A priority Critical patent/JP5295125B2/ja
Publication of WO2008089725A2 publication Critical patent/WO2008089725A2/de
Publication of WO2008089725A3 publication Critical patent/WO2008089725A3/de
Priority to US12/503,651 priority patent/US7952197B2/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/0538—Constructional combinations of supports or holders with electromechanical or other electronic elements
    • H03H9/0566—Constructional combinations of supports or holders with electromechanical or other electronic elements for duplexers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/07—Electric details
    • H05K2201/0707—Shielding
    • H05K2201/0723—Shielding provided by an inner layer of PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09972—Partitioned, e.g. portions of a PCB dedicated to different functions; Boundary lines therefore; Portions of a PCB being processed separately or differently

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Materials Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Acoustics & Sound (AREA)
  • Geometry (AREA)
  • Transceivers (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Wire Bonding (AREA)

Abstract

Es wird ein elektrisches Bauelement mit einem Trägersubstrat (100) angegeben, auf dem mindestens ein Halbleiter-Chip (202, 202') befestigt ist. Auf der Unterseite des Trägersubstrats (100) sind Anschlussflächen (141) und auf der Oberseite Kontaktflächen (142) angeordnet, die zur Bestückung mit Halbleiter-Chips (202, 202') vorgesehen sind. Das Trägersubstrat (100) hat einen Funktionsbereich (102), der in Sektionen (111-116) aufgeteilt ist, wobei jeder Sektion mindestens eine Funktion z. B. als Filter, Frequenzweiche, Balun usw. zugewiesen ist. Jeder Sektion (111-116) ist ein eigener Bereich des Trägersubstrats (100) zugewiesen. Für mindestens eine der Sektionen gilt: die Kontaktfläche und/oder die Anschlussfläche, die mit der Sektion leitend verbunden ist, liegt außerhalb der Grundfläche dieser Sektion. Die Verbindungsleitung, die den Ein- bzw. Ausgang der jeweiligen Sektion mit der Kontaktfläche und/oder der Anschlussfläche leitend verbindet, ist vorzugsweise von der Sektion durch eine Massefläche abgeschirmt.
PCT/DE2008/000065 2007-01-22 2008-01-16 Elektrisches bauelement mit einem trägersubstrat und einem halbleiter-chip WO2008089725A2 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009545817A JP5295125B2 (ja) 2007-01-22 2008-01-16 電気コンポーネント
US12/503,651 US7952197B2 (en) 2007-01-22 2009-07-15 Electrical component

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102007003182.5A DE102007003182B4 (de) 2007-01-22 2007-01-22 Elektrisches Bauelement
DE102007003182.5 2007-01-22

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/503,651 Continuation US7952197B2 (en) 2007-01-22 2009-07-15 Electrical component

Publications (2)

Publication Number Publication Date
WO2008089725A2 WO2008089725A2 (de) 2008-07-31
WO2008089725A3 true WO2008089725A3 (de) 2009-05-07

Family

ID=39284026

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2008/000065 WO2008089725A2 (de) 2007-01-22 2008-01-16 Elektrisches bauelement mit einem trägersubstrat und einem halbleiter-chip

Country Status (4)

Country Link
US (1) US7952197B2 (de)
JP (1) JP5295125B2 (de)
DE (1) DE102007003182B4 (de)
WO (1) WO2008089725A2 (de)

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US20120061789A1 (en) * 2010-09-13 2012-03-15 Omnivision Technologies, Inc. Image sensor with improved noise shielding
US9230889B2 (en) * 2013-01-16 2016-01-05 Infineon Technologies Ag Chip arrangement with low temperature co-fired ceramic and a method for forming a chip arrangement with low temperature co-fired ceramic
ITMI20130872A1 (it) * 2013-05-29 2013-08-28 Mavel Srl Dispositivo elettronico comprendente un circuito stampato
JP6019367B2 (ja) * 2015-01-13 2016-11-02 株式会社野田スクリーン 半導体装置
DE102015104641A1 (de) * 2015-03-26 2016-09-29 At & S Austria Technologie & Systemtechnik Ag Träger mit passiver Kühlfunktion für ein Halbleiterbauelement
KR20170056391A (ko) * 2015-11-13 2017-05-23 삼성전기주식회사 프론트 엔드 모듈
DE102018127075B4 (de) * 2018-10-30 2021-12-30 Auto-Kabel Management Gmbh Hochstromschaltung
DE102020105005A1 (de) * 2020-02-26 2021-08-26 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Substrat und halbleiterlaser

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Also Published As

Publication number Publication date
DE102007003182A1 (de) 2008-07-24
JP5295125B2 (ja) 2013-09-18
WO2008089725A2 (de) 2008-07-31
US7952197B2 (en) 2011-05-31
JP2010517252A (ja) 2010-05-20
US20090321917A1 (en) 2009-12-31
DE102007003182B4 (de) 2019-11-28

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