WO2008078098A1 - Systèmes de traitement acceptant des nombres exceptionnels - Google Patents

Systèmes de traitement acceptant des nombres exceptionnels Download PDF

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Publication number
WO2008078098A1
WO2008078098A1 PCT/GB2007/004956 GB2007004956W WO2008078098A1 WO 2008078098 A1 WO2008078098 A1 WO 2008078098A1 GB 2007004956 W GB2007004956 W GB 2007004956W WO 2008078098 A1 WO2008078098 A1 WO 2008078098A1
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WO
WIPO (PCT)
Prior art keywords
numbers
output
input
bits
group
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Application number
PCT/GB2007/004956
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English (en)
Inventor
Oswaldo Cadenas
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The University Of Reading
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Publication of WO2008078098A1 publication Critical patent/WO2008078098A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905—Exception handling
    • G06F7/4991—Overflow or underflow
    • G06F7/49921—Saturation, i.e. clipping the result to a minimum or maximum value
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905—Exception handling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel

Definitions

  • the present invention relates to processing systems and in particular to processing systems for performing arithmetical and other mathematical functions.
  • Processors are generally made up of a very large number of processing sub-systems or units each of which performs a simple operation. These units are grouped into larger units each of which is arranged to perform a specific task. These larger units are then themselves arranged to cooperate to perform the highly complex functions of which processors are capable.
  • transreal number system which uses a set of transreal numbers, the set including a series of real or rational numbers, positive infinity + ⁇ , negative infinity -oo and nullity ⁇ .
  • the present invention aims to provide a processing system that is suitable for use with such a transreal number system.
  • the present invention therefore provides a processing system comprising input means arranged to receive at least one input group of bits representing at least one respective input number and output means arranged to output at least one output group of bits representing at least one output number and processing means arranged to perform an operation on the at least one input groups of bits to produce the at least one output group of bits such that the at least one output number is related to the at least one input number by a mathematical operation, and wherein each of the numbers can be any of a set of numbers which includes a series of numbers, positive infinity, negative infinity and nullity.
  • the processing means may be implemented in hardware and comprise a plurality of hardware components.
  • the present invention therefore further provides a processing circuit comprising an input arranged to receive at least one input group of bits representing at least one respective input number, and an output arranged to output at least one output group of bits representing at least one output number, and a plurality of circuit components arranged to perform an operation on the at least one input groups of bits to produce the at least one output group of bits such that the at least one output number is related to the at least one input number by a mathematical operation, and wherein each of the numbers can be any of a set of numbers which includes a series of numbers, positive infinity, negative infinity and nullity.
  • the circuit components may be electronic components where the circuit is an electronic circuit, or may be optical components where the circuit is implemented optically.
  • Each group of bits may include a predetermined number p of bits, and the sequence or pattern of bits within the group may determine the number that the group represents.
  • the system may effectively define which numbers are represented by each of a set of bit sequences, and be arranged to generate the output bit group(s) or sequence(s) as determined from the input bit group(s) or sequence(s) using the numbers associated with the bit sequences and the mathematical operation as performed on the input numbers.
  • the system will of course generally be arranged to perform the same mathematical operation, for example addition, or multiplication, whatever the input numbers are.
  • the series of numbers may include zero, positive numbers from 1 to a maximum positive number and negative numbers from -1 to a maximum negative number.
  • each group may have p bits and each number value within the series of numbers n may be within the range:
  • the sequence of bits within the group varies in a regular progression, for example according to a predetermined set of rules, from each number in the series to the next, and wherein the sequences corresponding to the numbers -2 p l , -2 p l + 1 , and 2 p l -l are each reserved to represent one of: positive infinity, negative infinity and nullity.
  • the series of numbers can conveniently be represented using two's complement format. Other formats can also be used.
  • sequences corresponding to the numbers 2 p l -l , -2 p l + 1 and -2 p l are preferably arranged to represent positive infinity, negative infinity and nullity respectively.
  • the mathematical operation may be addition, or it may be multiplication, or any other suitable operation.
  • the processing means is preferably arranged to meet one or more of the following conditions which are required in transreal addition: that if either of the input numbers is nullity, then the output number is nullity; that if one of the input numbers is positive infinity then the output number is positive infinity; that if one of the input numbers is negative infinity then the output number is negative infinity; and that if the input numbers are positive infinity and negative infinity then the output number is nullity.
  • these conditions may be subject to one or more others.
  • the second and third may be subject to the fourth.
  • Figure 1 is a functional diagram of an adder according to a first embodiment of the invention
  • Figure 2 is a block diagram of the adder of Figure 1 ;
  • Figure 3 is a logic diagram of a two's complement adder forming part of the adder of Figure 1 ;
  • Figure 4 is a block diagram of the addition checker forming part of the adder of Figure 1 ;
  • FIG. 5 is a logic diagram of the addition checker of Figure 4.
  • Figure 6 is a circuit diagram of the addition checker of Figure 4.
  • Figure 7 is a block diagram of a case detector forming part of the adder of Figure 1;
  • Figures 8 to 10 are circuit diagrams of circuits providing different parts of the functionality of the case detector of Figure 7; .
  • Figure 11 is a circuit diagram of a circuit providing the "CO" output of
  • Figure 12 is a circuit diagram of a circuit providing the "Cl " output of Figure 7;
  • Figure 13 is a circuit diagram of a circuit providing the "C2" output of Figure 7;
  • Figure 14 is a circuit diagram of a circuit providing the "other" output of Figure 7;
  • Figure 15 is a circuit diagram of the whole of the case detector of Figure 7.
  • Figure 16 is a circuit diagram of the whole of the adder of Figure 1.
  • a binary number uses a base 2 notation, (our decimal system use base 10) .
  • An integer number N is represented, in the binary system, by a string of binary digits d p (that can take either 0 or 1) of length /?, provided the number being represented N is within the range determined by:
  • Table 1 Two's complement binary encoding for a 4-bit code.
  • Two's complement has a unique bit pattern for each positive and negative number within the range. There is a unique representation of zero (that for convention we have listed under positive numbers) . Note that there is a negative number (-8) in the table that does not have a positive counterpart representation within the range.
  • Two's complement can be extended to any number of p bits, preserving the above properties, with a well defined mechanism for assigning the bit patterns for each integer number within the range of representation.
  • Two's complement representation is very convenient for hardware implementation of arithmetic circuits, especially for adding and subtracting since both operations can be performed with the same circuitry.
  • the two's complement system of number representation is modified for a transreal number system which uses a set of transreal numbers, the set including a series of real or rational numbers, positive infinity (PINFINITY) + ⁇ , negative infinity (NINFINITY) -oo and nullity ⁇ .
  • the transreal number system is defined by a number of axioms. These include the following relating to Nullity: Nullity is the result of subtracting infinity from infinity; Nullity is the result of multiplying infinity by zero; the result of adding any real number to Nullity is Nullity, the result of multiplying any number by Nullity is Nullity.
  • any of the bit patterns can be reserved, but it is found to be particularly convenient, in a />-digit two's complement binary coding system, to reserve the numbers -2 P ', -2 p l + 1 , and 2 P '-1 for this purpose.
  • These reserved codes are therefore the sequence comprising a '0' followed by (p-1) l 's, the sequence comprising a ' 1 ' at each end with (p-2) O's in between, and a ' 1 ' followed by (p-1) O's.
  • This gives rise, for a p 4 system, to a binary coding system as indicated in Table 2 below, in which 0 is included in the list of positive numbers for convenience.
  • each positive number in the range 2 p l -2 has the same code representation as its equivalent two's complement counterpart.
  • each negative numbers in the range -2 p l + 2 has the same code representation as its equivalent two's complement counterpart.
  • the code 0111... (a most significant bit of 0 followed by p-1 consecutive bits in 1 ) is reserved, in this case for
  • the code 1000..1 (a most significant bit of 1 followed by p-2 consecutive bits in 0, ending in a least significant bit of 1) is reserved, in this case for NINFINITY.
  • the code 1000... (a most significant bit of 1 followed by p-1 consecutive bits in 0) is reserved, in this case for NULLITY.
  • p will be much greater than 4, which is uspd only for illustrative purposes herein . Typical values are 32 or 64. However, the system described above can be used for any value of p greater than 2.
  • this operation will always generate an overflow, i.e. the number which is the result of the operation requires more than p bits to code it.
  • overflow i.e. the number which is the result of the operation requires more than p bits to code it.
  • mechanisms to detect overflow in two's complement are well known, implementing this transreal case is relatively simple.
  • PINFINITY has the pattern that, in normal two's complement, is iarger than the largest of the set of non-reserved numbers
  • NINFINITY has the pattern that, in normal two's complement, is less than (more negative than) the lowest (most negative) of the set of non-reserved numbers. This means that the system preserves the piecewise topology of the transreal number line in the lexical ordering of bits. This can be exploited in hashing algorithms, search algorithms and similar types of algorithm for which PINFINTIY and NINFINITY are preferably treated as the highest and lowest numbers respectively.
  • the chosen binary assignment of the three special numbers in Transreal arithmetic is convenient from an implementation viewpoint since it facilitates the handling of special cases in Transreal arithmetic not found in the standard two's complement system.
  • the convenience comes from using known facts of two's complement arithmetic to reduce the complexity when implementing these Transreal special cases.
  • an adder based on the encoding in Table 2 is built similar to a standard adder in two's complement binary. For all cases where Transreal two's complement and standard two's complement agree in code representation, there is no difference required to perform the operation and the standard two's complement addition can be used. However a Transreal two's complement has to meet special considerations defined by the Transreal addition for Transreal number (TN) inputs TNl and TN2 defined in Table 3. In Table 3 each cell gives the result of addition of the number at the top of its column and the number at the left hand end of its row.
  • Case 0 This is managed by a hardware detection mechanism arranged to detect when one input is a NULLITY value and set the output to NULLITY. This can be performed by setting an internal hardware flag that gets activated when either TNl or TN2 is equal to NULLITY.
  • Case 1 This is managed by a hardware detection mechanism arranged to detect when one input is a PINFINITY value and, subject to Case 3, set the output to PINFINITY. This can be performed by setting an internal hardware flag that gets activated when either TNl or TN2 is equal to PINFINITY.
  • Case 2 This is managed by a hardware detection mechanism arranged to detect when one input is a NINFINITY value and, subject to Case 3, set the output to NINFINITY. This can be performed by setting an internal hardware flag that gets activated when either TNl or TN2 is equal to NINFINITY.
  • Case 3 This is managed by a hardware detection mechanism arranged to detect when both conditions for Case 1 and Case 2 above get activated at the same time, and set the output to NULLITY.
  • a normal two's complement addition is performed by the two's complement adder 10. That addition is checked by the mechanism described in the caveats above by the addition checker 12.
  • the inputs TNl , TN2 are also fed into the case detector 14 to determine the special cases CO, Cl and C2, while a final block 16 selects the correct output as the final addition among possible outputs of: two's complement addition ("other") , NULLITY value (when CO or both Cl and C2 was detected) , PINFINITY (Cl) or NINFINITY (C2) .
  • Two's complement ADDER 10 is a standard two's complement adder. This is very well known and it is not explained in more detail here.
  • Selector 16 represents a standard data selector. The role follows the following selection priority: - When the condition CO is active, the output TNR becomes NULLITY. C3 condition has been merged within condition CO, since both must produce the same result.
  • TNR output becomes PINFINITY.
  • condition C2 When the condition C2 is active (provided CO and Cl are both not active, which is satisfied trivially elsewhere) the output TNR becomes NINFINITY.
  • the functions outlined above are performed by a number of hardware components, with the Os and Is represented by different respective states of input or memory devices. The functions may be carried out in parallel by a combination of components, and the components may therefore not be divided into groups corresponding to the functions that they perform. The only requirement is that the output of the adder takes the required form for each of the possible combinations of inputs.
  • the addition checker has two 1-bit inputs "tr a msb" and "tr b msb” . These stand for the most significant bits of the two Transreal operands TNl and TN2 of Figure 1.
  • the /?-bits wide input “tr y” is the two's complement addition of TNl and TN2 generated by the "Two's complement ADDER” box in Figure 1.
  • the single /7-bit output "tr y checked” is the Transreal rectification performed by the block on the "tr y" input.
  • the rectangle on the right is a common data selector with three selections bits: “overflow”, “tr_a_msb” and “tr b msb”; when these are "100,” for example, the input PINF is selected and sent to the output "tr y checked".
  • PINF, NINF and NULY are synonyms for PINFINITY, NINFINITY and NULLITY respectively.
  • the case detector takes the two full length Transreal inputs TNl and TN2 from Figure 1; these are marked as “tr a” and “tr b” respectively.
  • Four 1-bit outputs are generated “CO”, “Cl”, “C2” and “other”.
  • the operation of the case detector depends on detecting as individual signals the conditions when:
  • Either "tr a” or “tr b” is PINF. This is referred to as “one is PINF”.
  • Either "tr a” or “tr_b” is NINF. This is referred to as “one_is_NINF” .
  • Output CO A schematic for this output is shown in Figure 11. Note that this depends only on condition "one_is_NULY. 10
  • Output Cl A schematic for this output is shown in Figure 12.
  • Output C2 A schematic for this output is shown in Figure 13.
  • the processing system is a multiplier comprising a number of hardware components arranged to perform multiplication of two input Transreal numbers to produce a Transreal result.
  • the multiplier of this embodiment includes the functionality of a two's complement multiplier with further circuitry arranged to perform further checking on the outputs of the two's complement multiplier and, when the appropriate conditions apply, produce a different output according to the rules of Transreal multiplication. Table 4 below shows the outputs required from the Transreal multiplier as compared to a normal two's complement multiplier, using the same notation as in Table 3 above.
  • NINFINITY The output is NINFINITY. This happens on a list of different subcases. -One input is PINFINITY while the other is NINFINITY. -One input is PINFINITY, the other negative Transreal. - One input is NINFINITY, the other positive Transreal.
  • Transreal - b is PNUM: that determines when the second input is positive
  • NULLITY For example for 4-bits NULLITY is 1000. This in normal two's complement is a negative number. So it is possible, in the two's complement domain (that is the frontend to the transreal multiplier) , to multiply one negative number and one positive number and get as a result the negative number 1000 (which in the Transreal multiplier is reserved as the NULLITY code) . This must not be confused with a genuine NULLITY. This condition is checked for, and responded to, in a module inside the multiplier that checks the plain response from the two's complement multiplier.
  • the functionality described above for the Transreal multiplier can be implemented in hardware in a corresponding manner to the Transreal adder, and in this embodiment the same coding as outlined in Table 2 is again used, giving the same advantages as it does for the adder.
  • the circuitry can comprise, in functional terms, a two's complement multiplier, and a multiplication checker to provide the caveats described above, case detector, and selector, each performing corresponding functions to those of the adder of Figure 1. It will also be appreciated that circuits for other mathematical operations can also be designed in the same manner.
  • Some of these will have two inputs and one output, as with the adder and multiplier, but others will have, for example, only one input and one output, for example a circuit arranged to square an input number, or find the integer part of an input number. Still others may have more outputs, for example a circuit arranged to output the square root of an input number can output positive and negative square roots, or the outputs may be the solutions to a simple equation defined by the inputs, in which case there could be one, two or more inputs, and one, two or more outputs.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

La présente invention concerne un système de traitement qui comporte : - un moyen d'entrée agencé pour recevoir au moins un groupe d'entrée de bits représentant au moins un nombre d'entrée respectif, - un moyen de traitement placé pour réaliser une opération sur au moins un groupe d'entrées de bits pour produire au moins un groupe de sortie de bits, de sorte qu'un nombre de sorties soit lié à au moins un nombre d'entrées par une opération mathématique. Chaque nombre peut être n'importe quel nombre parmi un ensemble qui comprend une série de nombres, une infinité positive, une infinité négative et une nullité.
PCT/GB2007/004956 2006-12-22 2007-12-21 Systèmes de traitement acceptant des nombres exceptionnels WO2008078098A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0625735A GB0625735D0 (en) 2006-12-22 2006-12-22 Processing systems
GB0625735.6 2006-12-22

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997012316A1 (fr) * 1995-09-26 1997-04-03 Advanced Micro Devices, Inc. Unite centrale en virgule flottante avec forçage de resultats mathematiques
EP1058185A1 (fr) * 1999-05-31 2000-12-06 Motorola, Inc. Un appareil de multiplication et d'accumulation et son procédé
US20020178202A1 (en) * 2001-05-25 2002-11-28 Sun Microsystems, Inc. Floating point multiplier for delimited operands
US20050210089A1 (en) * 2004-03-19 2005-09-22 Arm Limited Saturating shift mechanisms within data processing systems

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997012316A1 (fr) * 1995-09-26 1997-04-03 Advanced Micro Devices, Inc. Unite centrale en virgule flottante avec forçage de resultats mathematiques
EP1058185A1 (fr) * 1999-05-31 2000-12-06 Motorola, Inc. Un appareil de multiplication et d'accumulation et son procédé
US20020178202A1 (en) * 2001-05-25 2002-11-28 Sun Microsystems, Inc. Floating point multiplier for delimited operands
US20050210089A1 (en) * 2004-03-19 2005-09-22 Arm Limited Saturating shift mechanisms within data processing systems

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