WO2008067636A1 - Appareil et procédé permettant de communiquer avec des dispositifs à semi-conducteur d'une interconnexion série - Google Patents

Appareil et procédé permettant de communiquer avec des dispositifs à semi-conducteur d'une interconnexion série Download PDF

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Publication number
WO2008067636A1
WO2008067636A1 PCT/CA2007/002092 CA2007002092W WO2008067636A1 WO 2008067636 A1 WO2008067636 A1 WO 2008067636A1 CA 2007002092 W CA2007002092 W CA 2007002092W WO 2008067636 A1 WO2008067636 A1 WO 2008067636A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
master
clock signal
clock
data
Prior art date
Application number
PCT/CA2007/002092
Other languages
English (en)
Inventor
Hakjune Oh
Hong Beom Pyeon
Jin-Ki Kim
Original Assignee
Mosaid Technologies Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/771,023 external-priority patent/US8433874B2/en
Priority claimed from US11/771,241 external-priority patent/US7925854B2/en
Priority claimed from US11/942,173 external-priority patent/US7752364B2/en
Application filed by Mosaid Technologies Incorporated filed Critical Mosaid Technologies Incorporated
Publication of WO2008067636A1 publication Critical patent/WO2008067636A1/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

Un contrôleur de système communique avec des dispositifs dans une interconnexion série. Le contrôleur de système envoie une instruction de commande en lecture, une adresse de dispositif identifiant un dispositif cible dans l'interconnexion série et un emplacement mémoire. Le dispositif cible répond à l'instruction de commande en lecture de lire des données à l'emplacement identifié par l'emplacement mémoire. Des données lues sont fournies sous la forme d'un signal de sortie qui est transmis depuis un dernier dispositif dans l'interconnexion série vers un module de réception de données du contrôleur. Le module de réception de données établit des périodes d'acquisition en relation avec des signaux d'horloge en prenant en compte un temps de latence de transfert total dans l'interconnexion série. Lorsque chaque dispositif est doté d'un synchroniseur d'horloge, un signal d'horloge propagé à travers l'interconnexion série est utilisé pour établir les périodes d'acquisition. Les données lues sont verrouillées en réponse aux périodes d'acquisition établies en prenant en compte le temps de latence de transfert, des données valides sont verrouillées dans le module de réception de données.
PCT/CA2007/002092 2006-12-06 2007-11-20 Appareil et procédé permettant de communiquer avec des dispositifs à semi-conducteur d'une interconnexion série WO2008067636A1 (fr)

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
US86877306P 2006-12-06 2006-12-06
US60/868,773 2006-12-06
US89093507P 2007-02-21 2007-02-21
US60/890,935 2007-02-21
US11/771,023 US8433874B2 (en) 2006-12-06 2007-06-29 Address assignment and type recognition of serially interconnected memory devices of mixed type
US11/771,241 US7925854B2 (en) 2006-12-06 2007-06-29 System and method of operating memory devices of mixed type
US11/771,023 2007-06-29
US11/771,241 2007-06-29
US11/942,173 2007-11-19
US11/942,173 US7752364B2 (en) 2006-12-06 2007-11-19 Apparatus and method for communicating with semiconductor devices of a serial interconnection

Publications (1)

Publication Number Publication Date
WO2008067636A1 true WO2008067636A1 (fr) 2008-06-12

Family

ID=39491595

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CA2007/002092 WO2008067636A1 (fr) 2006-12-06 2007-11-20 Appareil et procédé permettant de communiquer avec des dispositifs à semi-conducteur d'une interconnexion série

Country Status (1)

Country Link
WO (1) WO2008067636A1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7752364B2 (en) 2006-12-06 2010-07-06 Mosaid Technologies Incorporated Apparatus and method for communicating with semiconductor devices of a serial interconnection
US7836340B2 (en) 2007-11-15 2010-11-16 Mosaid Technologies Incorporated Methods and systems for failure isolation and data recovery in a configuration of series-connected semiconductor devices
US7865756B2 (en) 2007-03-12 2011-01-04 Mosaid Technologies Incorporated Methods and apparatus for clock signal synchronization in a configuration of series-connected semiconductor devices
US8825967B2 (en) 2011-12-08 2014-09-02 Conversant Intellectual Property Management Inc. Independent write and read control in serially-connected devices
US8837655B2 (en) 2007-12-14 2014-09-16 Conversant Intellectual Property Management Inc. Memory controller with flexible data alignment to clock
CN109391308A (zh) * 2017-08-04 2019-02-26 维沃移动通信有限公司 一种天线波束切换感测系统、方法及移动终端

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5729683A (en) * 1995-05-18 1998-03-17 Compaq Computer Corporation Programming memory devices through the parallel port of a computer system
US5768173A (en) * 1995-11-11 1998-06-16 Samsung Electronics Co., Ltd. Memory modules, circuit substrates and methods of fabrication therefor using partially defective memory devices
US6144576A (en) * 1998-08-19 2000-11-07 Intel Corporation Method and apparatus for implementing a serial memory architecture

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5729683A (en) * 1995-05-18 1998-03-17 Compaq Computer Corporation Programming memory devices through the parallel port of a computer system
US5768173A (en) * 1995-11-11 1998-06-16 Samsung Electronics Co., Ltd. Memory modules, circuit substrates and methods of fabrication therefor using partially defective memory devices
US6144576A (en) * 1998-08-19 2000-11-07 Intel Corporation Method and apparatus for implementing a serial memory architecture

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7752364B2 (en) 2006-12-06 2010-07-06 Mosaid Technologies Incorporated Apparatus and method for communicating with semiconductor devices of a serial interconnection
US7865756B2 (en) 2007-03-12 2011-01-04 Mosaid Technologies Incorporated Methods and apparatus for clock signal synchronization in a configuration of series-connected semiconductor devices
US7836340B2 (en) 2007-11-15 2010-11-16 Mosaid Technologies Incorporated Methods and systems for failure isolation and data recovery in a configuration of series-connected semiconductor devices
US8837655B2 (en) 2007-12-14 2014-09-16 Conversant Intellectual Property Management Inc. Memory controller with flexible data alignment to clock
US8825967B2 (en) 2011-12-08 2014-09-02 Conversant Intellectual Property Management Inc. Independent write and read control in serially-connected devices
CN109391308A (zh) * 2017-08-04 2019-02-26 维沃移动通信有限公司 一种天线波束切换感测系统、方法及移动终端

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