WO2008059686A1

WO2008059686A1 - Substrate processing method and substrate processing system

Info

Publication number: WO2008059686A1
Application number: PCT/JP2007/070185
Authority: WO
Inventors: Yuichi Yamamoto
Original assignee: Tokyo Electron Limited
Priority date: 2006-11-14
Filing date: 2007-10-16
Publication date: 2008-05-22
Also published as: TWI355020B; TW200834658A; JP4548735B2; KR101252899B1; KR20090089288A; JP2008124291A

Abstract

Deterioration of throughput of a device in lithography process due to microminiaturization is prevented, cost is reduced and patterning dimensional accuracy is improved for microminiaturization. A substrate processing method has a lithography process of forming a prescribed pattern on a semiconductor wafer (W) by a substrate processing system by performing at least lithography steps, such as resist coating (COT), exposure (EXP), post-exposure heat treatment (PEB) and development (DEV),; an etching (ET) process wherein the developed pattern is used as a mask; and a measuring process of measuring the line width of a pattern. Based on the measurement information obtained by the measuring process, exposure correction for exposure in second and subsequent lithography process, temperature correction for post-exposure heat treatment and/or etching correction for the etching process are performed.

Description

Specification

Substrate processing method and substrate processing system

Technical field

The present invention relates to a substrate processing method and a substrate processing system for performing lithography processing on a substrate such as a semiconductor wafer or an LCD glass substrate.

Background art

In general, in the manufacture of semiconductor devices, a photolithography technique is used to form an ITO (Indium Tin Oxide) thin film or an electrode pattern on a substrate such as a semiconductor wafer or an LCD glass substrate. In this photolithography technique, a photoresist (hereinafter referred to as a resist) is applied to a substrate, the resist film formed thereby is exposed according to a predetermined circuit pattern, and the exposed pattern is developed. In this manner, a desired circuit pattern is formed on the resist film by a series of lithographic processes.

[0003] Such processing generally includes a resist coating processing unit that applies a resist solution to a substrate for processing, a heating processing unit that heats a substrate after completion of the resist coating processing and a substrate after exposure processing, and exposure processing. This is done by a coating / development processing system equipped with a plurality of development processing units, etc., for supplying a developing solution to a subsequent substrate for development processing.

Meanwhile, in recent years, there has been an increasing demand for miniaturization of device patterns. As one of the miniaturization methods, so-called multi-patterning technology that uses the lithographic process multiple times is being studied. In this multi-patterning technology, in addition to the multiple lithographic processes, it is necessary to perform etching processing to perform resist formation and microfabrication, and also to transport multiple substrates to the lithography process and transfer the substrate to the etching apparatus. Simplification of the form is important.

[0005] Conventionally, an apparatus that transports a substrate to a plurality of processing apparatuses and etching apparatuses that perform lithography processing and performs lithography processing and etching processing is known (for example, see Patent Document 1). The technique described in Patent Document 1 is configured so that the lithographic process can be repeated.

[0006] In addition, a transfer line for transferring a substrate to a plurality of processing apparatuses and another transfer line for transferring a substrate. There is known a substrate transfer method (apparatus) that is implemented by using both in and out (see, for example, Patent Document 2).

Patent Document 1 Japanese Patent Laid-Open No. 7-66265 (Claims, Fig. 1)

Patent Document 2 Japanese Patent Laid-Open No. 2003-282669 (Claims, Fig. 4) Disclosure of Invention

Problems to be solved by the invention

[0007] However, in the former technique, that is, the technique described in Japanese Patent Laid-Open No. 7-66265, the lithographic process can be repeated, so that a multi-pattern can be formed on the substrate. — In the device described in the publication No. 66265, since the processing device and the etching device of the lithographic process are formed separately, there is a concern that the number of devices increases and the size of the device increases. In addition, there is a problem that throughput is reduced and costs are increased with an increase in the substrate transfer process.

[0008] On the other hand, according to the technique described in the latter, that is, Japanese Patent Application Laid-Open No. 2003-282669, it is possible to selectively use the transport line as necessary, so that it is possible to prevent a decrease in throughput compared to the former. However, since multiple processing devices are arranged along the transfer line, it is necessary to transfer the substrate between the transfer line and each processing device. There is a problem of cost increase.

[0009] Furthermore, none of the techniques described in the above-mentioned JP-A-7-66265 and JP-A-2003-282669 refers to the multi-patterning technique, and the patterning dimensions in miniaturization are not mentioned. There remains a problem with accuracy.

[0010] The present invention has been made in view of the above circumstances, and it is possible to prevent a decrease in throughput and reduce the cost as in the lithographic process accompanying the miniaturization of the device, and to improve the pattern dimensional accuracy in the miniaturization. It is an object of the present invention to provide a substrate processing method and a substrate processing system which can be achieved.

Means for solving the problem

In order to solve the above-mentioned problems, the invention of the present application performs at least a lithography process such as a resist coating process, an exposure process, a post-exposure heating process, and a development process on a substrate to be processed by a substrate processing system. The lithographic process that forms the pattern of An etching step using the pattern after the development treatment as a mask;

Measuring step of measuring the line width of the pattern,

Based on the measurement information measured in the above measurement process, exposure correction in the second and subsequent lithographic processes is performed, temperature correction in the heat treatment after exposure, and / or etching correction in the etching process. And

[0012] The invention of the present application is characterized in that, in the substrate processing method, the pattern formed by the second and subsequent lithographic processes is formed between the patterns formed by the previous lithographic process. .

[0013] The invention of the present application embodies a substrate processing method, and applies at least lithography processing such as resist coating processing, exposure processing, post-exposure heating processing, and development processing to a substrate to be processed. A substrate processing system for forming a predetermined pattern,

An etching apparatus for performing an etching process using a pattern formed on the substrate to be processed after the development process as a mask;

A measuring device for measuring the line width of the pattern;

Information measured by the measuring device is stored, and based on the stored information! /, Exposure correction in the second and subsequent lithographic processes, temperature correction in the post-exposure heating process, and And / or a control means for performing etching correction in the etching process.

The invention of the present application embodies a substrate processing method, and includes a substrate loading / unloading unit for processing a substrate,

A coating / development processing unit having a resist coating device, a developing device and a heating device, and disposed between the coating / development processing unit and the exposure device, and a substrate to be processed is transferred between the coating / development processing unit and the exposure device. The interface part that manages

An etching processing unit having an etching apparatus for performing an etching process using a pattern formed on the substrate to be processed after the development process as a mask;

A measuring unit having a measuring device for measuring the line width of the pattern formed on the substrate to be processed;

Stores information measured by the measuring device, and based on the stored information! /, 2 And a control means for performing exposure correction in the exposure process of the lithographic process after the first time, temperature correction in the heating process after the exposure, and / or etching correction in the etching process.

[0015] Further, in the substrate processing system of the present application, it is more preferable that the measurement unit and the etching processing unit are disposed between the carry-in / carry-out unit and the coating / development processing unit. Preferably, the measurement unit and the etching processing unit are arranged in parallel, the etching processing unit is arranged on the coating / development processing unit side, and the measurement unit is arranged on the loading / unloading unit side.

[0016] In addition, in the substrate processing system of the present application, it is preferable that the etching apparatus is configured by a dry etching apparatus, and that a shield capable of blocking electromagnetic waves is provided on the casing forming the etching processing unit! / ,.

[0017] According to the invention of the present application, a lithography process for forming a predetermined pattern by performing a resist coating process, an exposure process, a post-exposure heating process and a developing process on the substrate to be processed, and a post-development process The multi-pattern can be formed on the substrate to be processed by performing the etching process using the pattern as a mask a plurality of times. Further, based on the measurement information of the line width of the pattern, it is possible to perform exposure correction in the exposure process for the second and subsequent lithographic processes, temperature correction in the heat treatment after exposure, and / or etching correction in the etching process. .

[0018] Further, according to the invention of the present application, a pattern formed by the second and subsequent lithographic processes is formed between patterns formed by the previous lithographic process, whereby one lithographic process is performed. The pattern can be miniaturized which is impossible.

[0019] According to the invention of the present application, the measurement unit and the etching processing unit are arranged between the loading / unloading unit and the coating-image processing unit, and the measurement unit and the etching processing unit are arranged in parallel. In addition, by arranging the etching processing section on the coating / developing processing section side and the measuring section on the loading / unloading section side, the lithographic process and the etching process can be integrated into one system, and the lithographic process The etching process and the etching process can be performed continuously. In addition, by arranging the measurement unit on the carry-in / carry-out unit side, it is possible to carry in the measurement in a short time by carrying the substrate to be processed, which only performs the measurement, into the measurement unit with the carry-in / carry-out unit force.

[0020] Further, according to the invention of the present application, an etching processing unit having a dry etching apparatus is configured. By applying a shield capable of blocking electromagnetic waves to the housing to be shielded, the force S can be used to suppress the effects of electromagnetic waves.

As described above, since the substrate processing method and the substrate processing system of the present invention are configured as described above, the following effects can be obtained.

[0022] (1) The lithography process and the etching process can be performed a plurality of times to form a multi-pattern on the substrate to be processed, and the second and subsequent processes can be performed based on the measurement information of the line width of the pattern. The exposure correction in the exposure process of the lithographic process, the temperature correction in the post-exposure heat process, and / or the etching correction in the etching process can be performed, so that the lithographic process and the etching process which are increased for device miniaturization can be reduced. It is possible to reduce the throughput and reduce the cost by consolidating, and to improve the pattern dimensional accuracy in miniaturization.

[0023] (2) Since the pattern can be miniaturized which is impossible in one lithographic process, the pattern can be further miniaturized.

[0024] (3) Since the lithographic process and the etching process can be integrated into one system, the lithographic process and the etching process can be performed continuously, so that the above (1), (2) In addition, the throughput can be further improved and the cost can be reduced. In addition, by arranging the measurement unit on the carry-in / carry-out unit side, it is possible to carry in the measurement in a short time by carrying the substrate to be processed, which performs only measurement, into the measurement unit with the force of the carry-in / carry-out unit.

[0025] (4) The effect of the electromagnetic wave can be suppressed by applying a shield capable of blocking the electromagnetic wave to the casing constituting the etching processing unit having the dry etching apparatus, so that the above (1) to (3 In addition to this, it is possible to further prevent harmful effects of electromagnetic waves in the apparatus and maintain the stability and safety of the apparatus.

Brief Description of Drawings

FIG. 1 is a schematic plan view showing an example of a resist coating / developing processing system to which a substrate processing system according to the present invention is applied.

FIG. 2 is a schematic perspective view of the resist coating / developing system.

FIG. 3 is a schematic front view of the resist coating / developing system.

FIG. 4 is a schematic rear view of the resist coating / developing system. FIG. 5 is a schematic side view showing a measuring apparatus according to the present invention.

FIG. 6 is a flowchart showing a substrate processing procedure by the substrate processing method according to the present invention. FIG. 7 is an enlarged sectional view showing the first pattern formation (a) and an enlarged sectional view showing the second pattern formation ( b).

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the best embodiment of the present invention will be described in detail with reference to the accompanying drawings. Here, a case where the substrate processing system according to the present invention is applied to a semiconductor wafer resist coating and developing processing system will be described.

FIG. 1 is a schematic plan view showing an example of the resist coating and developing system, FIG. 2 is a schematic perspective view, FIG. 3 is a schematic front view, and FIG. 4 is a schematic rear view. .

The resist coating / development processing system is a loading / unloading unit for loading / unloading a carrier 20 in which, for example, 25 semiconductor wafers W (hereinafter referred to as wafers W), which are substrates to be processed, are hermetically contained. A carrier block S1 and a plurality of, for example, four unit blocks B1 to B4 are arranged vertically. Coating · Development processing unit coating · Development processing block S2 (hereinafter referred to as processing block S2) and interface An etching block S5, which is an etching processing unit disposed between the carrier block S1 and the processing block S2 and disposed on the processing block S2 side. And a measurement block S6 which is a measurement unit arranged on the carrier block S1 side.

[0030] In the carrier block S1, a mounting table 21 on which a plurality of (for example, four) carriers 20 can be mounted, an opening / closing part 22 provided on a front wall surface as viewed from the mounting table 21, and an opening / closing A transfer arm B for taking out the wafer W from the carrier 20 via the part 22 is provided. This transfer arm B is movable in the horizontal X, Y direction and vertical Z direction so as to transfer the wafer W to and from the transfer stage T RS3 provided in the measurement block S6, and around the vertical axis. It is configured to be rotatable and movable!

[0031] A processing block S2, which is connected to the back side of the carrier block S1 via a measurement block S6 and an etching block S5 and is surrounded by a casing 70, is connected. In this example, the processing block S 2 is a first container for storing chemical containers such as a resist solution and a developer from the lower side. Unit block (CHM) B1, second unit block (DEV layer) B2 for performing development processing, coating film forming unit block for performing two-step resist solution coating processing, and cleaning unit for performing cleaning processing Blocks ij are assigned as the third and fourth unit blocks (COT layers) B3 and B4. In this case, one of the unit blocks for forming the coating film, for example, the third unit block (COT layer) B3 is used as a unit block for performing an antireflection film forming process formed on the lower layer side of the resist film ( BCT layer). Further, an antireflection film forming unit block for performing an antireflection film forming process formed on the upper layer side of the resist film may be provided above the fourth unit block (COT layer) B4. Good.

[0032] The first to fourth unit blocks B1 to B4 are disposed on the front surface side, and are disposed on the rear surface side with a liquid processing unit for applying a chemical solution to the wafer W, and the liquid processing unit. The processing units such as various heating units for pre-processing and post-processing of the processing performed in the above, the liquid processing unit arranged on the front side, the heating unit arranged on the back side, etc. In order to transfer wafer W between the processing unit, specifically the development processing unit at the lower level and the processing unit such as the heating unit and the processing unit with the resist processing unit at the upper level Main arms Al and A2 which are dedicated substrate transfer means.

[0033] In this example, the unit blocks B1 to B4 have the same layout layout of the liquid processing unit, the processing unit such as a heating unit, and the conveying means between the unit blocks B1 to B4. Has been. Here, the same arrangement layout means that the center of the wafer W in each processing unit, that is, the center of the spin chuck that is the means for holding the wafer W in the liquid processing unit, the heating plate or cooling in the heating unit, and so on. It means that the center of the plate is the same.

As shown in FIG. 1, the DEV layer B2 has an etching block S 5 on the carrier block S 1 side in the length direction of the DEV layer B2 (Y direction in the figure) at the approximate center of the DEV layer B2. A transfer area R1 of the wafer W (horizontal movement area of the main arm A1) for connecting the interface block S3 and the interface block S3 is formed. In addition, although not shown, COT layers B3 and B4 are located in the center of COT layers B3 and B4 in the length direction of COT layers B3 and B4 (in the Y direction in the figure), as in DEV layer B2. Carrier block S 1 side etching block S5 and interface block S3 are connected to form a transfer area R2 for wafer W (horizontal movement area for main arm A2) Has been.

[0035] To perform development processing as the liquid processing unit on both sides of the transport region Rl (R2) as viewed from the carrier block SI side, on the right side from the near side (carrier block S1 side) toward the back side. A plurality of, for example, three development processing units 31 are provided, a two-stage coating unit 32 and a cleaning unit (not shown) are provided. Each unit block is equipped with, for example, four shelf units Ul, U2, U3, U4, which are multi-staged heating units in order from the front side to the left side, and development is performed in the DEV layer B2. Various units for performing pre-processing and post-processing of the unit 31 are stacked in a plurality of stages, for example, three stages. In this way, the developing unit 31 and the shelf units U1 to U4 are partitioned by the transport region R1, and the particles in the region are suspended by ejecting clean air to the transport region R1 and exhausting it. It is designed to be suppressed.

[0036] Among the various units for performing the above pre-processing and post-processing, for example, as shown in FIG. 4, it is called a post-exposure baking unit that heat-treats the wafer W after exposure. It is called a heating unit (PEB) or a post-baking unit that heats the wafer W after development to remove moisture! /, A heating unit (POST), etc. It is. Each processing unit such as the heating unit (PEB, POST) is accommodated in the processing container 40, and the shelf units U1 to U4 are configured by stacking the processing containers 40 in three stages. A wafer loading / unloading port 41 is formed on the surface of the processing container 40 facing the transfer region R1. The heating unit (PEB, POST) is formed so that the heating temperature and heating time can be adjusted.

[0037] The main arm A1 is provided in the transfer region R1. This main arm A1 transfers wafers to and from all modules in the DEV layer B2 (where the wafer W is placed), for example, each processing unit of the shelf units U1 to U4 and each part of the developing unit 31. For this reason, it is configured to move in the horizontal X and Y directions and the vertical Z direction and to rotate about the vertical axis.

Note that the main arm Al (A2) is configured in the same manner, and the main arm A1 will be described as a representative example. For example, as shown in FIG. An arm main body 50 having two curved arm pieces 51 is provided, and these curved arm pieces 51 are configured to be movable forward and backward independently of each other along a base (not shown). The base is configured to be rotatable about the vertical axis, movable in the Y direction, and configured to be movable up and down. In this way, the curved arm piece 51 is configured to be movable back and forth in the X direction, movable in the Y direction, movable up and down, and rotatable about the vertical axis, and is mounted on each unit of the shelf units U1 to U4 and the carrier block S1 side. The wafer W can be delivered between the delivery unit TRS 1 of the arranged shelf unit U5 and the liquid processing unit. The driving of the main arm A1 is controlled by a controller (not shown) based on a command from the control unit 60 serving as control means. In addition, in order to prevent heat storage in the heating unit of the main arm A1 (A2), the order of receiving the wafers W can be arbitrarily controlled by a program.

[0039] The unit blocks B3 and B4 for coating film formation are both configured in the same manner, and are configured in the same manner as the unit block B2 for development processing described above. Specifically, a coating unit 32 for performing a resist solution coating process on the wafer W is provided as a liquid processing unit, and the shelf units U1 to U4 of the COT layers B3 and B4 are provided with a resist solution coating unit. Equipped with a heating unit (CLHP) that heats the wafer W and a hydrophobic treatment unit (ADH) that improves the adhesion between the resist solution and the wafer W, and is configured in the same way as the DEV layer B2. Yes. That is, the coating unit, the heating unit (CLHP), and the hydrophobizing unit (ADH) are configured to be divided by the transfer area R2 of the main arm A2 (horizontal movement area of the main arm A2). In COT layers B3 and B4, the main arm A2 delivers the wafer W to the delivery unit TRS1 of the shelf unit U5, the coating unit 32, and the processing units of the shelf units U; Is being carried out. The hydrophobic treatment unit (ADH) performs gas treatment in an HMDS atmosphere, but may be provided in any one of the unit blocks B3 and B4 for forming a coating film.

[0040] The etching block S5 disposed adjacent to the processing block S2 includes a casing 70a connected to the casing 70 of the processing block S2, and the casing 70a is stacked in multiple stages, for example, four stages. An etching unit 80, which is a dry etching apparatus that is A transfer arm C for loading / unloading the wafer W to / from the teaching unit 80 and a delivery stage TRS2 are provided. In this case, the transfer arm C transfers the wafer W between the transfer stage TRS 1 of the shelf unit U 5 in the processing block S2 and the transfer stage TR S2 in the etching block S5. , It is designed to move and rotate freely in the Y and vertical directions. The etching unit 80 is formed so that the etching rate can be controlled by adjusting the etching process conditions such as applied high frequency, high frequency voltage and gas pressure in a vacuum atmosphere.

[0041] The etching block S5 configured as described above has a shield for shielding electromagnetic waves on the casing 70a so that electromagnetic waves generated from the etching unit 80 do not affect the outside during the dry etching process. It has been subjected. Any shield may be used as long as it is a conductive metal or synthetic resin shielding plate, but in this embodiment, for example, a shielding plate 81 made of aluminum alloy is used to form the casing 70a. And!

[0042] As described above, the casing 70a of the etching block S5 is configured by the electromagnetic wave shielding plate 81, thereby blocking electromagnetic waves generated from the etching unit 80 from leaking to the outside during the dry etching process. Can do.

[0043] The measurement block S6 disposed between the carrier block S1 and the etching block S5 includes a casing 70b connected to the casing 70a of the carrier block S1 and the etching block S5. In the line 70b, a line width measuring device 90 which is a measuring device, a transfer arm D for transferring the wafer W to / from the line width measuring device 90, and a delivery stage TRS3 are arranged. In this case, the transfer arm D transfers the wafer W between the transfer stage TRS3 in the measurement block S6, the transfer stage TRS2 in the etching block S5, and the line width measuring device 90. It is configured to be movable in the X, Y and vertical directions and to be rotatable.

As shown in FIG. 5, the line width measuring apparatus 90 includes a mounting table 91 for mounting the wafer W horizontally. The mounting table 91 constitutes an XY stage, for example, and is formed to be movable in the horizontal X direction and the Y direction. Above the mounting table 91, a light irradiation unit 92 that emits light from an oblique direction to the wafer W mounted on the mounting table 91, and light reflected from the wafer W that is irradiated from the light irradiation unit 92 are detected. A light receiving unit 93 is disposed! Receiver 93 The information on the light detected in step 1 can be output to the detection unit 94, and the detection unit 94 is formed on the wafer W based on the acquired light information! The light intensity distribution of the reflected light reflected from can be measured. Note that the line width measuring device 90 can detect impurities, particles, and the like adhering to the wafer W in addition to measuring the line width of the pattern.

[0045] Information from the detection unit 94 is transmitted to the control unit 60, and information processing for measuring the line width, for example, is performed. The control unit 60 includes, for example, a calculation unit 61, a storage unit 62, and an analysis unit 63. The calculating unit 61 calculates each light intensity in calculating reflected light reflected from a plurality of virtual patterns having different line widths based on known information such as the optical constant of the resist film, the pattern shape and structure of the resist film, and the like. Distribution can be calculated. The storage unit 62 can store each calculated light intensity distribution for the virtual pattern calculated by the calculation unit 61 and create a library thereof.

The light intensity distribution for the actual pattern on the wafer W measured by the detection unit 94 can be output to the analysis unit 63. The analysis unit 63 collates the light intensity distribution of the actual pattern output from the detection unit 94 with the light intensity distribution of the virtual pattern stored in the library of the storage unit 62, and the virtual pattern with which the light intensity distribution matches. , And the line width of the virtual pattern can be estimated as the line width of the actual pattern to measure the line width.

[0047] Information on the line width measured as described above is transmitted to the exposure apparatus S4, the heating unit (PEB), and the etching unit 80. In this case, the exposure apparatus S4 has an exposure control unit (not shown), and is set according to exposure conditions such as an exposure position, an exposure amount, and an exposure focus on the optical system wafer W preset by the exposure control unit. The exposure process is controllable.

[0048] Therefore, by transmitting a control signal from the control unit 60 to the exposure apparatus S4, the heating unit (PEB), and the etching unit 80, the second and subsequent lithography processes are performed based on the measurement information of the line width of the pattern. Exposure correction such as exposure position, exposure amount and exposure focus in the exposure process of about Y, temperature correction such as heating temperature and heating time in heating process of post-exposure heating unit (PEB), high frequency applied in etching process Etching correction such as etching rate by adjusting etching process conditions such as high frequency voltage and gas pressure The ability to fi.

[0049] Further, as shown in FIG. 1, a shelf unit U6 is provided at a position accessible by the main arm A1 in the adjacent area of the processing block S2 and the interface block S3. The shelf unit U6 includes a delivery stage TRS4 and a delivery stage (not shown) having a cooling function for delivering the wafer W so as to deliver the wafer W to and from the main arm A1 of the DEV layer B2. ing. Further, as shown in FIG. 1 and FIG. 4, two stages of peripheral edge exposure devices (WEE) are arranged in the area adjacent to the processing block S2 and the interface block S3.

On the other hand, an exposure apparatus S4 is connected to the back side of the shelf unit U6 in the processing block S2 via an interface block S3. The interface block S3 includes an interface arm E for transferring the wafer W to each part of the shelf unit U6 of the DEV layer B2 of the processing block S2 and the exposure apparatus S4. The interface arm E serves as a means for transporting the wafer W interposed between the processing block S2 and the exposure apparatus S4. In this example, the interface arm E is connected to the delivery stage TRS4 etc. of the DEV layer B2. C) It is configured to move in the horizontal X, Y and vertical Z directions and to rotate around the vertical axis so as to deliver W!

Next, processing of the wafer W in the coating and developing processing system configured as described above will be described with reference to the flowchart shown in FIG. Here, the processing after the wafer W coated with a hard mask in advance is taken out from the carrier 20 and subjected to the hydrophobic treatment by the hydrophobic treatment unit (ADH) will be described.

The wafer W temporarily stored in the shelf unit U5 after being subjected to the hydrophobic treatment is taken out from the shelf unit U5 by the main arm A 2 and transferred to the coating unit 32, where a resist film is formed in the coating unit 32. (S-1). The wafer W on which the resist film is formed is transferred to the heating unit (CLHP) by the main arm A2 and subjected to a pre-beta (PAB) for evaporating the solvent from the resist film (S-2). Thereafter, the wafer W is transferred to a peripheral edge exposure apparatus (WEE), subjected to a peripheral exposure process (S-3), and then subjected to a heating process (S-4). Next, the wafer W is transferred to the exposure apparatus S4 by the interface arm E, where a predetermined exposure process is performed (S-5). The wafer W after the exposure processing is transferred to the delivery stage TRS4 of the shelf unit U6 by the interface arm E to deliver the wafer W to the DEV layer B2, and the wafer W on the stage TRS4 is transferred to the DEV layer. After being received by the main arm A1 of B2 and first subjected to post exposure beta processing (S-6) in the heating unit (PEB) in the DEV layer B2, the cooling plate (of the shelf unit U6 ( (Not shown) and adjusted to a predetermined temperature. Next, the wafer W is taken out from the shelf unit U6 by the main arm A1 and transferred to the developing unit 31, where a developing solution is applied (S-7). After that, it is transported to the heating unit (POST) by the main arm A1, and a predetermined development process is performed.

The wafer W after the development processing is transferred to the delivery stage TRS 1 of the shelf unit U5, and the wafer W on this stage TRS1 is received by the transfer arm C of the etching block S5, and the etching unit 80 of the etching block S5. Then, etching is performed using the developed pattern as a mask (S-8).

[0055] The wafer W after the etching process is taken out from the etching unit 80 by the transfer arm C and transferred to the delivery stage TRS2 of the etching block S5. The wafer W on the stage TRS2 is measured by the measurement block. It is received by the transfer arm D of S6, transferred to the line width measuring device 90 of the measurement block S6, and the line width of the pattern formed on the wafer W is measured (S-9). The measurement information of the line width is transmitted to the control unit 60 and stored in the control unit 60.

[0056] The wafer W on which the line width has been measured is taken out from the line width measuring device 90 by the transfer arm D, and then transferred to the transfer stage TRS2, transfer arm C, and processing block S2 of the etching block S5. The wafer W of the stage TRS1 is transferred to the stage TRS1, and is received by the main arm A2 of the processing block S2, and is transferred to the cleaning unit (SCR) to be cleaned (S-10). Thus, a series of lithographic processes (processing) and etching processes (processing) are completed. In this state, as shown in FIG. 7 (a), a pattern with a pitch P up to a critical dimension within a range where the resist PR does not collapse is formed on the surface of the wafer W by one lithography process. In FIG. 7, symbol CD is a line width, and HM is a node mask. [0057] A wafer W that has been subjected to the lithographic process (process) and the etching process (process) is formed into wafer W by repeating the same lithographic process (process) and the etching process (process) as described above. The pattern can be miniaturized. That is, the wafer W that has been subjected to the first lithographic process (process) and the etching process (process) is subjected to the resist coating process (COT) (S-11) → prebeta (PAB) (S— 12) → Peripheral exposure processing (WEE) (S 13) → Heat processing (BAKE) (S—14) → Exposure processing (EXP) (S—15) → Post Etspo Beta (PEB) (S—16) → Development By performing the processing (DEV) (S-17) → etching processing (ET) (S-18), as shown in Fig. 7 (b), the pitch P between the patterns formed by one lithography process This is done with the power to form a pattern with a pitch 1 / P.

[0058] Further, in the second lithographic process (processing) and the etching process (processing), the measurement information measured by the line width measuring device 90 after the first etching processing is transmitted from the control unit 60 to the exposure device S4, By transmitting to the unit (PEB) and the etching unit 80, the exposure position, exposure amount, exposure focus, etc. in the exposure process of the second and subsequent lithographic steps are determined based on the measurement information of the line width of the pattern. Correction, temperature correction such as heating temperature and heating time in the heating process of the heating unit (PEB) after exposure, etching rate by adjusting etching process conditions such as high frequency, high frequency voltage and gas pressure applied in the etching process, etc. Etching correction can be performed. These exposure correction, temperature correction, and etching correction may all be performed, or at least one may be performed. Thereby, the pattern formed on the wafer W can be miniaturized.

[0059] The wafer W that has been subjected to the second lithographic process (processing) and the etching process (processing) is transferred to the line width measuring device 90 of the measurement block S6, and the line width of the pattern is measured. Impurities and particles adhering to the wafer W surface are measured (CDM / MCR O) (S-19). This measurement information is also transmitted to the control unit 60, and the force S is used to confirm the shape of the line width formed on the wafer W, the pitch 1 / P, and the state of impurities and particles adhering to the wafer W.

[0060] The wafer W that has been subjected to the second lithographic process (processing) and the etching process (processing) as described above is placed on the carrier block S1 by the transfer arm B. Is returned to the original carrier 20 and the processing is completed.

In the above embodiment, the force described in the case where the lithographic process (processing) and the etching process (processing) are performed twice. These lithographic processes (processing) and the etching process (processing) are performed three or more times. May be. Of course, a single lithographic process (processing) and an etching process (processing) can be performed.

Further, in the above embodiment, the case where the antireflection film is not formed has been described. However, even when the antireflection film is formed below or above the resist film, the substrate processing method according to the present invention (system) ) Can be applied as well.

Claims

The scope of the claims

[1] A lithographic process for forming a predetermined pattern by subjecting a substrate to be processed to lithography processing such as resist coating processing, exposure processing, post-exposure heating processing and development processing on a substrate to be processed by the substrate processing system;

Measuring step of measuring the line width of the pattern,

Based on the measurement information measured in the above measurement process, exposure correction in the second and subsequent lithographic processes is performed, temperature correction in the heat treatment after exposure, and / or etching correction in the etching process. A substrate processing method.

[2] The substrate processing method according to claim 1,

A substrate processing method characterized in that a pattern formed by the second and subsequent lithographic processes is formed between patterns formed by the previous lithographic processes.

[3] A substrate processing system for forming a predetermined pattern by subjecting a substrate to be processed to at least a resist coating process, an exposure process, a post-exposure heating process, and a lithography process such as an image process to form a predetermined pattern. An etching apparatus for performing an etching process using a pattern formed on a substrate to be processed as a mask;

A measuring device for measuring the line width of the pattern;

[4] Loading / unloading substrate to be processed;

Measurement having a measuring device for measuring the line width of the pattern formed on the substrate to be processed And

A substrate processing system.

[5] The substrate processing system according to claim 4,

Between the loading / unloading section and the coating / development processing section, the measurement section and the etching processing section are arranged in parallel, and the etching processing section is arranged on the coating / developing processing section side, and the measuring section is loaded / unloaded. A substrate processing system, characterized in that the substrate processing system is arranged on the part side.

[6] The substrate processing system according to claim 5,

A substrate processing system, wherein the etching apparatus is constituted by a dry etching apparatus, and a shield capable of blocking electromagnetic waves is provided on a casing constituting the etching processing section.

[7] The substrate processing system according to claim 4,