Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
  • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
  • G11C11/5628—Programming or writing circuits; Data input circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/10—Programming or data input circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/10—Programming or data input circuits
  • G11C16/12—Programming voltage switching circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/30—Power supply circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C16/3436—Arrangements for verifying correct programming or erasure
  • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C16/3436—Arrangements for verifying correct programming or erasure
  • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
  • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C16/3436—Arrangements for verifying correct programming or erasure
  • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
  • G11C16/3486—Circuits or methods to prevent overprogramming of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
  • G11C2211/562—Multilevel memory programming aspects
  • G11C2211/5621—Multilevel programming verification

Definitions

• Embodiments in accordance with the present disclosure relate to programming non-volatile memory.
• Non-volatile semiconductor memory devices have become more popular for use in various electronic devices.
• non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices.
• Electrical Erasable Programmable Read Only Memory (EEPROM), including flash EEPROM, and Electronically Programmable Read Only Memory (EPROM) are among the most popular non-volatile semiconductor memories.
• FIG. 1 is a top view showing one NAND string.
• Figure 2 is an equivalent circuit thereof.
• the NAND string depicted in Figures 1 and 2 includes four transistors 100, 102, 104 and 106 in series and sandwiched between a first select gate 120 and a second select gate 122.
• Select gate 120 connects the NAND string to bit line 126.
• Select gate 122 connects the NAND string to source line 128.
• Select gate 120 is controlled by applying appropriate voltages to control gate 120CG via selection line SGD.
• Select gate 122 is controlled by applying the appropriate voltages to control gate 122CG via selection line SGS.
• Each of the transistors 100, 102, 104 and 106 includes a control gate and a floating gate, forming the gate elements of a memory cell.
• transistor 100 has control gate IOOCG and floating gate 100FG.
• Transistor 102 includes control gate 102CG and a floating gate 102FG.
• Transistor 104 includes control gate 104CG and floating gate 104FG.
• Transistor 106 includes a control gate 106CG and a floating gate 106FG.
• Control gate IOOCG is connected to word line WL3
• control gate 102CG is connected to word line WL2
• control gate 104CG is connected to word line WLl
• control gate 106CG is connected to word line WLO.
• Figures 1 and 2 show four memory cells in the NAND string, the use of four transistors is only provided as an example.
• a NAND string can have less than four memory cells or more than four memory cells.
• some NAND strings will include eight memory cells, 16 memory cells, 32 memory cells, etc. The discussion herein is not limited to any particular number of memory cells in a NAND string.
• a typical architecture for a flash memory system using a NAND structure will include several NAND strings.
• Figure 3 shows three NAND strings 202, 204 and 206 of a memory array having many more NAND strings.
• Each of the NAND strings of Figure 3 includes two select transistors or gates and four memory cells.
• NAND string 202 includes select transistors 220 and 230, and memory cells 222, 224, 226 and 228.
• NAND string 204 includes select transistors 240 and 250, and memory cells 242, 244, 246 and 248.
• Each string is connected to the source line by one select gate (e.g. select gate 230 and select gate 250).
• a selection line SGS is used to control the source side select gates.
• the various NAND strings are connected to respective bit lines by select gates 220, 240, etc., which are controlled by select line SGD. In other embodiments, the select lines do not necessarily need to be in common.
• Word line WL3 is connected to the control gates for memory cell 222 and memory cell 242.
• Word line WL2 is connected to the control gates for memory cell 224 and memory cell 244.
• Word line WLl is connected to the control gates for memory cell 226 and memory cell 246.
• Word line WLO is connected to the control gates for memory cell 228 and memory cell 248.
• a bit line and respective NAND string comprise a column of the array of memory cells.
• the word lines (WL3, WL2, WLl and WLO) comprise the rows of the array. Each word line connects the control gates of each memory cell in the row.
• word line WL2 is connected to the control gates for memory cells 224, 244 and 252.
• Each memory cell can store data (analog or digital).
• the range of possible threshold voltages of the memory cell is divided into two ranges which are assigned logical data "1" and "0.”
• the threshold voltage is negative after the memory cell is erased, and defined as logic "1.”
• the threshold voltage after a program operation is positive and defined as logic "0.”
• the threshold voltage is negative and a read is attempted by applying 0 volts to the control gate, the memory cell will turn on to indicate logic one is being stored.
• the threshold voltage is positive and a read operation is attempted by applying 0 volts to the control gate, the memory cell will not turn on, which indicates that logic zero is stored.
• a memory cell can also store multiple levels of information, for example, multiple bits of digital data.
• the range of possible threshold voltages is divided into the number of levels of data. For example, if four levels of information are stored, there will be four threshold voltage ranges assigned to the data values "11", “10", “01”, and "00.”
• the threshold voltage after an erase operation is negative and defined as "11.” Three different positive threshold voltages are used for the states of "10", "01", and "00.”
• Shifts in the apparent charge stored on a floating gate can occur because of coupling of an electric field based on the charge stored in adjacent floating gates.
• This floating gate to floating gate coupling phenomena is described in U.S. Patent 5,867,429, which is incorporated herein by reference in its entirety.
• An adjacent floating gate to a target floating gate may include neighboring floating gates that are on the same bit line, neighboring floating gates on the same word line, or neighboring floating gates that are on both a neighboring bit line and neighboring word line, and thus, across from each other in a diagonal direction.
• the floating gate to floating gate coupling phenomena occurs most pronouncedly, although not exclusively, between sets of adjacent memory cells that have been programmed at different times.
• a first memory cell can be programmed to add a level of charge to its floating gate that corresponds to a set of data.
• one or more adjacent memory cells are programmed to add a level of charge to their floating gates that correspond to a set of data.
• the charge level read from the first memory cell may appear to be different than when it was programmed because of the effect of the charge on the adjacent memory cell(s) being coupled to the first memory cell.
• the coupling from adjacent memory cells can shift the apparent charge level being read from a selected memory cell by a sufficient amount to lead to an erroneous reading of the data stored.
• the effect of the floating gate to floating gate coupling is of greater concern for multi-state devices because in multi-state devices the allowed threshold voltage ranges and the forbidden ranges (range between two distinct threshold voltage ranges that represent distinct memory states) are narrower than in binary devices. Therefore, floating gate to floating gate coupling can result in memory cells being shifted from an allowed threshold voltage range to a forbidden range.
• the lowest programmed state in multi-state non-volatile flash memory devices can suffer from an increased level of bit line to bit line capacitive charge coupling when compared with other states.
• Program voltages applied to memory cells as increasing voltage pulses can be incremented using smaller values when programming memory cells to the lowest programmable level or state. Smaller increments in the applied voltage allow for greater precision and a narrower threshold voltage distribution to compensate for the disproportionate charge coupling experienced by cells programmed to this state. Smaller increment values can be used in one embodiment when programming a first logical page and larger increment values used when programming other pages. In a pipelined programming architecture where cells forming a physical page store two logical pages of data and programming for one logical page begins before receiving data for the other logical page, the increment value can be increased when switching from programming the first logical page to programming both pages concurrently.
• a method of programming non-volatile storage includes receiving a request to program data to a set of multi- state non-volatile storage elements, applying a predetermined number of program voltage pulses to the set of non-volatile storage elements to program the data to the non-volatile storage elements, and applying one or more additional program voltage pulses to the set of non-volatile storage elements to complete programming of the data.
• Applying a predetermined number of program voltage pulses to the set can include increasing a size of each of the program voltage pulses by a first increment value until the predetermined number is reached.
• Applying one or more additional program voltage pulses to the set can include increasing a size of each of the one or more additional program voltages by a second increment value.
• a method of programming non-volatile storage is provided.
• a first set of data designated for storage in a physical page of nonvolatile storage is received.
• the first set of data can include less than all of a maximum amount of data storable by the physical page.
• the first set of data forms a lower logical page of data.
• the first set of data is programmed to the physical page by programming the data using a program voltage signal having a peak value that is incremented by a first increment value when programming the data to the physical page.
• a second set of data is received that is also designated for storage in the physical page. The second set of data can be received after beginning programming of the first set of data to the physical page and prior to completing programming of the first set of data to the physical page.
• programming of the first set of data is stopped or interrupted. After stopping programming of the first page of data, the first set of data and the second set of data are concurrently programmed to the physical page.
• Concurrently programming can include programming the first data and the second data using a program voltage signal having a peak value that is increased by a second increment value while concurrently programming the first data and the second data to the physical page.
• a non- volatile memory system includes a plurality of storage elements, a plurality of data buffers in communication with the storage elements and managing circuitry in communication with the buffers and storage elements.
• the managing circuitry receives first data to be stored in the storage elements and in response, provides the first data to a first set of the buffers.
• the managing circuitry programs the first data to the storage elements using a plurality of program voltage pulses increased by a first increment value.
• the managing circuitry receives second data to be stored in the storage elements while programming the first data and in response, provides the second data to a second set of the buffers.
• the managing circuitry stops programming the first data to the storage elements and begins concurrently programming the first data and the second data to the storage elements using a plurality of program voltage pulses increased by a second increment value.
• Figure 1 is a top view of a NAND string.
• Figure 2 is an equivalent circuit diagram of the NAND string of Figure 1.
• Figure 3 is a circuit diagram depicting three NAND strings.
• Figure 4 is a block diagram of one embodiment of a non-volatile memory system.
• Figure 5 illustrates an exemplary organization of a memory array.
• Figure 6 depicts an exemplary program voltage signal.
• Figure 7 depicts an exemplary set of threshold voltage distributions and a full sequence programming process.
• Figure 8 depicts an exemplary set of threshold voltage distributions and a two-pass programming process.
• Figures 9 is a table depicting the effects of capacitive charge coupling in an exemplary non-volatile memory system.
• Figure 10 is a timing diagram for programming lower page data and upper page data during discrete intervals of time.
• Figure 11 is a program voltage signal in accordance with one embodiment that can be used to program the lower and upper pages of data as shown in Figure 10.
• Figure 12 is a timing diagram for programming lower page data and then concurrently programming lower and upper page data when upper page data is received.
• Figure 13 is a program voltage signal in accordance with one embodiment that can be used to program the lower and upper pages of data as shown in Figure 12.
• Figure 14 is a flowchart depicting a method of programming nonvolatile memory in accordance with one embodiment.
• Figure 15 is a flowchart depicting a method for setting a program command when additional data for a set of memory cells currently being programmed is received.
• Figure 16 is a flowchart depicting a method for transitioning to full sequence or upper page programming using larger increment values when lower page programming is complete.
• Figures 17A, 17B and 17C depict one embodiment of a programming process that is performed as part of coarse/fine programming.
• Figures 18A, 18B and 18C depict one embodiment of a programming process that is performed as part of coarse/fine programming.
• Figure 4 is a block diagram of one embodiment of a flash memory system that can be used to implement one or more embodiments of the present disclosure. Other systems and implementations can be used.
• Memory cell array 302 is controlled by column control circuit 304, row control circuit 306, c- source control circuit 310 and p-well control circuit 308.
• Column control circuit 304 is connected to the bit lines of memory cell array 302 for reading data stored in the memory cells, for determining a state of the memory cells during a program operation, and for controlling potential levels of the bit lines to promote or inhibit programming and erasing.
• Row control circuit 306 is connected to the word lines to select one of the word lines, to apply read voltages, to apply program voltages combined with the bit line potential levels controlled by column control circuit 304, and to apply an erase voltage.
• C- source control circuit 310 controls a common source line (labeled as "C-source” in Fig. 5) connected to the memory cells.
• P-well control circuit 308 controls the p-well voltage.
• the data stored in the memory cells is read out by the column control circuit 304 and output to external I/O lines via data input/output buffer 312.
• Program data to be stored in the memory cells is input to the data input/output buffer 312 via the external I/O lines, and transferred to the column control circuit 304.
• the external I/O lines are connected to controller 318.
• Command data for controlling the flash memory device is input to controller 318.
• the command data informs the flash memory of what operation is requested.
• the input command is transferred to state machine 316 which is part of control circuitry 315.
• State machine 316 controls column control circuit 304, row control circuit 306, c-source control 310, p-well control circuit 308 and data input/output buffer 312.
• State machine 316 can also output status data of the flash memory such as READY/BUSY or PASS/FAIL.
• Controller 318 is connected to or connectable with a host system such as a personal computer, a digital camera, or personal digital assistant, etc. It communicates with the host that initiates commands, such as to store or read data to or from the memory array 302, and provides or receives such data. Controller 318 converts such commands into command signals that can be interpreted and executed by command circuits 314 which are part of control circuitry 315. Command circuits 314 are in communication with state machine 316. Controller 318 typically contains buffer memory for the user data being written to or read from the memory array.
• One exemplary memory system comprises one integrated circuit that includes controller 318, and one or more integrated circuit chips that each contain a memory array and associated control, input/output and state machine circuits.
• the memory system may be embedded as part of the host system, or may be included in a memory card (or other package) that is removably inserted into the host systems.
• a memory card may include the entire memory system (e.g. including the controller) or just the memory array(s) with associated peripheral circuits (with the controller or control function being embedded in the host).
• the controller can be embedded in the host or included within the removable memory system.
• a NAND flash EEPROM is described that is partitioned into 1,024 blocks.
• the data stored in each block can be simultaneously erased.
• the block is the minimum unit of cells that are simultaneously erased.
• Each block is typically divided into a number of pages which can be a unit of programming. Other units of data for programming are also possible and contemplated.
• individual pages may be divided into segments and the segments may contain the fewest number of cells that are written at one time as a basic programming operation.
• One or more pages of data are typically stored in one row of memory cells.
• each block of the example in Figure 5 there are 8,512 columns that are divided into even columns and odd columns.
• the bit lines are divided into even bit lines (BLe) and odd bit lines (BLo).
• bit lines are divided into even bit lines (BLe) and odd bit lines (BLo).
• BLe even bit lines
• BLo odd bit lines
• FIG 5 shows four memory cells connected in series to form a NAND string. Although four cells are shown to be included in each NAND string, more or less than four can be used (e.g., 16, 32, or another number).
• One terminal of the NAND string is connected to a corresponding bit line via a first select transistor or gate (connected to select gate drain line SGD), and another terminal is connected to c-source via a second select transistor (connected to select gate source line SGS).
• bit lines are not divided into odd and even bit lines.
• Such architectures are commonly referred to as all bit line architectures.
• all bit lines of a block are simultaneously selected during read and program operations. Memory cells along a common word line and connected to any bit line are programmed at the same time.
• Memory cells are erased by raising the p-well to an erase voltage
• Electrons are transferred from the floating gate to the p-well region and the threshold voltage becomes negative (in one embodiment).
• the select gates of a selected block are raised to one or more select voltages and the unselected word lines (e.g., WLO, WLl and WL3) of the selected block are raised to a read pass voltage (e.g. 4.5 volts) to make the transistors operate as pass gates.
• the selected word line of the selected block (e.g., WL2) is connected to a reference voltage, a level of which is specified for each read and verify operation in order to determine whether a threshold voltage of the concerned memory cell is above or below such level. For example, in a read operation of a one bit memory cell, the selected word line WL2 is grounded, so that it is detected whether the threshold voltage is higher than OV.
• the selected word line WL2 is connected to 0.8V, for example, so that as programming progresses it is verified whether or not the threshold voltage has reached 0.8V.
• the source and p-well are at zero volts during read and verify.
• the selected bit lines (BLe) are pre-charged to a level of, for example, 0.7V. If the threshold voltage is higher than the read or verify level, the potential level of the concerned bit line (BLe) maintains the high level, because of the associated non-conductive memory cell. On the other hand, if the threshold voltage is lower than the read or verify level, the potential level of the concerned bit line (BLe) decreases to a low level, for example less than 0.5V, because of the conductive memory cell.
• the state of the memory cell is detected by a sense amplifier that is connected to the bit line and senses the resulting bit line voltage.
• the difference between whether the memory cell is programmed or erased depends on whether or not net negative charge is stored in the floating gate. For example, if negative charge is stored in the floating gate, the threshold voltage becomes higher and the transistor can be in enhancement mode of operation.
• the drain and the p-well receive OV while the control gate receives a series of programming pulses with increasing magnitudes.
• the magnitudes of the pulses in the series range from 12V to 24V. In other embodiments, the range of pulses in the series can be different, for example, having a starting level of higher than 12 volts.
• verify operations are carried out in the periods between the programming pulses. That is, the programming level of each cell of a group of cells being programmed in parallel is read between each programming pulse to determine whether or not it has reached or exceeded a verify level to which it is being programmed.
• One means of verifying the programming is to test conduction at a specific compare point.
• FIG. 6 depicts a program voltage signal in accordance with one embodiment. This signal has a set of pulses with increasing magnitudes. The magnitude of the pulses is increased with each pulse by a predetermined step size.
• an exemplary step size is 0.2V (or 0.4V).
• the signal of Figure 6 assumes a four state memory cell, therefore, it includes three verify pulses. For example, between programming pulses 330 and 332 are three sequential verify pulses.
• the first verify pulse 334 is depicted at a zero volt verify voltage level.
• the second verify pulse 336 follows the first verify pulse at the second verify voltage level.
• the third verify pulse 338 follows the second verify pulse 336 at the third verify voltage level.
• a multi-state memory cell capable of storing data in eight states may need to perform verify operations at seven compare points.
• seven verify pulses are applied in sequence to perform seven verify operations at seven verify levels between two consecutive programming pulses. Based on the seven verify operations, the system can determine the state of the memory cells.
• One means for reducing the time burden of verifying is to use a more efficient verify process, for example, as disclosed in: U.S. Patent Application Serial No. 10/314,055, entitled “Smart Verify for Multi-State Memories,” filed December 5, 2002; U.S. Patent Application Serial No. 11/259,799, entitled “Apparatus for Programming of Multi-State Non-Volatile Memory Using Smart Verify," filed October 27, 2005; and U.S. Patent Application Serial No. 11/260,658, entitled “Method for Programming of Multi-State Non-Volatile Memory Using Smart Verify,” filed October 27, 2005, all of which are incorporated herein by reference in their entirety.
• the threshold voltages of the memory cells should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells, as appropriate.
• Figure 7 illustrates threshold voltage distributions for the memory cell array when each memory cell stores two bits of data.
• Figure 7 shows a first threshold voltage distribution E for erased memory cells.
• Three threshold voltage distributions, A, B and C for programmed memory cells, are also depicted.
• the threshold voltages in the E distribution are negative and the threshold voltages in the A, B and C distributions are positive.
• Each distinct threshold voltage range of Figure 7 corresponds to predetermined values for the set of data bits.
• the specific relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells.
• data values are assigned to the threshold voltage ranges using a gray code assignment so that if the threshold voltage of a floating gate erroneously shifts to its neighboring physical state, only one bit will be affected.
• gray coding is not used.
• One example assigns "11" to threshold voltage range E (state E), “10” to threshold voltage range A (state A), “00” to threshold voltage range B (state B) and "01” to threshold voltage range C (state C).
• Figure 7 shows four states, the present invention can also be used with other multi-state structures including those that include more or less than four states.
• Figure 7 also shows three read reference voltages, V ⁇ A , V ⁇ B and
• V r c for reading data from memory cells.
• the system can determine what state the memory cell is in.
• Figure 7 also shows three verify reference voltages, V VA , V VB and V v c-
• V VA , V VB and V v c- When programming memory cells to state A, the system will test whether those memory cells have a threshold voltage greater than or equal to V VA -
• V VB - When programming memory cells to state B, the system will test whether the memory cells have threshold voltages greater than or equal to V VB -
• the system will determine whether memory cells have their threshold voltage greater than or equal to V v c.
• Figure 7 depicts one embodiment that utilizes full sequence programming.
• memory cells can be programmed from the erase state E directly to any of the programmed states A, B or C.
• a population of memory cells to be programmed may first be erased so that all memory cells in the population are in erased state E.
• the process hereinafter described with respect to Figure 7, using a series of program voltage pulses applied to the control gates of selected memory cells, will then be used to program the memory cells directly into states A, B or C. While some memory cells are being programmed from state E to state A, other memory cells are being programmed from state E to state B and/or from state E to state C.
• Figure 8 illustrates an example of a two-pass technique of programming a multi-state memory cell that stores data for two different pages: a lower page and an upper page.
• states are depicted: state E (11), state A (10), state B (00) and state C (01).
• state E both pages store a "1.”
• state A the lower page stores a "0" and the upper page stores a "1.”
• state B both pages store "0.”
• state C the lower page stores "1" and the upper page stores "0.”
• bit patterns may also be assigned.
• the cell's threshold voltage level is set according to the bit to be programmed into the lower logical page.
• the threshold voltage is not changed since it is in the appropriate state as a result of having been earlier erased. However, if the bit to be programmed is a logic "0,” the threshold level of the cell is increased to be state A, as shown by arrow 302. That concludes the first programming pass. [0055] In a second programming pass, the cell's threshold voltage level is set according to the bit being programmed into the upper logical page. If the upper logical page bit is to store a logic "1,” then no programming occurs since the cell is in one of the states E or A, depending upon the programming of the lower page bit, both of which carry an upper page bit of "1.” If the upper page bit is to be a logic "0,” then the threshold voltage is shifted.
• the cell is programmed so that the threshold voltage is increased to be within state C, as depicted by arrow 306. If the cell had been programmed into state A as a result of the first programming pass, then the memory cell is further programmed in the second pass so that the threshold voltage is increased to be within state B, as depicted by arrow 304.
• the result of the second pass is to program the cell into the state designated to store a logic "0" for the upper page without changing the data for the lower page.
• a system can be set up to perform full sequence writing if enough data is written to fill up an entire page. If not enough data is written for a full page, then the programming process can program the lower page with the data received. When subsequent data is received, the system will then program the upper page.
• the system can start writing data using the two-pass technique and then convert to full sequence programming mode if enough data is subsequently received to fill up an entire (or most of a) word line's memory cells. More details of such an embodiment are disclosed in U.S. Patent Application titled "Pipelined Programming of Non-Volatile Memories Using Early Data," Serial No. 11/013,125, filed on December 14, 2004, inventors Sergy Anatolievich Gorobets and Yan Li, incorporated herein by reference in its entirety.
• FIG. 8 Other programming techniques can be used in accordance with various embodiments in addition to full sequence and upper page - lower page programming as shown in Figure 8.
• a two- pass technique that reduces floating gate to floating gate coupling between cells on different word lines by, for any particular memory cell, writing to that particular memory cell with respect to a particular page subsequent to writing to adjacent memory cells for previous pages, can be used.
• the memory cells store two bits of data per memory cell, using four data states (e.g., non-Gray coding where erased state E stores 11, programmed states A, B and C store 01, 10, and 00, respectively).
• Each memory cell stores two pages of data that, for reference purposes, will be called upper page and lower page.
• the lower page is programmed - a memory cell that is to store data 1 in the lower page remains at state E, while a memory cell that is to store data 0 is raised to an intermediate state B'.
• the upper page is programmed.
• a memory cell in erased state E that is to store data 1 for the upper page remains at state E, while a memory cell in state E that is to store data 0 for the upper page is programmed to state A.
• a memory cell in the intermediate state B' that is to store data 1 for the upper page is programmed to final state B, while a memory cell in the intermediate state B' that is to store data 0 for the upper page is programmed to state C.
• Figure 9 is a table depicting the various capacitive charge coupling effects for cells programmed in both a single page technique such as upper/lower page programming and full sequence programming where all data states are programmed at once.
• the table of Figure 9 depicts the effects for a four state memory device but it will be appreciated by those of ordinary skill in the art that the embodied principles can be used with systems having more physical states.
• the memory cells programmed to the first programmed state A suffer the most effects from capacitive charge coupling.
• the first row depicts single page programming (column 382) and a memory cell in state A with a neighbor programmed to state C (column 384).
• the cell in state A will experience an increase in its apparent threshold voltage that is equal to the product of a constant ⁇ , representing the coupling coefficient between floating gates, and the change in voltage between the erased state E and the programmed state C. Because the memory cell in state A was programmed when programming a first page and its neighbor was programmed to state C later when programming a second page, the neighbor's floating gate voltage will rise by the difference between the erased state and the C programmed state.
• Column 386 sets forth exemplary threshold voltage changes for a memory cell programmed between the various states in a memory system. In the provided example, programming from state E to state C will shift the threshold voltage about 6V. The memory cell in state A will experience an apparent shift in its threshold voltage equal to the product of this difference and the coupling coefficient.
• a cell in state A with a neighbor programmed to state B will experience an apparent shift equal to the product of the constant and the change in voltage between the first programmed state A and the second programmed state B (e.g., 2V).
• a cell in state B with a neighbor in state C will experience an apparent shift in threshold voltage equal to the product of the constant and the change in voltage between the second programmed state B and the third programmed state C (e.g., 2V).
• state A memory cells experience less capacitive charge coupling in full sequence programming, they still experience the most when compared to the cells in other states.
• state A e.g., 2V
• state C e.g., 2V
• all states are programmed at the same time.
• the selected cell will reach state A around the same time as its neighbor in most cases.
• the only coupling effects after the selected cell was programmed are reflected by the neighbor moving from state A to state C.
• a cell in state A with a neighbor programmed to state B will experience an apparent shift equal to the product of the constant and the change in voltage between the first programmed state A and the second programmed state B (e.g., 2V).
• a cell in state B with a neighbor in state C will experience an apparent shift in threshold voltage equal to the product of the constant and the change in voltage between the second programmed state B and the third programmed state C (e.g., 2V).
• FIG. 9 illustrates, cells in the lowest programmed physical state will suffer the most capacitive charge coupling from later programmed neighbors. These disproportionate coupling effects can widen the A state distribution and possibly cause read errors.
• the first programmed state is programmed with greater precision to compensate for the additional charge coupling effects in one embodiment.
• techniques are used to achieve a tighter threshold voltage distribution for the first programmed state to compensate for a subsequent change in its apparent threshold voltage.
• a lower increment value for the program voltage signal can be used when programming cells to the lowest programmable state in one embodiment.
• the increment value is lower when programming a first logical page of data to a set of memory cells and larger when programming a second logical page of data to the set.
• the increment value can be increased when the memory switches from single page programming to full sequence programming.
• Figure 10 is a timing diagram illustrating a non-volatile memory system processing and writing individual logical pages of data, where a first page of data for a set of cells is completed before beginning a second page of data.
• Data from the host device is first received at the controller.
• the controller forwards the data and address information to the column control circuitry which places the data in the data registers.
• a lower page of data is received by the controller before an upper page of data for the same memory cells.
• the appropriate registers are loaded and in response to a program command from the controller, the state machine will begin programming the lower page data into the set of cells at time tl.
• Data for the upper page of data for the corresponding set of memory cells is received from the host after time tl.
• the controller completes loading of the data into the registers at the array at time t2.
• the system does not program the upper page of data until the lower page has been programmed.
• the state machine continues to program the lower page of data into the set of cells until time t3, and the upper page data remains in the registers.
• the controller can issue a program command for the upper page of data and the state machine respond by programming the upper page data from the registers into the array.
• programming the upper page includes programming cells from state E to state C and from state A to state B.
• a two-pass technique as previously described is used such that upper page programming includes programming cells from state E to state, and from an intermediate state to state B and state C.
• FIG. 10 a different increment value for the program voltage signal is used in an embodiment as shown in Figure 10 when programming the upper page at time t3.
• Figure 11 depicts a program voltage signal in accordance with one embodiment. Programming memory cells from the erased state to state A begins at time tl when a first program voltage pulse is applied. After performing a verification to determine which cells, if any, are programmed to state A, an additional pulse is applied with a peak value incremented by ⁇ Vpgml. This continues until lower page programming completes at time t3.
• Lower page programming can complete after the number of program voltage pulses reaches a predetermined maximum number or after a sufficient number of memory cells to be programmed to state A are successfully verified as having reached state A.
• the program voltage increment value is changed to ⁇ Vpgm2.
• ⁇ Vpgm2 is larger than ⁇ Vpgml in order to speed up the programming process in one embodiment.
• ⁇ Vpgm2 is selected after analysis to determine an appropriate value for programming the majority of memory cells in an array as quickly as possible (larger increment value), but while also ensuring precise programming of data (smaller increment value).
• the value of ⁇ Vpgml can be an adjusted value of ⁇ Vpgm2 to compensate for the increased amount of charge coupling experienced by the cells programmed to state A. For example, ⁇ Vpgml can be lowered from the ⁇ Vpgm2 value based on the amount of additional capacitive charge coupling it receives.
• ⁇ Vpgml when programming state A could be lower than ⁇ Vpgm2 by an amount based on the 4V difference in the floating gate voltage of its neighbor after programming versus the 2V difference for the cells programmed to states B and C.
• ⁇ Vpgml for the lower page could be about 0.3V in one embodiment and ⁇ Vpgm2 about 0.4V for upper page or full sequence programming.
• Figure 12 is a timing diagram illustrating a non-volatile memory system processing and writing logical pages of data, where programming begins for a first page of data and then pauses or interrupts when a second page of data is received in order to begin full sequence programming for all the pages.
• Data from the host device is received at the controller.
• the controller forwards the data and address information to the column control circuitry which places the data in the data registers.
• a lower page of data is received by the controller before an upper page of data for the same memory cells.
• the appropriate registers are loaded and in response to a program command from the controller, the state machine begins programming the lower page data into the set of cells at time tl.
• Upper page data for the same set of memory cells is received from the host after time tl.
• the controller completes loading of the data into the registers at the array at time t2.
• the controller can interrupt the program operation.
• the system can interrupt, pause, or otherwise stop the lower page programming process to switch to a full sequence operation.
• the controller only stops the lower page programming operation if it is not complete already or not sufficiently complete to warrant allowing it to finish.
• the controller can issue a new program command for full sequence programming after providing the upper page data to the data registers in the column control circuitry.
• a verification operation can be performed to lock out those cells that have reached their target states. Programming then continues for both pages of data using full sequence programming.
• a different increment value for the program voltage signal is used in an embodiment as shown in Figure 12 when utilizing full sequence programming after time t2.
• Figure 12 depicts a program voltage signal in accordance with one embodiment. Programming memory cells from the erased state to state A begins at time tl when a first erase voltage pulse is applied. Before programming to state A for the lower page is complete, upper page data is received from the host. The controller issues the data to the column control circuitry where it is stored in registers at time t2.
• full sequence programming begins with the first pulse after time t2. With the full sequence command issued, the next program voltage pulse is incremented by ⁇ Vpgm2 over the last program voltage pulse before stopping lower page programming.
• ⁇ Vpgm2 and ⁇ Vpgml values can vary by embodiment and the requirements of various implementations. In one embodiment, ⁇ Vpgml and ⁇ Vpgm2 are selected as described with respect to Figure 11.
• FIG 14 is a flowchart of a method for programming non-volatile memory in accordance with one embodiment.
• a variable increment value is used based on the state being programmed and/or the type of programming operation and data.
• a "data load" command is issued by controller 318 and input to command circuits 314, allowing data to be input to data input/output buffer 312.
• the input data is recognized as a command and latched by state machine 316 via a command latch signal, not illustrated, input to command circuits 314.
• address data designating the page address is input to row controller or decoder 306 from the controller or host.
• the input data is recognized as the page address and latched via state machine 316, affected by the address latch signal input to command circuits 314.
• a page of program data for the addressed page is input to data input/output buffer 312 for programming. For example, 532 bytes of data could be input in one embodiment. That data is latched in the appropriate registers for the selected bit lines. In some embodiments, the data is also latched in a second register for the selected bit lines to be used for verify operations.
• the data corresponds to a logical page of data stored by a set of cells that stores additional logical pages. The set of cells may be said to store multiple logical pages in the physical page defined by the set of cells.
• a physical page may comprise all the data storable by a set of cells such as a row at one time. It can also represent the maximum amount of data programmable to the set at one time.
• a "program” command is issued by the controller and input to data input/output buffer 312.
• the command is latched by state machine 316 via the command latch signal input to command circuits 314.
• the data latched in step 506 will be programmed into the selected memory cells controlled by state machine 316 using the stepped pulses of Figure 6 applied to the appropriate word line.
• Vpgm the programming pulse voltage level applied to the selected word line, is initialized to the starting pulse (e.g., 12V) and a program counter PC maintained by state machine 316 is initialized at 0 or another value.
• the first Vpgm pulse is applied to the selected word line.
• the states of the selected memory cells are verified. If it is detected that the target threshold voltage of a selected cell has reached the appropriate level, then the data stored in the corresponding data latch is changed to a logic "1.” If it is detected that the threshold voltage has not reached the appropriate level, the data stored in the corresponding data latch is not changed. In this manner, a bit line having a logic "1" stored in its corresponding data latch does not need to be programmed. When all of the data latches are storing logic "1,” the state machine knows that all selected cells have been programmed. At step 516, it is checked whether all of the data latches are storing logic "1.” If so, the programming process is complete and successful because all selected memory cells were programmed and verified to their target states. A status of "PASS" is reported at step 518.
• step 516 If, at step 516, it is determined that not all of the data latches are storing logic "1," then the programming process continues.
• the program counter PC is checked against a program limit value.
• a program limit value is 20, however, other values can be used in various implementations. If the program counter PC is not less than 20, then it is determined at step 526 whether the number of bits that have not been successfully programmed is equal to or less than a predetermined number. If the number of unsuccessfully programmed bits is equal to or less than the predetermined number, then the programming process is flagged as passed and a status of pass is reported at step 528. The bits that are not successfully programmed can be corrected using error correction during the read process.
• the program process is flagged as failed and a status of fail is reported at step 530. If the program counter PC is less than 20, then the Vpgm level is increased by the step size and the program counter PC is incremented at step 522. After step 522, the process loops back to step 512 to apply the next Vpgm pulse.
• the memory system may receive additional data for one or more arrays while performing any of the operations depicted in Figure 14.
• An additional data load command 502' may be issued by the controller in response to data from the host at anytime. Step 502' may occur in other locations and times than as specifically shown in Figure 14. Data from the host may be received, and a data load command executed at step 502' to load address data at the row controller(s) at step 504' and program data into the available registers at the array at step 506'.
• the controller waits until the state machine or column controller issues an available signal that it can receive more data in the registers.
• the controller and state machine can process the newly received data in various ways.
• the controller stops the current lower page programming operation. This is represented by the arrow from box 508' to box 508.
• the controller then issues a new program command instructing the state machine to program the lower page and upper page data at the same time (concurrently) using full sequence programming.
• the state machine can set ⁇ Vpgm to ⁇ Vpgm2 at step 510' so a larger increment value is used when programming both pages in full sequence.
• the programming operation then continues as previously described, but using the larger increment value ⁇ Vpgm2.
• Vpgm is reset before beginning full sequence and the PC counter is reset to 0.
• Vinitial2 can be equal to, less than, or greater than Vinitiall.
• Vpgm is not reset in all embodiments, however. For example, if the upper page data arrives relatively quickly and only a few program voltage pulses have been applied, Vpgm may begin at its last peak value, at a value larger than the last peak value (incremented by ⁇ Vpgm2 or another value), or at a value smaller than the last peak value.
• Figure 15 is a flowchart depicting more details of setting the program command in step 508' of Figure 14.
• Figure 15 is but one exemplary implementation where a smaller increment value is used for lower page programming and a larger increment value is used for upper page programming or full sequence programming.
• the controller prior to issuing the program command to the column control circuitry, compares the address data of the newly received data with the data currently being programmed for the lower page of the set of memory cells at step 602. If the controller sees a match at step 604, meaning that the data being programmed is for the same memory cells that the newly received data is for, the method proceeds at step 608. In one embodiment, the state machine and/or column control circuitry perform step 604.
• lower page programming continues, e.g., by applying the next program voltage pulse at step 512 of Figure 14.
• the method of Figure 14 may continue at other locations after step 606 of Figure 15 besides step 512.
• the controller determines if lower page programming is complete at step 608.
• Lower page programming may be complete when a predetermined number of program voltage pulses have been applied, when all of the cells to be programmed to state A have been successfully programmed to state A, or when a predetermined number of cells have been successfully programmed to state A.
• the upper page data is programmed into the set of memory cells beginning at step 610, where the upper page program command is issued by the controller.
• step 620 upper page programming continues as depicted at step 510' in Figure 14, where the program voltage signal is initialized to Vinitial2 and ⁇ Vpgm is set to ⁇ Vpgm2.
• a second increment value of ⁇ Vpgm2 is used to increase the size of subsequent programming pulses when programming the upper page of the memory cells. Because the memory cells in state A will have a naturally wider threshold voltage distribution due to subsequently programmed neighbors, a smaller ⁇ Vpgm 1 is used when programming the lower page and a larger ⁇ Vpgm2 is used for the upper page at step 512.
• the controller stops the lower page programming operation at step 612.
• the controller stopping lower page programming is conceptually illustrated by the arrow from step 508' to step 508.
• the controller or state machine can issue a command forcing the column control circuitry to stop programming the lower page of data.
• the controller sets the full sequence program data command at step 614.
• the command is input to buffer 312 and latched by the state machine via the command latch signal input to the command circuitry.
• the state machine is triggered to program the selected memory cells in response to the program command.
• the controller can cause the column control circuitry to perform a verify operation at step 616 to determine which cells have been successfully programmed during the lower page programming.
• step 620 corresponding to step 510' of Figure 14, where the increment value can be adjusted.
• ⁇ Vpgm2 is larger than ⁇ Vpgml in one embodiment.
• a lower ⁇ Vpgml is used for lower page programming or for programming the lowest programmed physical state in order to reduce the width of the state A distributions after programming. Because of the additional capacitive coupling effects experienced by the cells in state A, the lower ⁇ Vpgm value is used to avoid over programming and/or causing program disturb.
• step 510' further includes resetting the initial value of Vpgm.
• Vpgm may be reset to a lower value before applying the voltage signal to program the upper page or to program in full sequence.
• Vpgm is reset to the same starting value as when beginning the lower page programming.
• Vpgm is reset to a value lower than its current value but not as low as the original value for lower page programming.
• the program voltage signal is increased or decreased by a third increment value ⁇ Vpgm3 from the last value used when programming the lower page.
• the program voltage signal Vpgm is not reset before beginning upper page or full sequence programming.
• the last voltage pulse for lower page programming is increased by ⁇ Vpgm2 in one embodiment.
• the last voltage pulse for lower page programming is increased by ⁇ Vpgm3 for the first upper page or full sequence pulse.
• the value is increased by ⁇ Vpgm2 as described.
• ⁇ Vpgm3 can be larger than ⁇ Vpgm2 to provide a more stable transition between the two programming rates that result from the two different step sizes.
• Step 510' can also include resetting the program counter PC.
• a maximum number of pulses can be established independently for lower page and upper page or full sequence programming.
• the counter PC can be reset to 0 or another value.
• the counter PC is not reset and a total maximum number of iterations or pulses for the whole programming operation are used. Other variations may be practiced in accordance with embodiments.
• the increment value for the program voltage pulses is not increased until programming the lowest programmed state is complete, even after transitioning to full sequence programming. If the controller determines that lower page programming is complete at step 608. The operation proceeds at step 610 as already described. If lower page programming has not completed, however, the controller stops the lower page programming process and coverts to full sequence programming as illustrated at steps 612-618. However, the program voltage increment value will not be changed to ⁇ Vpgm2 until programming for the lowest programmed state (e.g., state A) has completed. When all or a predetermined cells are verified as having reached state A, the program voltage increment value can be changed to ⁇ Vpgm2.
• a predetermined number of program voltage pulses is selected and used to determine when to switch to ⁇ Vpgm2. For example, after switching to full sequence programming, the program voltage increment value can be changed to ⁇ Vpgm2 after a predetermined number of program voltage pulses have been applied since originally beginning the lower page programming process.
• a determination that lower page programming is complete at step 608 can be based on a predetermined number of iterations of the lower page programming cycle (i.e., predetermined number of program voltage pulses), regardless of whether the cells are actually programmed to the appropriate state (e.g., state A).
• Lower page programming can also be determined to be complete when a predetermined number of cells have reached the appropriate state, which could be before the entire set of cells normally required to verify successful lower page programming has reached the appropriate state. In either of these instances, some cells may need additional programming based on the lower page data after resetting the program voltage signal and using an increment value of ⁇ Vpgm2. This can be handled during upper page programming at step 610 by not locking out those cells to be programmed to state A that have not verified as having reached state A, and continuing to verify at the state A level during upper page programming.
• ⁇ Vpgm is not changed to ⁇ Vpgm2 until programming for the lowest programmed state completes.
• ⁇ Vpgml will continue to be used during upper page programming until programming for the lowest programmed state is verified. For example, after a predetermined number of the cells to be programmed to state A have reached state A, ⁇ Vpgm can be changed from ⁇ Vpgml to ⁇ Vpgm2.
• the controller does not stop the lower page programming process and convert to full sequence programming immediately upon receiving the upper page data if the lower page programming is not complete as determined at step 608. Rather, the controller waits until it determines that lower page programming is complete before trans itioning.
• Figure 16 is a flowchart of a method that only changes the increment value after additional data is received if programming for the lower page is complete.
• the technique can switch increment values when transitioning from lower page programming to upper page programming or from lower page programming to full sequence programming.
• Lower page data is received at step 704.
• the address data is set at step 706, program data is input at step 708, and the controller issues the program command at step 710.
• Vpgm is set to its initial value, the program counter initialized, and ⁇ Vpgm set to ⁇ Vpgml at step 712.
• the lower page data is programmed at step 714, for example as shown in Figure 14 (steps 512-530). While programming the lower page, upper page data is received at step 716.
• the address data is set at step 718 and the program data input at step 720.
• the controller determines if lower page programming is complete at step 722. As previously described for step 608 of Figure 15, determining if state A programming is complete can be performed in various ways. A determination can be made if all or a predetermined number of the cells to be programmed to state A have reached state A. In other instances, step 722 can include determining if a predetermined number of pulses have been applied and if so, determine that lower page programming is complete.
• step 724 the controller continues lower page programming at step 724 and continues in this loop to wait for lower page programming to complete.
• step 726 the controller issues an updated program command.
• the controller can reset Vpgm to an intial value Vinitial2, reset the increment value ⁇ Vpgm to ⁇ Vpgm2, and reset the program counter PC at step 728.
• After resetting the signals which can be performed by resetting a digital to analog converter responsible for providing the program voltage signal, programming under the new command begins at step 730.
• the program command set at step 726 is for upper page programming.
• the controller can wait until programming for state A is successfully verified before determining that lower page programming is complete.
• the lower page programming data is already programmed and programming for the upper page is all that needs to be performed at step 730.
• the upper page program command can be issued at 726 and programming continue for the upper page at step 730 as soon as lower page programming completes.
• ⁇ Vpgm is not reset at step 728 until programming for the lowest programmed state is verified as complete.
• a determination that lower page programming is complete at step 722 is made when some cells may still need to be raised to state A (e.g., by determining based on a predetermined number of pulses)
• programming can transition to full sequence programming at step 726 in one embodiment. Verification can be performed before applying the first program voltage pulse for full sequence programming. Any cells that reached their final target state during lower page programming can be locked out from additional programming during full sequence programming. Any cells to be programmed to state A that had not reached state A by the time a determination that lower page programming was complete will undergo additional programming during the full sequence iterations.
• the full sequence programming can perform verification at the state A level so that cells that did not reach their target A state during lower page programming can be programmed to state A during full sequence programming.
• the transition to full sequence programming at step 726 is made when lower page programming completes but the program voltage increment value is not changed to ⁇ Vpgm2 until the lowest programmed state is verified as complete (if not already so verified).
• Embodiments that only transition to full sequence programming (or upper page programming) and a larger increment value after completing lower page programming as shown in Figure 16 may provide benefits in particular implementations.
• some memory devices will use a digital to analog converter to produce a program voltage signal for the different sized program voltage pulses.
• the digital to analog converter can form part of the row control circuitry in one embodiment.
• Some converters rely on a digital input value to produce analog program voltage pulses having the requisite peak values.
• altering a program voltage increment value in the middle of a program voltage pulse sequence may prove problematic. Changing the increment size may not produce the next pulse with a peak value equal to the previous pulse plus the new increment value.
• the system will wait for lower page programming to complete.
• the digital to analog converter can be reset with the new increment value as well and an initial program voltage pulse size. This will avoid any inconsistencies or large jumps in the program voltage pulse values.
• embodiments have been described in accordance with transitions from lower page programming to full sequence programming or from lower page programming to upper page programming, embodiments can be applied to single type programming operations.
• a smaller increment value ⁇ Vpgml is used when programming the lowest programmed state in full sequence programming.
• the ⁇ Vpgm can be reset to a larger increment value ⁇ Vpgm2.
• the increment value is still adjusted to more precisely the lowest level programmed state.
• statistics are used to predict when the lowest programmed state will complete programming.
• the program voltage increment size can be changed after the predicted completion of lower state programming. For example, it may be determined that the lower state completes programming after 8 pulses 90% of the time.
• the programming algorithm could use a smaller ⁇ Vpgml for the first eight program voltage pulses and then switch to a larger increment value ⁇ Vpgm2 for the remaining pulses. In this manner, no circuitry is necessary to assess whether lower page programming is actually complete and alter the program voltage increment value in response. Rather, the increment value is automatically changed after a specified or predetermined number of pulse or applications of the program voltage signal.
• This approach can be used with any of the aforementioned techniques that wait for the lowest programmed state to complete programming before switching the increment value.
• the predetermined number of pulses applied before switching to ⁇ Vpgm2 as previously described can be based on statistical estimations of when programming cells to state A will be complete.
• a coarse programming phase includes an attempt to raise a threshold voltage in a faster manner while paying less attention to achieving a tight threshold voltage distribution.
• the fine programming phase attempts to raise the threshold voltage in a slower manner in order to reach the target threshold voltage, thus achieving a tighter threshold voltage distribution.
• One example of a coarse/fine programming methodology can be found in United States Patent 6,643,188, incorporated herein by reference in its entirety.
• Figures 17 and 18 provide more detail of one example of a coarse/fine programming methodology.
• Figures 17A and 18A depict the programming pulses V pgm applied to the control gate.
• Figures 17B and 18B depict the bit line voltages for the memory cells being programmed.
• Figures 17C and 18C depict the threshold voltage of the memory cells being programmed.
• This example depicts programming of memory cells to state A using two verify levels, indicated in the Figures as V VAI and V VA - The final target level is V VA .
• V VAI verify levels
• V VA - The final target level is V VA .
• the bit line voltage can be raised to V inh ibit (See Figure 17B and Figure 17B).
• V inh ibit See Figure 17B and Figure 17B.
• the threshold voltage shift of the memory cell during subsequent programming pulses is slowed down by applying a certain bias voltage to the bit line, typically on the order of 0.3v to 0.8v. Because the rate of threshold voltage shift is reduced during the next few programming pulses, the final threshold voltage distribution can be narrower.
• a second verify level that is lower than that of V VA is used.
• This second verify level is depicted in Figures 17 and 18 as V VAI -
• V VAI bit line bias
• Figures 17 A, 17B, and 17C show the behavior of a memory cell whose threshold voltage moves past V VAI and V VA in one programming pulse.
• the threshold voltage is depicted in Figure 17C to pass V VAI and Vv A in between t 2 and t 3 .
• the memory cell prior to t 3 , the memory cell is in the coarse phase.
• the memory cell is in the inhibit mode.
• Figures 18A, 18B, and 18C depict a memory cell that enters both the coarse and fine programming phases. The threshold voltage of the memory cell crosses V VAI in between time t 2 and time t3. Prior to t3, the memory cell is in the coarse phase.
• the bit line voltage is raised to Vs to place the memory cell in the fine phase.
• the threshold voltage of the memory cell crosses V VA . Therefore, the memory cell is inhibited from further programming by raising the bit line voltage to V in hibit-
• these coarse/fine programming techniques are used when changing increment values.
• the use of coarse/fine programming can produce a narrower threshold distribution. This can be used to compensate for any increase in the width of a distribution that results from using a larger increment value.
• These techniques can be incorporated into the change in increment values in various fashions.
• coarse/fine programming can be used when programming and verifying each state in one embodiment.
• coarse/fine programming can be used in conjunction with the switch in increment values.
• a single final verify level can be used when programming the lower page for determining if the cells have reached state A for example.
• coarse/fine programming can be instigated.
• coarse and fine verify levels are used for each state during the full sequence or upper page programming.
• coarse and fine verify levels are only used for a select state or states. For example, coarse and fine levels could be used just for state B and state C or just state C.

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