TW200837760A - Systems utilizing variable program voltage increment values in non-volatile memory program operations - Google Patents

Abstract

The lowest programmed state in multi-state non-volatile flash memory devices can suffer from an increased level of bit line to bit line capacitive charge coupling when compared with other states. Program voltages applied to memory cells as increasing voltage pulses can be incremented using smaller values when programming memory cells to the lowest programmable state. Smaller increments in the applied voltage allow for greater precision and a narrower threshold voltage distribution to compensate for the disproportionate charge coupling experienced by cells programmed to this state. Smaller increment values can be used when switching from lower page to upper page programming in some implementations. In a pipelined programming architecture where cells forming a physical page store two logical pages of data and programming for one logical page begins before receiving data for the other logical page, the increment value can be increased when switching from programming the first logical page to programming both pages concurrently.

Description

200837760 IX. Description of the Invention: [Technical Field of the Invention] A specific embodiment according to the present invention relates to a stylized non-volatile memory. [Prior Art] • Semiconductor memory devices have become more and more widely used in various electronic devices. For example, non-volatile semiconductor memory is used in mobile phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices. Electrically Erasable Programmable Read Only Memory (EEPROM) (including flash EEPROM) and Electrically Programmable Read Only Memory (EPROM) are the most common Non-volatile semiconductor memory.

One example of a flash memory system uses a NAND structure that includes a plurality of transistors arranged in series between two select gates. The transistors in series and the select gates are referred to as a NAND string. Figure 1 shows NAND

Top view of the C string. Figure 2 shows its equivalent circuit. The NAND string shown in Figures 1 and 2 includes four transistors 100, 102, 104 and 106 sandwiched between a first select gate 120 and a second select gate 122. Select gate 120 connects the NAND string to bit line 126. Select gate 122 connects the NAND string to source line 128. The selection gate 120 is controlled by applying an appropriate voltage to the control gate 120CG via the select line SGD. The selection gate 122 is controlled by applying an appropriate voltage to the control gate 122CG via the selection line SGS. The transistors 100, 102, 104 and 106 each comprise a control gate and a floating gate 125212.doc 200837760 pole forming a gate element of a memory cell. For example, the transistor 1 has a control gate 100CG and a floating gate 100FG. The transistor 102 includes a control gate 102CG and a floating gate 102FG. The transistor 104 includes a control gate 104CG and a floating gate 104FG. The transistor 106 includes a control gate 106CG and a floating gate 106FG. Control gate 100CG is coupled to word line WL3, control gate 102CG is coupled to word line WL2, control gate 104CG is coupled to word line WL1, and control gate 106CG is coupled to word line WL0. Note that although Figures 1 and 2 illustrate that there are four memory cells in the NAND string, the use of four memory cells is provided as an example only. A NAND string can have fewer than four memory cells or more than four memory cells. For example, some NAND strings will include 8 memory cells, 16 memory cells, 32 memory cells, and the like. The discussion herein does not limit the number of any particular memory cells in a NAND string. A typical architecture for a flash memory system using a NAND structure would include several NAND strings. For example, Figure 3 illustrates three NAND strings 202, 204, and 206 having a memory array of more NAND strings. Each of the NAND strings shown in Figure 3 includes two select transistors (or select gates) and four memory cells. For example, NAND string 202 includes select transistors 220 and 230 and memory cells 222, 224, 226, and 228. NAND string 204 includes select transistors 240 and 250 and memory cells 242, 244, 246, and 248. Each string is connected to the source line by a select gate (e.g., select gate 23 0 and select gate 250). A select line SGS is used to control the source side select gate. The various NAND strings are connected to their respective bit lines by selecting gates 125212.doc 200837760 220, 240 (controlled by select line SGD) and the like. In other embodiments, the select lines are not necessarily to be common lines. Word line WL3 is connected to the control unit of memory unit 222 and memory unit 242. The word line WL2 is connected to the (four) gate of the memory unit 224 and the memory unit 244. Word line WL1 is connected to memory unit 226 and memory list

Control gate of element 246. The word line WL 〇 is connected to the memory cell 2 and the control gate of the memory cell 248. As shown, a single bit line and a respective NAND wide string form one row of a memory cell array. The word lines (WL1, WL2, WL3, and WL4) form a matrix. Each word line connects to the control gate of each of the memory cells in the column. For example, word line hunger 2 is connected to the control gates of memory cells 224, 244, and 252. The parent-hidden unit can store data (analog or digital). When storing a one-digit digital data, the possible threshold voltage range of the memory unit is divided into two ranges that are assigned as logical data "丨,, and "〇,. In the nand type>, the case of the L-body, the threshold iy after the memory cell is erased (negative and derogated as logic "1". The threshold ink after the stylization operation Positive and defined as logic, "When the threshold voltage is negative and an attempt is made to apply a 〇, 彳 制 gate for reading, the memory unit will be turned on to indicate that the memory is being stored. When the voltage is positive and an attempt is made to apply the sag to the control gate, the memory cell is not turned on, indicating that the logic "0" is stored. The memory cell can also store multiple levels of information, for example, Evening digit data. If multiple levels of data are stored, the possible threshold voltage range can be obtained from the number of data. For example, if you store four quasi-before, there are four paragraphs. The voltage limit range is assigned as the data value 125212.doc 200837760 "11", "10", "01" and "00". In one example of the NAND type memory, the threshold voltage after the erase operation is negative and Is defined as "丨丨,,. Three different positive threshold voltages are used for "10", "01,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, U.S. Patent No. 5,570,315; U.S. Patent No. 5,774,397; U.S. Patent No. 6,046,935; U.S. Patent No. 6,456,528; and U.S. Patent Application Serial No. 9/893,277, US 2003/0002348). When programming an EEPROM or flash memory device, typically a program voltage is applied to the control gate and the bit line is grounded. The electrons from the channel are injected into the floating gate. When accumulating in the floating gate, the floating gate becomes a negative load state, and the threshold voltage of the memory cell rises, so that the memory cell is in a stylized state. The floating gate charge and threshold of the memory cell The voltage may indicate a particular state corresponding to the stored lean material. For more information on stylization, please refer to U.S. Patent Application Serial No. 1/379,6,8, filed on March 5, 2003. U.S. Patent Application Serial No. 10/629,068, filed on Jul. 29, 2003, entitled "Detecting 〇ver Programmed Memory", the entire contents of which are incorporated herein by reference. The offset of the apparent charge stored on the floating gate can be caused by the electric field coupling based on the charge stored in the adjacent floating gate. This floating gate to floating gate is described in U.S. Patent No. 5,867,429. 125212.doc 200837760 Boxing phenomenon 'The whole content of this case is incorporated herein by reference. The adjacent floating gates of the target floating gate may include: ~ j including: adjacent floating gates on the same bit line; adjacent oceanic gates located on the same Fengqi μ dim - a U sub-line, or located Near the bit line and the Zheng near word line, the hundreds of sub-gates, and thus cross each other in the diagonal direction. (d) The most significant (but not exclusive) phenomenon of gate-to-floating gates occurs between several sets of adjacent memory cells that have been programmed at different times. In contrast, the 'memory memory cell' is programmed to add the -charge level to its net-drive gate' which corresponds to a set of data. Thereafter, one or more adjacent memory cells are programmed to add a charge level to their floating gate, and (4) to the group data. After - or more of the adjacent memory cells are processed, the first memory is read because the charge on the adjacent memory cells is coupled to the first memory cell. The unit's electrical standard seems to be different from the programmed charge level. Coupling from an adjacent memory allows the apparent charge level in the read to be offset with an offset sufficient to cause erroneous reading of the stored data. ^Because the allowable threshold voltage range and the disable range in the multi-state device ('I differs between the different threshold voltage ranges of the memory state: 1巳) Binary device, so for multi-shape: the device is more concerned with the effect of floating gate to floating gate coupling. Therefore, the /-sub-pole-to-floating gate face-to-face phenomenon can cause the memory single-it-permitted threshold voltage range to be shifted to the disabled range. Also thinking about the size of the U-body unit continues to shrink, it is expected that the natural threshold voltage is a knives due to the short channel effect, the larger oxide thickness 125212.doc 200837760 ratio change and larger channel doping The debris increases and fluctuates, thus reducing the available separation between adjacent states. This effect of multi-state memory is more pronounced than binary memory using only two states. In addition, the space between the sub-lines and the reduction in space between the bit lines will also increase the coupling between adjacent floating gates. SUMMARY OF THE INVENTION In a multi-state non-volatile flash memory, a bit line-to-bit line capacitance charge coupling with an increased level can be encountered with its low programmed state. When the memory cell is programmed to the lowest programmable level or state, the program voltage applied to the memory cell can be incremented with a smaller value as the voltage pulse is increased. The smaller the amount of increase in the applied voltage, the higher the accuracy and the narrower the threshold voltage distribution to compensate for the unbalanced charge encounters encountered by the memory cells programmed into this state. In a specific example 5, when a first logical page is programmed, a smaller increment value can be used, and when other pages are programmed, a larger increment value can be used. In a pipelined privateization architecture (where the memory cells forming a physical page store (4) logical pages: data, and the stylization of the logical pages begins before receiving another = page), when self-programming When the first-logical page is switched to the two pages that are stylized, the increment value can be increased. In a specific embodiment, the method of 袒# < 1 includes: 接接 = non-volatile storage of the storage element 1 & formulaized batting to - group multi-state non-swing To the New Zealand to add pre-determined (four) storage elements, and: to programmatically program the data to the non-volatile σ or a plurality of additional program voltage pulses to the group of non-125212.doc 200837760 volatile storage elements to complete „ Styling the material. Applying a predetermined number of programs to the set of multi-state non-volatile storage elements may include increasing the size of each of the program's pulses by a 帛-increment value until arrival The predetermined number. Applying - or a plurality of additional program voltage pulses to the set of multi-state non-volatile (four) storage elements can include: increasing each of the one or more additional program voltage pulses by a first increment value One size.

In a specific embodiment, a method of staging a non-volatile storage device is provided. Receiving - The first set of data, the first set of data is designated for storage in a physical page of a non-volatile storage device. The first set of data may include less than the maximum amount of data that can be stored on the physical page. In the specific embodiment, the first set of data is formed on the lower logical page data. The first set of bead material is programmed into the physical page by using a program voltage signal to program the data. The program voltage signal has a peak value. When the data is stylized to the physical page, the first An increment value is used to increment the peak. A second set of data is received, which is also designated for storage in the physical page. The second set of data may be received after beginning to program the first set of data to the physical page and before completing the stylization of the first set of data to the physical page. Responding to receiving the first set of data prior to completing the stylization of the first set of data 'stops or interrupts the stylized first set of data. After the programming of the first set of data is stopped, the first set of data and the second set of data are programmed in parallel to the physical page. The parallel programming may include: using a program voltage signal to program the first data and the second data, the program voltage signal having a peak value, when the first data and the second data are programmed to the 125212.doc -12- 200837760 Body page 递增 increments the peak with a first increment value. And in two specific embodiments, a non-volatile memory system is provided, 4 is a hard number of storage elements; a plurality of data buffers, basins

2 storing 7° pieces of communication; and managing circuitry, and receiving, by the buffer (4) component management circuit, the first data to be stored in the storage (4), and responding, providing the first data to the buffers One of the group buffers in the device. The management circuit programs the first data to the storage elements using a plurality of program voltage pulses that are incremented by a -th increment value. The official circuit receives the data to be stored in the storage element when the first data is programmed and makes a call to provide the second data to the second set of buffers of the & The management circuit stops programming the first data to the storage elements and begins to program the first data and the second data in parallel using a plurality of program voltage pulses that are incremented by a second increment value Store components. Other features, aspects, and objectives of the specific embodiments of the disclosed technology will be apparent from the scope of the appended claims. [Embodiment] FIG. 4 is a block diagram showing one embodiment of a flash:recognition system that can be used to implement one or more embodiments of the present invention. Other systems and implementations can be used. The memory cell array 3〇2 is controlled by a row control circuit 〇4, a column control circuit 306, a common source line control circuit 310, and a ρ well control circuit 308. The 仃 control circuit 〇4 is connected to the bit line of the memory cell array for: reading data of the material in the memory unit; 敎 the state of the memory cell during the stylizing operation; and controlling the potential of the bit line Bit 125212.doc •13- 200837760 is intended to facilitate or prohibit stylization and erasure. Column control circuit 306 is coupled to the sub-wire ' to: select one of the word lines; apply a read voltage; apply a program voltage 结合 in conjunction with a bit line potential level controlled by row control circuit 304 and apply an erase voltage . The common source line control circuit 3 丨〇 controls a common source line (labeled as "common source line" in Fig. 5) connected to the memory unit. The ρ well control circuit 308 controls the ρ well voltage. The data stored in the unit is read by the row control circuit 3 and output to the external "〇 line via the data input/output buffer 312. The data to be stored in the memory unit is via the external 1/ The line is input to the data input/output buffer 312, and is transmitted to the line control circuit 304. The 1/〇 lines are connected to the controller 3 j 8. Command data for controlling the flash memory device It is input to the controller 318. The command data informs the flash memory of the required operation. The input command is transmitted to the state machine 316 belonging to the components of the control circuit 315. The sorcerer 316 controls the row control circuit 3〇4, Column control circuit 〇6, common source line control circuit 310, P-well control circuit 308, and data input/output buffer 3 12. The sorcerer 3 16 can also output status data of the flash memory, such as, ready /busy" (rEADY/busy) or "pass/fail". The controller 318 is connected to or connectable to the main (four) system, such as a personal ~ t brain, a digital camera or a personal digital assistant, etc. The controller and the starting life 7 Host communication, such as storing data to or reading data from the memory array, and providing or receiving such data. The controller 3 18 converts the commands into commands via the command circuit 314 (which belongs to The command signal is interpreted and executed by the control circuit 315. The command circuit 314 is in communication with the state machine 316 of 125212.doc -14-200837760. The controller 318 typically includes a buffer memory for writing to the memory array or User data read from the memory array. An exemplary memory system includes an integrated circuit (which includes controller 3 18) and one or more integrated circuit chips (each integrated circuit chip contains a memory) Body arrays and associated control, input/output, and state machine circuits. One trend is to integrate a system of memory arrays and controller circuits on one or more integrated circuit chips. The system can be embedded as a component of the host system or can be included in a removable memory card (or other package) that can be removably inserted into the host system. This memory card can include the entire memory system (eg, , including the controller), or only the memory array and associated peripheral circuits (along with controllers or control functions embedded in the host). Therefore, the controller can be embedded in the host or included in the removable Within the system of the memory system, see FIG. 5' to describe an exemplary structure of the memory cell array 302. As an item, a NAND flash EEPROM divided into 1, 24 blocks is described. The data stored in each block can be erased at the same time. In a specific example, the block is the smallest unit of memory cells that are simultaneously erased. In this example, each block has 8, 5 12 rows. Each block is typically divided into several pages (possibly a stylized unit). Other stylized information °° is also practicable and considered. In a specific embodiment, individual pages can be knifed into segments, and the segments can include a minimum number of memory cells that are written at a time as a localized private operation. One or the eve page is typically stored in a list of memory cells. |^| 5 0|Tr — There are not only 8 and 5 12 lines in each block, but it is divided into even 125212.doc -15· 200837760 lines and odd lines. The bit lines are divided into even bit lines (Β^) and odd bit lines (BLo). In an odd/even bit line architecture, a memory of a memory element along a common word line connected to an odd bit line is performed, and a memory along a common word line and connected to an even bit line is performed. The body unit is further stylized. Figure 5 illustrates four memory cells connected in series to form a ΝΑ string. Although four memory cells are included in each _ Ναν〇 string, four or more memory cells (e.g., H or other numbers) may be used. The terminal of the NAND string is connected to the corresponding bit line ' via a first selection transistor or gate (which is connected to the selected interpole line SGD) and the other terminal is via the second selection A crystal (which is connected to the select gate source line SGS) is connected to a common source line. In other implementations, the bit lines are not divided into even and odd bit lines. This type of architecture is often referred to as the "full bit line architecture". In a full bit line architecture, all bit lines of a block are selected simultaneously during read and program operations. Memory cells along the - common word line and connected to any bit line are simultaneously programmed. During the read and stylization operations of the particular embodiment, 4'256 memory cells are simultaneously selected. The selected memory cells have the same word line (eg, 'WL2-0 and the same bit line (eg, even bit line). Therefore, 532 bytes of data can be read or programmed simultaneously. The 532 bytes of data obtained or stylized form a cough ^ ^ logical page. Therefore, in this example, '-blocks can store at least eight pages. When each memory unit stores two bits of data Time (for example, a multi-level memory unit), 125212.doc * 16 - 200837760 One block stores 16 pages. The specific embodiment can also use other sizes of blocks and pages can also be used in addition to Figures 4 and 5 The embodiment is implemented by a different architecture. The way to erase the memory cell is to raise the p-well to an erase voltage (eg, 20 volts) and ground the word line of a selected block. The line and bit line are in a floating state. Erasing can be performed on the entire memory array, separate blocks, or other memory unit units. Electrons are transferred from the floating gate (Λ to the Sakai area, and the threshold voltage becomes Negative (in a specific embodiment). In the verifying operation, the select gate of a selected block is raised to one or more select voltages, and the unselected word lines (eg, WL0, WL1, and WL3) of the selected block are raised to a read transfer voltage. (eg, 4.5 volts) to operate the transistor as a transfer gate. The selected word line (eg, WL2) of the selected block is connected to a reference voltage, which is specified for each read and verify operation The level of the voltage to determine whether the threshold voltage of the memory cell involved is higher or lower than the level of the reference voltage. For example, in the read operation of the one-bit memory cell, the selected The word line WL2 is grounded to detect whether its threshold voltage is higher than the stagnation. In the verify operation of the one-bit memory cell, the selected word line WL2 is connected to, for example, 0.8 volts, so that During the stylization process, it is detected whether the threshold voltage has reached 0.8 volts. During reading and verification, the source and p wells are zero volts. The selected bit line (BLe) is precharged (eg ) 〇 7 volts. If the threshold voltage is higher than the read or verify level Because of the associated non-conducting state memory cell, the potential level of the bit line (BLe) involved is maintained at a high level. On the other hand, if the threshold voltage is lower than the read or verify bit 125212.doc -17 - 200837760 准, because of the conduction state of the memory cell, the potential level of the bit line (BLe) involved is reduced to a low level, for example, less than 0.5 volts. By means of a sense amplifier connected to the bit line Detecting the state of the memory cell and sensing the resulting bit line voltage. The difference between whether the memory cell is programmed or erased depends on whether the net negative charge is stored in the floating gate. If a negative charge is stored in the floating gate, the threshold voltage becomes higher and the transistor may be in an enhanced mode of operation. In one example, when staging a memory cell, the drain and p wells receive 0 volts, while the gate receives a series of stylized pulses of increasing magnitude. In a specific embodiment, the pulse magnitude of the series of pulses is in the range of Μ to 24 volts. In other embodiments, the pulse range of the pulse may be different ', for example, having a starting level above 12 volts. During the stylization of the memory unit, the verify operation is performed during the period between the stylized pulses. That is, the programmed level of each memory cell in a group of memory cells being serialized in parallel is read between each stylized pulse to determine if the memory cell has reached or exceeded The level of verification applied to it when stylized. One means of verifying stylization is to test the conduction of a particular comparison point. Memory cells that have been verified to be fully programmed are locked. For example, in a NAND memory cell, the lock mode is such that for all subsequent stylized pulses, the bit line rises from 〇 to Vdd (eg, 2·5)伏)' to terminate the stylized processing of their memory cells. In some cases, the number of pulses (e.g., 2 pulses) will be limited, and if the last pulse does not adequately program a given memory cell, then an error is assumed. In some embodiments, the 125212.doc 18 200837760 memory unit (in blocks or other units) is erased prior to stylization. Figure 6 illustrates a stylized voltage signal according to a specific real family of mussels. This signal has a set of pulses with increasing magnitudes. The magnitude of the pulses is incremented by a predetermined step size with each pulse (four). In the embodiment of the memory list (10) containing the multi-bit data of the museum, the exemplary step size is 〇·2 volts (or 〇·4 volts). The verification pulse is between each stylized pulse. The signal of Figure 6 assumes a four-state memory unit, so the signal includes three verify pulses. For example, there are three consecutive verify pulses between the stylized pulses 330 and 332. One of the first verification pulses 334 is shown to be at a zero volt verify voltage level. The second verify pulse 336 following the first-verify pulse is at the second verify voltage level. The third verification pulse 338 connected to the second verification pulse is at the third verification voltage level. The multi-state memory unit capable of storing data in eight kinds of sorrows may have to perform verification operations at seven comparison points. . Therefore, seven verify pulses are sequentially applied between the two consecutive stylized pulses to perform the verify operation at the seven verification C levels. The system can determine the state of the memory unit based on seven verification operations. - The means of reducing the verification time load is to use a more efficient verification process, for example, as disclosed in the following patent application, Patent Application No. 1/314, filed on December 5, 2002, 〇55 titled "Smart Verify for Multi_State Memories"; Patent Application No. 11/259,799, filed on January 27, 2005, entitled "Apparatus f〇r Programming of Multi-State Non-Volatile Memory Using Smart Verify ; and Patent Application No. 11/260,658, filed October 27, 2005, entitled ''Method for Programming 〇f Multi- 125212.doc -19· 200837760

State Non_v〇iatile Mem〇ry using Smart Verify, the entire contents of which are incorporated herein by reference. The erasing, capture and verification operations described above are carried out according to techniques well known in the art. Therefore, those skilled in the art can change many of the details explained. Right, at the end of the successful stylization process, the memory unit's solar C should be in one or more of the private memory cells. Voltage limit

Within a knife cloth or within a threshold voltage distribution of the erased memory cell. Figure 7 shows the fe limit voltage distribution of the memory array when each memory cell stores two bits of data. Figure 7 illustrates a first threshold voltage distribution E of the erased memory cell. Three threshold voltage distributions A, BW of the stylized memory unit are also depicted. In a specific embodiment, the threshold voltage in the distribution is negative, and the threshold voltage in the A, B*c distribution is positive. The parent-individual threshold voltage range of Figure 7 corresponds to a pre-S decision value for each set of data bits. The specific relationship between the data of the stylized (4) unit towel and the threshold voltage level of the memory unit depends on the data encoding scheme used by the memory unit. In a specific embodiment, a (four) Gray code assignment is used to assign data values to the threshold voltage limits such that if a threshold voltage of a floating gate is erroneously offset to its vicinity Entity status, only one bit will be affected. However, in other specific embodiments, the snow paper coding method is not used. An example assigns "11" to the threshold voltage range E (distance from E) · and, 1 (, ritual 10, to the threshold voltage range A (displaced from A); assign "00" to the threshold voltage Range B (state B); and assignment "〇i " (4) 125212.doc -20- 200837760 Limit voltage range c (state c). Although Figure 7 shows four states, it can also be combined with other multi-state structures ( The invention is applied to a multi-state structure having four or more states. Figure 7 also shows three read reference voltages VrA, VrB and VrC for reading data from a memory cell. By testing a given memory The threshold of the body unit. Whether the voltage is higher or lower than Vm, VrB and VrC, the system can determine the state of the memory unit. Figure 7 also shows three verification reference voltages VvA, VB and When the memory unit is programmed to state A, the system will test whether the memory unit 70 has a threshold voltage greater than or equal to VvA. When the memory unit is programmed to state B, the system will test whether the memory unit has greater than Or equal to the threshold voltage of VvB. When the memory unit is programmed to state c, The system will determine whether the memory cell has a threshold voltage greater than or equal to νπ. Figure 7 illustrates one embodiment using full sequence stylization. In full sequence programming, the memory cell can be erased from state E. Directly stylized to any of the stylized states A, Β, or C. For example, a population of memory cells to be programmed may be erased first, such that all memory cells in the population are In the erased state E. Next, use the processing procedure described below with reference to Figure 7 (using a series of program voltage pulses applied to the control gate of the selected memory cell) to program the memory cell directly to state A, B or C. When some memory cells are being programmed from state E to state A, other memory cells are being programmed from state E to state β and/or from state E to state C. Figure 8 An example of a two-step process of a stylized multi-state memory unit 125212.doc -21 - 200837760 (two-pass), which stores data for two different pages (the lower page and the upper page). Paint Four states: state E (11), state A (10), state B (00), and state C (01). For state £, the two pages store '·1π. For state A, the lower page stores 〇' And the upper page stores, 丨,,. For state B, the two pages store "〇". For state c, the lower page stores, 1, and the upper page stores "〇". Note that although the specific bit type A bit pattern has been assigned to each state, but different bit patterns can be assigned. In the first stylization process, the memory cells are set according to the bits to be programmed into the lower logical page. Threshold voltage level. If the bit is a logical Π1", the threshold voltage is not changed because it has been properly erased earlier. However, if the bit to be programmed is a logical one, the threshold voltage level of the memory cell is increased to state A, as indicated by arrow 302. This causes the first stylization process to terminate. In the second stylization process, the threshold voltage level of the memory unit is set according to the bit being programmed into the upper logical page. If the upper logical page bit stores a logic "1", since the memory cell is in state E or A (depending on the stylization of the lower page bit), both states carry the upper page bit. Yuan "1", so no stylization occurred. If the upper page bit is logic "0", the threshold voltage is shifted. If the first process causes the memory cell to remain in the erased state E, then in the second phase, the memory bank 7L is programmed such that the threshold voltage is increased to the range of the bear C, as indicated by arrow 306. Shown. If the first stylization process causes the record unit to be privateized to state a, the memory unit is further programmed in the second process such that the threshold voltage is increased to the state B range 125212.doc -22 - 200837760, as indicated by arrow 304. The result of the second process is to program the memory cells into data that is designated to cause the upper page to store logic and without changing the lower page.

1 In one embodiment, a system can be set up to perform a full sequence of writes if sufficient data is written to fill a full page. If the data is not sufficient to write a full page, the stylized program can use the received data to program the lower page. When the follow-up data is received, the system will then program the upper page. In another embodiment, the system can begin to write data using two process techniques, and then if sufficient data is subsequently received, transition to full sequence stylized mode to fill an entire (or majority) The memory unit of the word line. For more information on this specific example, please refer to the inventor Sergy Anatolievich Gorobets and Yan Li on December 4, 2004, U.S. Patent Application Serial No. 11/13, No. 125 entitled "pipelined gramming 〇f Non- Volatile Memories Using Early Data", the entire contents of which is incorporated herein by reference. In addition to the full sequence and upper page_lower page stylization as shown in FIG. 8, according to various embodiments, 'may also be used Other stylized techniques. For example: In one embodiment, a two-stage process technique can be used, which reduces the floating gate to floating gate coupling: for any special port After a single page is written to the previous page of the adjacent memory unit, ^ is a specific page of the unit. In one of the techniques, the code is used, and the four types are used. Data status (for example, non-Gray 2, 2, erased storage 11, stylized states A, B, and c store 01, 10 盥 - /, respectively) store two bit data of the mother memory unit. 125212.d〇i -23- 20083776 0 The parent-body unit stores two pages of data based on the reference destination page and the lower page. In the first process, the lower page is stored in the stylized part page! The memory unit is maintained in state e, material 0 The memory unit rises to the intermediate state B. In the second process: Baye f! 7 is stylized. The memory unit in the upper page where the data 1 is in the state of being erased is maintained in the state E. And to be stored in the upper page: the memory unit in state E is programmed to state A. The memory unit in the intermediate state B where the data 1 is stored in the second part is programmed to In the final state B, the memory unit in the intermediate state B to be stored in the upper page is programmed to the state c.

The table of Figure 9 depicts the various capacitive charge couplings of a single page technique (such as the upper page/lower page stylized version of the insane sequence (--stylized all data states). The table of 9 describes the effects of the four-state memory device, but those skilled in the art should understand that the principle of materialization can be applied to systems with more physical states. In single page customization and full sequence programming Among them, the memory unit programmed to the first programmed state A encounters the most capacitive charge coupling effect. The first column describes the single page stylization (block 382) and the memory unit in state A and its The neighbor is programmed to state c (column 38. The memory unit in state A will increase in its apparent threshold voltage, which is equal to the constant α (representing the coupling coefficient between the floating gates). The product of the voltage change between the erased state Ε and the stylized state C. Because the stylized memory cell is programmed when the first page is programmed, and later when the second page is programmed Adjacent The program is programmed to state C, so the neighbor's 125212.doc -24-200837760 is on the gate: the electricity [will rise] its rise is the difference between the erased state and the program mc. Column 386 lists An exemplary threshold voltage change for a memory cell that is stylized between states in a memory system. In the example provided, staging from state 状态 to state C will shift the threshold voltage by about 6 volts. The memory cell in state 将 will experience the apparent offset in its threshold voltage, which is equal to the product of this difference multiplied by the face factor. The neighbors are privately conditioned to the state Β memory cell Will experience an apparent offset, 彡 equals the constant multiplied by the product of the voltage change (eg, 2 volts) between the first-stylized state A and the first programmed state B. The neighbor is in state C. The memory cell of state B will experience an apparent offset in its threshold voltage, which is equal to the constant multiplying the voltage change between the second programmed B and the second programmed state c (eg, ^ The product of volts. Although the memory unit of state A In the full sequence of stylization, the smaller capacitive charge is combined, but compared with the memory cells in other states, the memory cell of the A is still more capacitively coupled. For its neighbors, it is programmed to The memory unit of state C in state a, in full sequence stylization, after the selected memory unit is programmed, the neighbor will only rise from state A to state C (eg, 2 volts). In the middle, all states are programmed at the same time. Therefore, in most cases, the selected memory unit will arrive at state A at approximately the same time as its neighbors. Therefore, 'the only coupling after the selected memory unit is programmed The effect is reflected by the neighbors moving from state A to state c. The memory unit 125212.doc -25-200837760 whose state is programmed to state B in state B will experience an apparent offset equal to a constant Multiplies the product of the voltage change (eg, 2 volts) between the first programmed state A and the second programmed state B. The memory cell in state B whose state is in state B will experience an apparent offset in its threshold voltage, which is equal to the constant multiplication between the second programmed B and the third programmed state c. The product of the voltage change (for example, 2 volts). As shown in Figure 9, the memory cells in the lowest programmed entity state will encounter the most capacitive charge coupling from the later programmed neighbors. These unbalanced coupling effects can widen the A-state distribution and may cause errors in this term. To compensate for the larger apparent threshold voltage offset experienced by the memory cells in the first programmed state, in one embodiment, the first programmed state is programmed with higher accuracy to compensate Additional charge coupling effect. In various embodiments, techniques are used to achieve a tighter threshold voltage distribution of the first programmed state to compensate for subsequent changes in its apparent threshold voltage. In one embodiment, a smaller increment value can be used for the program voltage signal when the program memory is 7G to the lowest programmable state. In another embodiment, when the first logical page data is programmed to a set of memory cells, the increment value is smaller; when the second logical page data is programmed to the set of memory cells, the increment value is compared. Big. In a pipelined architecture, the incremental value can be increased when the memory is programmed from a single page to a full sequence. Figure 10 illustrates a sequence diagram of a non-volatile memory system processing and writing individual logical page data. The first page of a set of memory cells is first completed, and then the second page of data is started. The lean material from the main unit 125212.doc •26-200837760 is first received at the controller. The controller forwards the data and the address information to the row control circuit, and the current control device places the data in the data register. In Fig. 1〇, the controller _τ is for the =I memory unit Page data, after which it receives: top: page data. Loads the appropriate scratchpad and responds to the command from the control's program. At time _, the state machine will start to program the lower page data to the group of memory. In the body unit, after the interval t1, the data for the upper page data of the corresponding group memory unit is received from the host. At time m2, the controller completes the register order to the person at the array. In a particular embodiment, the system up to: the programmed lower page is to program the upper page data. Accordingly, the state machine subsequently privateizes the lower page data into the set of memory cells until time u' and The upper page data is maintained in the scratchpad. Once the lower page data is processed, the controller can issue a program command for the upper page data, and the sorrow machine responds to program the upper page data from the scratchpad to In the array. As mentioned, (4) The page includes staging the memory unit from state E to state C and from state A to state B. In the case of the alternative, the use of the sub-process technique, as described above, makes the stylized upper part The page includes staging the memory unit from the state to the state and staging from the intermediate state to state B and state c. According to a particular embodiment of the technology disclosed herein, in one embodiment as shown in FIG. When the upper page is programmed at time t3, the program voltage signal is used with a different increment value. Figure u illustrates the program voltage tfl number according to an embodiment. The memory unit is programmed from the erased state to the state. A begins with the time u when a first program voltage pulse is applied. After 125212.doc -27·200837760, only one verification is performed to determine the memory unit (if any) that is programmed to state A. The extra pulse, whose peak value is incremented by ΔVmm. Continue this process private sequence until the lower page is programmed at time t3. After the program voltage pulse reaches the predetermined maximum number, or wait for • autumn After the sufficient number of memory cells of state A have been successfully verified as having arrived at A, the lower page stylization can be completed. As the memory cells are formatted as state A, or as the lower page is programmed The program value is changed to AVPgm2. In a specific embodiment, Δνρ(f) is greater than AVpgml in order to speed up the privateization process. In the specific embodiment, after the analysis is performed to determine the appropriate value, AVpgm2, which causes most of the memory cells in the array to be optimized (larger increments), but also ensures accurate stylized data (smaller increments). The value can be adjusted to ΔVPgm2 to Compensating for the increased amount of charge coupling experienced by the memory cells programmed to state 。. For example, Δνρ (f) can be reduced from the AVpgm2 value depending on the amount of additional capacitance charge received. Please refer to 1/Fig. 9 for example. When the stylized state is lower than ΔνΡΕηι1, the difference of 4 volts in the floating gate voltage of its neighbors after the simplification can be based on the stylized state. A 2 volt difference in the memory unit of C. By way of non-limiting example, in one embodiment, for the lower page. (5) can be about 〇3 volts, △Vpgm2 can be about 〇·4 volts on the upper page or in the full sequence. . 12 is a timing diagram of processing and writing logical page data of a non-volatile memory system, in which the stylization for the first page of data is started, and then when the second page of data is received, it is paused or interrupted to start for all pages. The full 125212.doc •28· 200837760 sequence stylized. The controller receives the data from the host device, and the controller forwards the data and the address information to the row control circuit, and the row control circuit is placed in the data register. In Fig. 12, 'the next page data is received first for the same memory unit controller', and then an upper page data is received. The appropriate scratchpad is loaded and, in response to a program command from the controller, the =time ti' state machine begins to program the lower page data into the set of memory cells.

C After the time ti, the upper (four) material for the same group of memory cells is received from the host. At time t2, the (4) device completes the manned data into the register at the array. After determining that the new data is used for the upper page information of the same memory unit, the controller can interrupt the stylization operation. In the particular embodiment illustrated in Figure 12, the system can interrupt, pause, or otherwise stop the lower page stylization process to switch to full sequence operation. In one embodiment, the controller stops the lower page stylization operation only if the lower page stylization operation has not completed the county sufficient = to ensure that it is allowed to end. The controller can issue a new program command for full sequence stylization after providing the upper page data to the data register in the column control circuit. 'Complete=: Verify operation to lock the memory unit that has reached its target state = continue to use the full sequence of stylization to continue the stylization of the two pages of data. According to a specific embodiment, 'in a specific embodiment as shown in Fig. 12', when the full sequence is programmed after time t2, a different increment value is used for the program voltage signal. Figure 12 illustrates a program voltage signal in accordance with an embodiment of the invention. Staging the memory cell from the erased state to state A begins at a time 当 when a first erase voltage pulse is applied. Before the completion of the 125212.doc -29-200837760 private state to state A, the upper page data is received from the host at time t2 'the controller issues the data to the row control circuit, and the row control circuit stores the data in In the scratchpad. After verifying, locking, and issuing a new program command, the full sequence stylization begins with the first pulse after time t2. With the full sequence command issued, after the lower page is programmed, the next program voltage pulse is incremented by =vPgm2 higher than the last program voltage pulse. The Δνρ^2 values and values may vary with the particular embodiment and various embodiments. In the specific embodiment, 丨 and ΔVpgw are selected as described with reference to Figure U. 14 is a flow chart of a method of staging non-volatile memory in accordance with an embodiment. A variable increment value is used depending on the state being programmed and/or the stylized operation and data type. At step 5, 2, a "data load" command is issued by controller 318 and input to command circuit 314 to allow data to be entered into data input/output buffer η]. The input feed is recognized as a command and is latched by state machine 316 via a command latch signal (not shown) that is input to command circuit Η#. At step 504, the address data of the specified page address is input from the controller or host to the column controller or decoder 3G6. The input material is recognized as a page address and is latched via state machine 316 (affected by the address latch signal input to command circuit 314). At the step of writing, a page of program data of the page of the address is input to the data input/output buffer 312 for programization. For example, in a specific embodiment, a positive byte data can be entered. The poor material is latched in the appropriate register for the selected bit line. In one embodiment, the data is also latched in the selection for verification operation. 125212.doc -30- 200837760

The second register of the bit line. In one embodiment, the data corresponds to a logical page of information stored by a set of memory cells storing additional logical pages. The set of memory cells can be set to store a plurality of logical pages in a body page defined by the set of memory cells. A physical page can include a set of memory that has all the poor materials stored in the early days, such as one column at a time. A physical page can also be programmed to the maximum amount of data in the set of memory cells. At step 508, a "program" command is issued by controller 318 and input to data input 7 output buffer 312. The command is latched by state machine 3 16 via a command latch signal input to command circuit 314. By the trigger of the "program" command, the stepping pulse applied to the appropriate word line as shown in FIG. 6 is controlled by the state machine 3丨6 to program the data latched in the step to the selected memory unit. in. At step 51, the programmed pulse voltage level Vpgm applied to the selected word line is initialized to a start pulse (eg, 12 volts), and a program counter maintained by state machine 316 is initialized to zero or another A value. At step 512, a first pulse is applied to the selected word line. If the logic is stored in a particular data latch, 〇" indicates that the corresponding memory cell should be programmed, then the corresponding bit line is grounded. On the other hand, if stored in a particular latch The logic "丨", which means that the corresponding memory list should maintain its existing data state, the corresponding bit line is connected to VDD to prohibit stylization.隹Step 514, heart, 别木1踯到—The target threshold voltage of the selected memory unit has reached the appropriate level, then the data stored in the corresponding data latch is changed to logic "丨, 2 If the target threshold voltage is not reached to the appropriate level, then the relative value is not changed: 125212.doc -31 - 200837760

: Material stored in the material latch. In this mode, the logic has been stored in its own corresponding data latch, and the bit line of i π does not need to be programmed. When all data latches are storing logic, the state machine knows that all selected memory cells have been programmed. At step 516, it is checked if there are latches H are storing logic "Γ, if so, Because the (4) selection fe body has been programmed and verified to be programmed to its target state, the stylization process is completed and successful. In the step, report 'pass' (PASS) status. In step 516, if it is determined that not all of the data latches are storing the logical "1", the stylized processing continues. In step 52, the (four) pc is checked by comparing the one-way limit value. The program limit value for the item instance is 20, however, other values may be used in various embodiments. If the program counter PC is not less than 20, it is determined in step 526 whether the number of bits that have not been successfully programmed is equal to or less than the number of pre-shirts. If the number of unprogrammed bits is equal to or less than a predetermined number, the stylized handler is flagged as passed, and a pass status is reported in step 528. Error corrections can be used to correct unsuccessfully programmed bits during the read process. However, if the number of unsuccessfully stylized bits is greater than a predetermined number, the stylized handler is flagged as failed with a flag, and a failure status is reported in step 530. If the type 'counter PC is less than 20, increase the Vpgm level by the step size.

522 increments the program counter pC and at step 512, applies the next Vpgm pulse. At step 522, the processing loops back to steps 502' through 510'. When any of the operations shown in FIG. 14 are performed, the 125212.doc -32 - 200837760 system can be connected (four) to - or multiple (four) Additional information. (d) η at any time from the host's data, and the release-extra data is carried in step 502'). The step tour can occur in addition to the information shown in Figure 14 and the position and time of the gossip. The data from the host can be received, and in the step, for example, the execution-data manned command is executed to load the address in the step of the column controller in step (4) 6, and the (four) stylized transition is available = store μ. In the specific embodiment, the controller waits until the state machine or row control circuit issues an available signal that it can receive more data in the scratchpad. At step 508, the controller and state machine can process the newly received bedding in a variety of ways. In one embodiment, the controller stops the current lower page stylization operation. This is drawn by the arrow from the square to the box 5〇8. The controller then issues a new program command that instructs the state machine to use the full sequence to program (simultaneously) program the lower page of the lower page. At step 510'' the state machine can set Δνρ^ν_ such that a larger increment value is used when the two pages are programmed in full sequence. Next, the program operation continues (as described above), but using a larger increment value in a particular embodiment shown in step 51 〇' resets Vpgm before starting the full sequence and the PC counter is reset to 〇. ν(4)&丨2 can be equal to, less than, or greater than Vinitiall. However, it is not reset in all of the specific embodiments. For example, 'if the upper page arrives relatively quickly and only a few private voltage pulses have been applied' then Vpgm can start at its last peak, start at a value greater than its last peak (increment in other values) or start at less than Its final peak value. 125212.doc -33- 200837760 Figure 15 depicts a more detailed description of the step 508 of Figure 牛牛丨4, setting the program life

flow chart. Figure 15 is an exemplary embodiment in which - for a stylized use - a smaller divergence value, and for an upper tiling or column stylization - a larger increment value. In the embodiment of FIG. 15, before issuing the program command to the row control circuit, in step 602, the controller compares the newly received (four) address data with the data currently being programmed by the lower page of the active money unit. . At step 604, if the controller finds a match (which means that the data being newly received by the same memory unit is being stylized), then the method proceeds to step 608. In a specific embodiment, the state machine and/or the row control circuit implements step 6()4. If the address does not match, then the lower page stylization continues, for example, by applying the next program voltage pulse at step 512 of FIG. In addition to step 512, the method of FIG. 14 can also continue after step 6-6 of FIG. If the address data does not match, then at step 6〇8' the controller determines if the lower page stylization is complete. When a predetermined number of program voltage pulses have been applied, when all memory cells to be programmed into state 已 have been successfully programmed to state A, or when a predetermined number of memory cells have been successfully programmed to In state A, the lower page is stylized. If below. After the page is programmed, the upper page data is programmed into the set of memory cells in step 6 i, where the controller issues the upper page command. At step 620, the upper page stylization continues, as shown in step 510' of Figure 14, where the program voltage signal is initialized to (1) and set to AVp^2. When stylizing the upper page of the memory cell, use the second increment value to increase the size of the subsequent stylized pulse. 125212.doc -34- 200837760 Proximity:: The sorrow A reading unit will be attributed to the subsequent stylization Chuan, ^ = pure width threshold voltage distribution, so use a smaller ΔΥρ_ when using a larger page on the step page, and for the upper step 2 = page is not completed (or not connected w white half stop lower page stylized In Figure 14, the controller can be issued by the controller or the state machine - the forced row control circuit stops the command of the lower page data. In step 612, the lower page is programmed: after step 614 The controller sets the full sequence program data command. In the embodiment, the command is input to the buffer 312 via the command latch signal input to the command circuit and is latched by the state machine. The program command triggers the state machine to programmatically select the selected memory. In step 616, the controller can cause the row control circuit to perform a verify operation on the memory unit that has been successfully programmed during the programming of the next page. Has Any memory unit whose target level is reached, the controller locks its memory unit to prevent further stylization. After locking the programmed memory unit, the method proceeds to step 62, which corresponds to the map. Step 5 1 〇 ', in this step the incremental value can be adjusted. In a specific embodiment, greater than Δνρ Εΐ η 1. After stylization, in order to reduce the state Α distribution width, for the lower page stylized or for the stylized minimum Stylize the state of the entity, using a smaller Vpgmi. Because the memory cells in state A have an extra capacitive coupling effect, use a smaller AVpgm value to avoid over-stylization and/or stylize dry 125212.doc -35 - 200837760. In a specific embodiment, step 510 further includes resetting, the initial value of @. For example, if the lower part of the 葙彳 葙彳 ^ ^ 丨 私 私 私 私 私 私 私 私 私The signal is programmed to the upper page or, |Becker is stylized by the king sequence. The value of Vpgm can be reset to a lower value. Too s ^ weight-like value in a specific implementation Vpgm is reset to the same starting value as when starting the lower page stylization. In the specific embodiment, v- is reset to its current value but not to the original value for the lower page stylization. The same low value. In another embodiment, when the full sequence or upper page stylization is started after the completion of the lower page stylization, the last value used when the lower page is programmed is started, with a third increment value. AVp^3 increases or decreases the program voltage signal. In one embodiment, the program voltage signal Vpgm is not reset until the upper page or full sequence is programmed. In a specific embodiment, ¥1)^2 increases the final voltage pulse for the lower page stylization. In another embodiment, for the first upper page or full sequence of pulses, the final voltage pulse for lower page programming is increased by AVpgm3. After the first additional pulse, as described, the value is increased by AVpgm2. AVpgm3 may be greater than AVpgm2 to provide a more stable transition between the two stylized rates resulting from two different step sizes. Step 510' may also include resetting the program counter pc. For example, the maximum number of pulses can be independently built for the lower and upper pages or the full sequence. The counter PC can be reset to 〇 or another value when stylized between the lower page and the upper page or between the lower page and the full sequence stylization. In another embodiment, the counter PC is not reset and the total maximum number of repeated jobs or pulses are used for the overall stylized operation. Roots 125212.doc -36- 200837760 Other variations can be practiced in accordance with specific embodiments. In the variation of the technique described in Figure 15, the increment value for the program voltage pulse is not increased until the programmed minimum programmed state is completed, even after transitioning to full sequence stylization. At step 608, if the controller determines that the lower page is stylized, then the operation proceeds to step 6, as described above, but if the lower page is not yet programmed, the controller stops the lower page stylization process, and Switch to full sequence stylization as shown in steps 612 through 618. However, until the stylization of the lowest programmed state (eg, sadness A) is completed, the program voltage increment value is changed to ΔVpgm2, and all or predetermined memory cells are verified as arrived state A, the program voltage The increment value is more variable than AVpgm2. In a specific embodiment, the program voltage pulse is determined and used to determine the date π is switched to ΔΥρ"2. For example, after switching to full sequence programming, the program voltage increment value can be changed to ΔVpgW after a predetermined number of program voltage pulses have been applied since the initial page programming process. In a specific embodiment, in step (10), the determination of the completion of the lower page stylization can be based on a predetermined number of stylized cycle repetitions (ie, 'predetermine the number of programs, the number of the device's pulse balances, regardless of the memory. It is actually programmed to the appropriate state (for example, state Α). When it is determined in advance that the unit has reached the appropriate state, it can also be determined that the lower page of the program element is 'this can be determined before the entire set of memory cells required to verify that the book page is properly programmed has arrived at the appropriate state. In the case of the case, after resetting the program signal and using the increment value, according to the lower page 125212.doc •37-200837760 material 'some memory units may require additional stylization. This may be handled during the upper page stylization of step 610 by not locking those memory cells that have not been verified as having arrived at state A to be programmed to state a and continuing during the upper page stylization Verification is performed at the status A level. In a particular embodiment where the § 己 体 早 早 can still be programmed to the lowest programmed state, in step 610 to the upper page stylization, until stylized for the lowest programmed state Only when ΔVpgm is changed to ΔVpgw. △Vpgml will continue to be used during the stylization of the upper page until the stylization for the lowest programmed state is verified. For example, § 'After a predetermined number of memory cells to be programmed into state A have arrived at state A, AVpgm can be changed from AVpgml to AVpgm2. In another variation of FIG. 15, if it is determined in step 608 that the lower page stylization is not completed, the controller does not immediately stop the lower page stylization process and convert to full sequence stylization after receiving the upper page data. . Instead, the controller waits until it determines that the lower page is programmed. Figure 16 is a flow chart showing a method of changing the increment value only after receiving the extra data if the stylization of the lower page is completed. This technique toggles the increment value from the next page stylization to the upper page stylization or from the lower page stylization to the full sequence stylization. At step 704, the lower page information is received. The address data is set in step 706, the program data is entered in step 708, and the controller 318 issues a program command in step 710. At step 712, Vpgm is set to its initial value, the program counter is initialized, and 125212.doc -38 - 200837760 Δvpgm is set to ΔΥμμ. At step 714, the lower page material is programmed, for example, as shown in Figure 14 (steps 512 through 530). When the lower page is programmed, the upper page data is received at step 71 6. The address data is set at step 718 and the program data is entered at step 720. Prior to issuing an update program command, in step 722, the controller determines if the lower page stylization is complete. As described above with respect to step 608 of FIG. 15, the various states can be used to determine whether the stylization is complete. It can be determined whether or not the program is to be programmed (all or a predetermined number of memory cells of state A have arrived at state A. In other cases, step 722 can include determining if a predetermined number of pulses have been applied, and if so, determining the lower portion The page is stylized. If the lower page is not programmed, then in step 724, the controller continues the lower page stylization and continues this loop to wait for the lower page to be programmed to complete the TANASY Sigma page. Proceeding to step 726, the controller issues an update program command. In step 8, the controller can reset Vpgm to an initial value of νίη_ΐ2, reset the increment value, and I and heavy: the private counter PC. After the signals (which can be implemented by a digital-to-digital converter that resets a negative Bayesian voltage signal), in step 730, the stylization begins with the new command. In a specific embodiment, The program command set at step 726 is set for upper page stylization. At step 722, the controller can wait until the lower page is stylized until stylized for state A. Successful verification. In this case, the lower page stylized material has been programmed, and only the stylization for the upper page needs to be performed at step 730. In a variation of this technique, the upper page program command can be issued at step 726. And once the lower 125212.doc -39-200837760 page is programmed, the stylization of the upper page is continued immediately in step 730. However, the ΔVpgm is reset in step 728 until the stylization for the lowest programmed state is verified as complete. The e-sense body that has been programmed to state A has been programmed to be sorrowful A will be locked to prevent further stylization, and to be stylized into state A's memory that has not yet reached state A. The unit will suffer further programming and verification. When the state A stylization is verified to be completed, the program voltage increment value can be changed to AVpgm2. In a specific embodiment, when some memory cells can still need to rise to state A. At step 722, it is determined that the lower page is programmed (eg, by determining the number of pulses in advance), and in step 726, the stylization can be converted to full Sequence stylization. For full sequence stylization, verification can be performed before the first program voltage is applied. During full sequence stylization, any memory cells that have reached their final target state during the next page stylization can be locked to block Further stylization. Any memory unit that has not yet arrived in state A to be programmed to state a on the date of completion of the stylization of the lower page will be subject to additional stylization during full sequence stylization. Full sequence stylization is available The status A level performs verification so that during the full sequence of stylization, the target A state memory unit is not allowed to arrive during the lower page stylization period can be privateized to state A. In a specific embodiment, the lower page When the stylization is complete, the transition to full sequence stylization is performed in step 726, but the program voltage increment value is changed to AVpgm2 until the lowest programmed state is verified as complete (if not already verified). A specific embodiment (as shown in Figure 16) that transitions to full sequence stylization (or upper page stylization) and larger increment values after completion of the lower page stylization may be 125212.doc 200837760 provides benefits in a particular implementation . For example, some memory devices will use a digital to analog converter to generate a private voltage signal for a program of different sizes. In a specific embodiment, the digital to analog converter can form part of a column control circuit. Some converters rely on 'a digital input value to generate an analog voltage pulse with the necessary peak value. In some cases, an improved program dust rise value in the middle of the program voltage pulse can present a problem. Changing the increment size can not produce a down-pulse with a peak of the previous pulse plus the new increment value. Instead, some converters can generate the next pulse, as if the value of θ has been new since the program was programmed. According to this, in the case of using such a converter, 纟, 4 will wait for the lower page to be programmed. When the lower page is programmed 70%, the new increment value and the initial program (four) pulse can also be used. Resizing the digital to analog converter. This will avoid any inconsistency or large jump in the program voltage pulse value. Although it has been converted from the lower page to the full sequence or from the next page to the upper page. The specific embodiment is described, but the specific embodiment can be applied to a single type of stylized operation. For example, in a practical example, when the minimum sequence is programmed in the full sequence stylization, The car has a small increment value of Δνρ(10). When the lowest programmed state (for example, state A) is programmed, it can be reset to Vpgm to a larger increment value of ΔvPgm2. In this mode, the program is compensated by a smaller one. The increased capacitance splicing effect encountered by the memory cells in state A. Although no changes have been made in the stylized method, the incremental values are still adjusted to make the lowest level stylized state more accurate. 125212.doc 200837760 In one embodiment, statistics are used to predict when the lowest programmed state will be stylized. After the predicted lower state stylization is completed, the program voltage increment can be changed. For example, it can be 8 pulses at 90. After % time, it is determined that the lower state completes the stylization. The stylized algorithm can use a smaller AVpgmi for the first eight program voltage pulses, and then switch to the larger increment value Δνρρ2 for the remaining pulses. In this way, no • any A circuit that evaluates whether the lower page is stylized and actually responds (and changes the program voltage increment value. Instead, the increment value is automatically changed after a specified or predetermined number of pulses or a program voltage signal is applied.) Stylize with the lowest programmed state before switching the increment value as mentioned above Any technique is used together. For example, the number of predetermined pulses applied before switching to as described above may be based on a statistical evaluation of when the staging memory unit to state will be completed. The technique of changing the increment value when transitioning to the upper page stylization or full sequence stylization or when stylized for the first stylized state can be combined with other stylization techniques. In one embodiment, 'incorporating changes The increment value takes advantage of the so-called coarse/fine program--. • In coarse/fine stylization, the rough stylization phase involves attempting to make the 2-limit voltage rise in a faster manner and relatively less noticeable. Vertical knives. The fine stylization phase attempts to bring the threshold voltage to the target threshold voltage at a slower side, thus achieving a tighter threshold voltage knives. For an example of a rough/fine stylized methodology, see U.S. Patent No. 125,212.doc-42-200837760, Patent No. 6,643,188, the entire disclosure of which is hereby incorporated by reference herein in An example of a methodology is more detailed in Section II. Figure 7A and Figure 8a illustrate the programmed pulse vpgm applied to the control gate. 17B and 18B illustrate the bit line voltage for the early memory of the memory being programmed. The graph PC and Fig. 18C show the threshold voltage of the 忑L and the body το which are being programmed. This example describes the use of two verification levels (as shown in VvA1 and VvA in the figure) to program the memory unit to state A. The most, and the private level VvA. When the threshold voltage of the memory unit When the VvA has been reached, the voltage is applied to the bit line corresponding to the memory unit by the force-carrying port to prohibit the step-by-step programming of the memory unit. For example, the bit line voltage can be Rise to Vinhibit (see Figure 17B and Figure 18B). But =, when the memory cell has reached a threshold voltage close to (but less than) the target value VvA, by applying a specific bias voltage (typically about 0.3 volts) Up to 0.8 volts to the bit line, causing the threshold of the memory cell to shift during the subsequent stylized pulse. Because the threshold voltage shift rate is reduced during the next few stylized pulses, the final The threshold voltage distribution is narrow. To implement this method, a second verification level is used, which is lower than the Vva level. This second verification level is depicted as VvAi in Figures 17 and 18. When the memory unit (4) When the voltage limit is greater than VvA1 but still less than Vva, by applying One bit line bias voltage Vs (Fig. 18B), the threshold voltage offset of the memory cell will decrease for subsequent stylized pulses. Note that in this case, two verify operations are required for each state. Apply each state of the coarse/fine stylized methodology to the corresponding final verification level (eg, U performs a 125212.doc -43 · 200837760 verification operation, and for each state, the corresponding second verification bit A verification operation (eg, Vva!) is performed. This increases the total time required to program the memory unit. However, a larger step size can be used to speed up the processing. Figure 17Α, 17Β, and 17C In a stylized pulse, its threshold voltage moves through the behavior of the VvA and VvA memory cells. For example, the threshold voltage is shown in Figure 17C as being between 1 and ¥. Previously, the memory cell was in a rough phase. After "the memory cell is in the disable mode. Figures 18A, 18B and 18C show the memory cell entering the coarse and fine stylization phase. Voltage between the time "and" crossed Vval. Prior H, system memory cell in the coarse phase. "Behind,

Between t3 and t4, the threshold voltage of the memory unit crosses the VM. Therefore, by

Step by step. Nhibit ‘ prohibits the memory unit from entering

In a specific embodiment, it can be refined. However, the change in the increment value can be combined with the increment value to use the rough / 125212.doc -44 - 200837760 fine, 'field. For example, by using a single final verification level, the # page can be used to determine the state A. The full-sequence (four) formula is performed after the process has been reached. For the upper embodiment, the heart = dynamic coarse/fine stylization. During a stylization of a program, a sequence, or an upper page, for each centroid, use a rough and fine verification bit for the (four) ~ soil + long" 匕 specific examples, only ... use coarse and fine For example, the embodiment of the present invention may have been proposed in the foregoing, and the foregoing description has been made for the purpose of illustration and description only for the form of SC' or only for the shape of red. The invention may be modified or modified in accordance with the foregoing teachings. The specific example A is chosen to best explain the principles and practical applications of the present invention. The present invention is best utilized in various embodiments, and various modifications are applicable to the specific materials considered. The invention is intended to be defined by the scope of the accompanying claims. 9 [Simple Description] Figure 1 Figure 2 is a circuit diagram of three NAND strings. Figure 4 is a block diagram of a specific embodiment of a non-volatile memory system. Memory Exemplary Organization of Body Arrays Figure 6 illustrates an exemplary set of program voltage signals. Figure 7 illustrates an exemplary set of threshold voltage distributions and a full sequence of stylized sections 125212.doc -45-200837760. A set of exemplary threshold & pressure distribution and two-pass processing procedures are shown. Figure 9 is depicted for use in a

The appearance of capacitive charge-coupled effects in non-dry non-volatile memory systems. μ Ά T Figure 1 〇 shows the timing diagram for stylizing the upper page of the lower page during the interval between the „ κ and # 子 intervals. Only the Bayer and Figure 11 are based on a specific caution. For example, the program voltage signal can be used for the stylized lower page data and the upper page data as shown in FIG. 10, and FIG. 12 shows the program for the lower part 1 beibe and then when the upper page data is received. The timing chart of the lower page and the upper page data is shown in Fig. 13. Fig. 13 shows the program voltage signal according to the specific embodiment, and the basin can be used for the stylized lower page data and the upper page data as shown in FIG. A flow chart of a method for stylizing non-volatile memory according to the specific embodiment is shown in Figure 15. Figure 15 is a diagram showing additional data for receiving a memory unit for a group that is currently being stylized. Time setting - a flow chart of the method of the program command. ~ , Figure 16 shows the method for changing the page layout to the upper page when using the larger incremental value for the full sequence programming when the lower page is programmed. Flow chart. Figure and 17C A specific embodiment of the programming program, the stylized processing program is part of a rough/fine stylization. Figure 1, (10) and a specific embodiment of the stylized processing program, the stylized processing program is Rough/fine stylized part. 125212.doc -46- 200837760 [Main component symbol description] 100, 102, 104, 106 Transistor 100CG, 102CG, control gate 104CG, 106CG 100FG, 102FG, floating gate 104FG, 106FG 120 first selection gate 120CG control gate 122 second selection gate 122CG control gate 126 bit line 128 source line 202, 204, 206 NAND string 220, 230, 240, 250 select transistor (select gate) 222, 224, 226, 228, memory unit 242, 244, 246, 248, 252 302 The threshold voltage level of the memory unit is increased to state A (Fig. 8) 304 The threshold voltage is increased to the state B range (Fig. 8 306 The threshold voltage is increased to the range of state C (Fig. 8) 302 Memory cell array (Fig. 4) 125212.doc -47- 200837760 304 row control circuit (Fig. 4) 306 column control circuit (column controller or solution) (Fig. 4) 308 P well control circuit 310 common source line control circuit 312 data input/output buffer * 314 command circuit 315 (control circuit 316 state machine 318 controller 330, 332 stylized pulse 334 first verify pulse 336 brother one verification pulse 338 third verification pulse BLe even bit line / BLo \ ^ odd bit line PC program counter SGD selection line (select gate dipole line) • SGS selection line (select gate source line) WLO , WL1, WL2, word line WL3... A, B, C Price limit voltage distribution (stylized state) E ^ Limit voltage distribution (erased state) V inhibit Prohibited voltage code 125212.doc 48- 200837760

Vinitiall, Vinitiai2 program voltage signal

Vpgm program voltage

VrA5 VrB, VrC read reference voltage Vva, Vvb, Vvc verify reference voltage VvA1, Vva verify level (Figure 17, Figure 18) V v Pgm Stylized pulse voltage level ^Vpgmi5 ^Vpgm2, △Vpgm3 program voltage increment value 125212 .doc 49-

Claims (1)

200837760 X. Patent application scope: 1 · A non-volatile memory system, comprising: a set of multi-state non-volatile storage elements; a management circuit, and the plurality of non-volatile storage elements ^ management circuit are programmed in the following manner The plurality of non-needle pieces of the non-volatile storage element receive a stylized data to the group of multi-state requests, Applying a predetermined number of program voltage pulses to the set of multi-state non-volatile storage elements 'to program the material to the non-volatile storage items'. The application includes increasing the programs by a -first increment value One of each of the voltage pulses, up to the predetermined number, applying one or more additional program voltage pulses to the set of multi-state non-volatile storage elements to complete the stylization of the data, the application of one or The plurality of additional program voltage pulses includes increasing a size of each of the one or more additional program voltage pulses by a second increment value. 2. The non-volatile memory system of claim 1, wherein the applying a predetermined number of program voltage pulses comprises causing the program to be programmed to a first programmed state, a second programmed state, and a a threshold voltage rise of the third programmed state non-volatile storage element; the applying one or more additional program voltage pulses comprising causing to be programmed to the second programmed state and the third programmed A threshold voltage of the non-volatile storage element of the state rises. 125. The method of claim 1, wherein the second incremental value is greater than the first incremental value. 4. The non-volatile memory system of claim 1, wherein: the management circuit comprises a digital to analog converter, the digital to analog converter providing a program voltage signal, the program voltage signal including the predetermined number of programs a voltage pulse and the one or more additional program voltage pulses; and the logic circuit resets the program voltage signal prior to applying the one or more additional erase voltage pulses. 5. The non-volatile memory system of claim 4, wherein: the management circuit resets by decreasing a peak value of the program voltage signal to an initial value before applying the one or more additional erase voltage pulses The program voltage signal. 6. The non-volatile memory system of claim 1, wherein: applying the one or more additional program voltage pulses comprises applying one of the first additional program voltage pulses of the additional program voltage pulses; applying the predetermined number of The program voltage pulse includes applying a last program voltage pulse of the predetermined number of program voltage pulses; and the first additional program voltage pulse has a peak value substantially equal to one of the peak value of the last program voltage pulse and the second The sum of one of the increment values. 7. The non-volatile memory system of claim 1, wherein: applying the one or more additional program voltage pulses comprises applying one of the first additional program voltage pulses of the additional program voltage pulses; 125212.doc 200837760,, Adding, the county determines the number of programmable electrical impulses including applying one of the pre-, a few of the private voltage pulses of the last program voltage pulse; and the additional 轾 voltage pulse has a peak value, the repair value is substantially equal to the last The sum of the program's pulse-peak and - third increment values. 8_ The non-volatile memory system of claim 7, wherein the third incremental value is greater than the second incremental value. 9. The non-volatile memory system of claim 7, wherein: the set of multi-state non-volatile storage elements is a set of multi-state nand type flash memory devices. 10. A method of staging a non-volatile storage device, comprising: receiving a request for a data to a set of multi-state non-volatile storage elements; applying a predetermined number of programmed voltage pulses to a set of non-volatile a storage element for staging the data to the non-volatile storage elements, the applying comprising increasing a size of each of the program voltage pulses by a first increment value until the predetermined amount is reached; One or more additional program voltage pulses are applied to the set of non-volatile storage elements to complete programming of the data, the applying one or more additional program voltage pulses comprising increasing the one or more by a second incremental value One of the extra program voltage pulses of each size. 11. The method of claim 10, wherein the applying a predetermined number of program voltage pulses comprises causing the program to be programmed to a first programmed state, a second programmed state, and a 125212.doc 200837760 A threshold voltage of the non-volatile storage element in a programmed state is increased; the addition or the plurality of additional program voltage pulses includes a program to be programmed to the second programmed state and the third programmed state A threshold voltage of the non-volatile storage element rises; 12. The method of claim 10, wherein the second incremental value is greater than the first incremental value. 13) The method of claim 1 wherein: the predetermined number of program voltage pulses and the one or more additional program voltage pulses are provided by a common program voltage signal; and the method further comprises applying The program voltage signal is reset before the one or more additional erase voltage pulses. 14. The method of claim 13 wherein resetting the program voltage signal comprises decreasing a peak value of the program voltage signal to an initial value prior to applying the one or more additional erase voltage pulses. The method of claim 1, wherein: applying an additional voltage pulse comprises applying a first additional program voltage pulse of the additional program voltage pulses; applying the predetermined number of program voltage pulses Including applying a last program voltage pulse of the predetermined number of program voltage pulses; and the first additional program voltage pulse has a peak value substantially equal to one of a peak value of the last program voltage pulse and the second increment value A sum. The method of claim 1, wherein applying the one or more additional program voltage pulses comprises applying one of the first additional program voltage pulses of the additional program voltage pulses; applying the predetermined amount The program voltage pulse includes applying a last program voltage pulse of the predetermined number of program voltage pulses; and the first additional program voltage pulse has a peak value substantially equal to one of the last program voltage pulses and one peak The sum of one of the third increment values. 17. The method of claim 10, wherein the third incremental value is greater than the second incremental value. 1 8 The method of claim 1, wherein the multi-state non-volatile storage element is a multi-state NAND type flash memory device. 125212.doc