WO2008036484A3 - Nonvolatile memory with reduced coupling between floating gates - Google Patents

Nonvolatile memory with reduced coupling between floating gates Download PDF

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Publication number
WO2008036484A3
WO2008036484A3 PCT/US2007/076163 US2007076163W WO2008036484A3 WO 2008036484 A3 WO2008036484 A3 WO 2008036484A3 US 2007076163 W US2007076163 W US 2007076163W WO 2008036484 A3 WO2008036484 A3 WO 2008036484A3
Authority
WO
WIPO (PCT)
Prior art keywords
floating gates
nonvolatile memory
reduced coupling
inverted
floating
Prior art date
Application number
PCT/US2007/076163
Other languages
French (fr)
Other versions
WO2008036484A2 (en
Inventor
Henry Chien
George Matamis
Tuan Pham
Masaaki Higashitani
Hidetaka Horiuchi
Jeffrey W Lutze
Nima Mokhlesi
Yupin Kawing Fong
Original Assignee
Sandisk Corp
Henry Chien
George Matamis
Tuan Pham
Masaaki Higashitani
Hidetaka Horiuchi
Jeffrey W Lutze
Nima Mokhlesi
Yupin Kawing Fong
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/534,139 external-priority patent/US20080074920A1/en
Priority claimed from US11/534,135 external-priority patent/US7615445B2/en
Application filed by Sandisk Corp, Henry Chien, George Matamis, Tuan Pham, Masaaki Higashitani, Hidetaka Horiuchi, Jeffrey W Lutze, Nima Mokhlesi, Yupin Kawing Fong filed Critical Sandisk Corp
Publication of WO2008036484A2 publication Critical patent/WO2008036484A2/en
Publication of WO2008036484A3 publication Critical patent/WO2008036484A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures. An array having inverted-T shaped floating gates may be formed in a self-aligned manner.
PCT/US2007/076163 2006-09-21 2007-08-17 Nonvolatile memory with reduced coupling between floating gates WO2008036484A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/534,139 2006-09-21
US11/534,135 2006-09-21
US11/534,139 US20080074920A1 (en) 2006-09-21 2006-09-21 Nonvolatile Memory with Reduced Coupling Between Floating Gates
US11/534,135 US7615445B2 (en) 2006-09-21 2006-09-21 Methods of reducing coupling between floating gates in nonvolatile memory

Publications (2)

Publication Number Publication Date
WO2008036484A2 WO2008036484A2 (en) 2008-03-27
WO2008036484A3 true WO2008036484A3 (en) 2008-08-07

Family

ID=39166676

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/076163 WO2008036484A2 (en) 2006-09-21 2007-08-17 Nonvolatile memory with reduced coupling between floating gates

Country Status (2)

Country Link
TW (1) TWI359499B (en)
WO (1) WO2008036484A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8429574B2 (en) * 2011-04-14 2013-04-23 Cadence Design Systems, Inc. Dual-pattern coloring technique for mask design

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19617632A1 (en) * 1995-12-26 1997-07-03 Lg Semicon Co Ltd Non-volatile memory cell device, e.g. ROM cell
WO2005001922A1 (en) * 2003-06-20 2005-01-06 Sandisk Corporation Floating gate structures with vertical projections
US20050087795A1 (en) * 2003-09-22 2005-04-28 Makoto Sakuma Nonvolatile semiconductor memory device
US20050199939A1 (en) * 2004-03-12 2005-09-15 Lutze Jeffrey W. Self aligned non-volatile memory cells and processes for fabrication
US20050212034A1 (en) * 2004-03-24 2005-09-29 Renesas Technology Corp. Nonvolatile semiconductor memory device and manufacturing method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19617632A1 (en) * 1995-12-26 1997-07-03 Lg Semicon Co Ltd Non-volatile memory cell device, e.g. ROM cell
WO2005001922A1 (en) * 2003-06-20 2005-01-06 Sandisk Corporation Floating gate structures with vertical projections
US20050087795A1 (en) * 2003-09-22 2005-04-28 Makoto Sakuma Nonvolatile semiconductor memory device
US20050199939A1 (en) * 2004-03-12 2005-09-15 Lutze Jeffrey W. Self aligned non-volatile memory cells and processes for fabrication
US20050212034A1 (en) * 2004-03-24 2005-09-29 Renesas Technology Corp. Nonvolatile semiconductor memory device and manufacturing method thereof

Also Published As

Publication number Publication date
WO2008036484A2 (en) 2008-03-27
TWI359499B (en) 2012-03-01
TW200820428A (en) 2008-05-01

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