TW200820428A - Nonvolatile memory with reduced coupling between floating gates - Google Patents

Abstract

A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures. An array having inverted-T shaped floating gates may be formed in a self-aligned manner.

Description

200820428 IX. Description of the Invention: [Technical Field of the Invention] The large system of the present invention relates to a non-volatile flash memory system, and, in other words, to the structure and memory of a memory cell, 疋T~< I竿Columns, and the specialties are about the process of forming them. All of the patent applications and other documents cited in this application are hereby incorporated by reference in their entirety. [Prior Art] ° f

There are many commercially successful non-volatile memory products (especially in the form of miniaturized cards) that use flash lightning to erase programmable read-only memory (Electrically ErasaMe _

An array of Programmable Read Only Memory (EEPROM) units. In one type of architecture (NAND array), a series of strings having more than two (such as 16 or 32) memory cells are connected to one or more select transistors between individual bit lines and a reference potential. Together to form a unit of the line. The word line extends across a large number of cells in these rows. Reading individual cells in a row and verifying the individual cells during stylization by causing the remaining cells in the string to be driven, such that current flowing through the string is stored in the addressing unit The level of charge depends on the level of charge. An example of a NAND architecture array as part of a memory system and its operation can be found in U.S. Patent No. 6,046,935. In another type of array having a "split channel" between the source and drain diffusion regions, the floating gate of the cell is located on one of the channels and the word, line (also known as the control gate) is located elsewhere. Channel section and floating gate. This effectively forms a cell having two series transistors, a transistor 123977.doc 200820428 (memory transistor) having a charge on the floating gate and a voltage on the word line that controls the amount of current that can flow through a portion of its channel. The combination of the other (selective transistor) has a word line that acts as its gate alone. The word line extends over one of the floating gates. Examples of such units are provided in the memory system in U.S. Patent Nos. 5,070,032, 5,095,344, 5,315,541, 5,343, 〇63, 5,661, 〇53, and 6,281,075. Use and its manufacturing methods. ^ Modification of this split-channel flash EEPROM cell adds a pilot gate that provides a strong capacitive coupling to the floating gate in the case of a T-direct control channel. Each of the lead gates of the array extends perpendicular to the word line and on one of the floating gates. The result is that the word line is free from reading or stylizing a selected unit. These two functions are (丨) acting as one of the gates of the selection transistor, thus requiring an appropriate voltage to turn the selection transistor on and off, and (2) an electric field between the word line and the floating gate. (Capacitive) Coupling drives the voltage of the floating gate to a desired level. It is often difficult to perform these functions using a single-voltage in a better way. In the case of adding a boot gate, the word line only needs to perform the function (1), and the added guidance is performed on the stomach b (2). For source-side injection programming, by driving only the select gate to approximately its threshold voltage (eg, near 〇·5ν), the pilot gate voltage will gradually increase from a stylized clock to the next clock (at Effective stylization is performed by performing verification and locking operations in the middle of the stylized clock. The use of a pilot gate in a flash EEPROM array is described in, for example, U.S. Patent Nos. 5,313,421 and 6,222,762. In any of the types of memory cell arrays described above, the cell float 123977.doc 200820428:: is programmed by injecting electrons from the substrate to the floating gate. This is done by appropriate doping in the m-channel region and by applying an appropriate voltage to the source, drain and other interpoles. Two techniques for removing charge from a dirty gate to erase a memory cell are the three types of arrays described above. - Techniques ',,,, ..., bungee and other gates apply appropriate voltages from the = part of the dielectric layer between the floating interpole and the substrate to erase:, the erase technique is via a floating The intervening dielectric layer between the gate and the other gate transfers the electrons from the floating gate to the other gate. In the above =:: the type of unit is provided for this purpose - the third erase = In the third type of unit described above (due to the use of -1, there are already three gates at 7°), the floating gate is removed to the point where it does not require one or four idle poles. Add:: by sub: the second function of execution, but these functions are performed at different times: thus avoiding the necessity of two conflicting requirements (4) In addition to the technology, 'a large number of memory cells are grouped together' Simultaneous erasure in the second door. In one method, the 'group includes enough == early ^ stored in the disc sector to be stored, i.e., 512 bytes) plus some additional items. In the other method, 'every-(9) contains enough units to hold thousands of bits of shouting = m for the same amount of data in the slice sector). In the US patent foot test = bucket = multi-zone (four) in addition to 'defect management and other flashes in the majority of integrated circuit applications, flash eeprom system also exists 123977.doc 200820428 Λ铋 a ^ body circuit function required The pressure of the shrinkage of the substrate region is continued, and it is necessary to increase the number of 4 and 2 materials that can be stored in a given area of the substrate to increase the storage of the memory card and other types of seals. Capacity, or both capacity and size. One way to increase the density of the data is to store more than one bit in each memory cell. This is done by placing a window of floating gate charge level voltage ranges into two or more states. The use of four of these states allows for the storage of two bits of data per 7 cells, and the state of each person allows for the storage of one bit of material per cell. The multi-state flash EEpR〇M structure and operation are described in U.S. Patent Nos. 5,94, and 5,172,33. Increasing the data density can also be achieved by reducing the physical size of the memory cells and/or the total array. When processing techniques are modified over time to permit implementation of smaller feature sizes, the reduction in integrated circuit size is typically performed for all types of circuits. However, since there is usually at least a feature that is limited to what extent it can be reduced, so that the total layout can be reduced by =, so there is usually a limit on how much the circuit layout and the size of the given circuit can be & . When this happens, the designer will go to one of the new or different layouts or shelves # of the circuit being implemented to reduce the amount of area required to perform its function. The above flash EEPRQM integrated circuit system (reduction can achieve similar limitations. t Another flash EEPROM architecture uses a pair of floating gate memory cells and polymorphic memory on each floating gate. In this type of cell The two floating gates are included on the channel between the source and the drain diffusion region (having a selective transistor between the source and the non-polar diffusion region). Each of the floating gates 123977.doc 200820428 A row includes a pilot gate and a word line is provided thereon along each of the floating gates. When a given floating gate is accessed for reading or programming, the cell containing the floating gate of interest is The pilot gates on the other floating gates are raised enough to turn on the channels under the other floating gates regardless of the charge level present on them. When reading or programming the floating gates of interest in the same memory cell 'This effectively eliminates other floating gates as a factor. For example, the amount of current flowing through the cell (which can be used to read its state) is the floating gate of interest, not the other word in the same cell. An example of the amount of charge on the gate is described in U.S. Patent Nos. 5,712,180, 3,573, and 6,151,248. In volatile memory, carefully control the amount of field coupling between the floating gate and the control electrode passing over the floating gate. The coupling amount determines the percentage of voltage applied to the control gate coupled to its floating gate. The percentage of the surface area of the floating gate that overlaps the surface of the gate of the control gate J is determined by a number of factors. It is usually necessary to maximize the amount of overlap between the floating gate and the control gate. The method of increasing the area of the face is described in U.S. Patent No. 5,343, the disclosure of which is incorporated herein by reference. A large vertical surface of the gate surface. Another method for increasing the coupling-floating pole and a region of the control gate is described in Yuan Patent No. 6,9() 8, 817. When adding adjacent floating gates and controls Gate The vertical coupling area between the two is to be increased by increasing the area of the substrate occupied by each unit, 123977.doc -10- 200820428. Similarly, the buckle is also good to reduce the ocean gate and float. In order to make the neighboring floating 〇 子 子 子 子 子 。 。 。 。 。 。 。 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 r due to the reduced area of the relatively floating closed-face facet in the direction of the squall line, the shape of the listened M reduces the coupling between adjacent floating gates in the direction of the bit line. The size of the upper part of the positive gate

The reduction in U (compared to a floating gate having a rectangular shape) provides more space for controlling the idle and dielectric layers between adjacent floating electrodes in the word line direction. A variety of processes can be used to produce floating memory arrays with inverted τ shapes. One of the processes for forming an inverted-T-shaped floating gate uses a mask portion to form an STI structure and a channel region extending in the direction of the bit line. # Forming the mask portion > by using Slimming to make the channel region narrower than the STI structure. The channel can also be narrower than the minimum feature size of the lithography process used (7). Subsequently, a first floating gate layer is formed, and the first floating gate layer is patterned into a first floating gate portion that is wider (and comparable to F wide) than the lower channel region using an additional mask portion having sidewall spacers A high tolerance is provided for one of the misalignments between the first floating gate portion and the channel region. Subsequently, the pattern j is further provided with a mask portion and a sidewall spacer such that the grooves between the sidewall spacers extend from the first floating gate portion. A second floating gate portion is formed in the slots. Subsequently, a dielectric layer and a control gate layer are formed on the floating gate layer and etching is performed to divide the control gate layer into word lines, and at the same time, the floating gate portion is divided into individual floating gates. 123977.doc -11 · 200820428 Another process for forming a - inverted τ-shaped floating closed-pole forms a first floating gate layer and then uses the mask portion on the first-floating idler layer to establish a structure for STm The position ' makes the STI structure self-aligned with the first floating gate portion formed by the first floating closed layer. The STI structure has sidewalls that extend vertically to a level of the first floating gate portion. The sidewall spacers are formed on the side walls such that the sidewall spacers leave a second floating gate portion on the first floating pole portion formed in the slots such that they are self-aligned with the first floating idle portion. Subsequently, the sidewall spacers are removed and partially tapered. A dielectric layer and a control gate layer are deposited on the floating interrogation portion. The dielectric layer is then controlled to control the closed layer and the floating gate portions together such that the word lines of the self-aligned floating gates are formed. The other process for forming an inverted-to-theta-shaped floating-pole uses a mask portion extending in the direction of the bit line to form a floating closed-pole layer. A portion of the floating interlayer is partially covered by the mask portion (4) to cover a portion of the floating layer, and when the unshielded portion of the net gate layer is removed, a portion of the gate layer is followed by a vertical dog discharge. This part of the etched etched through the floating gate layer. With: 'fine by - reduce the thickness of the vertical protrusions on the sidewalls of the oxidation process to form a sidewall spacer" η μ and then use these sidewalls as a cover "floating gate layer, thus forming an independent Floating gate section. The sidewall spacer is also used as a mask for the etched underlying substrate to form the STI trench. Cerium oxide is added to fill the ruthenium and sidewall spacers, and a dielectric #二*a is deposited. Remove the mask portion θ and the gate layer. The gate layer, dielectric layer, and floater will then be protected with the word line of the floating pole. Sickle knives to form self-alignment 123977.doc -12- 200820428 [COMPLEX MODE] Memory Operation An example of a memory system 100 incorporating various aspects of the present invention is generally illustrated in the block diagram of FIG. A large number of individually addressable memory cells are arranged in the regular array 110 of columns and rows, but other physical unit configurations are of course: a possible M-series line (indicated herein as extending along the row of the cell array 110) The one-line decoding and driving circuit 130 is electrically connected by a line 150. The word line Γ (which is here shown as extending along the column of the cell array uo) is electrically connected to the word line delineation drive circuit 19G by the line 170. Each of the decoding and 19〇 receives the memory unit address from a memory controller 18 via the bus bar 160. The decode and drive circuits are also coupled to controller 180 via respective control and status signal lines 1 3 5 and 195. Controller 180 can be coupled to a host device (not shown) via line 140. The machine can be a personal computer, a notebook computer, a digital camera, an audio broadcast player, various other handheld electronic devices, and the like. Figure 1 memory ί, system, first 100 pass # will be implemented in a number of existing physical and electrical standards

One of the removable cards (such as from PCMCIA, C〇mpactFlashTM Association, MMCTM and/or his association). Other removable formats include USB flash drives such as the Cruzer_flash driver. When in the pick-up mode, the line 140 terminates in a connector with a complementary connector of the host device. The interface of many removable memory systems follows the ΑΤΑ π 〃 〃 ° 饫 饫 看来 看来 看来 看来 看来 看来 看来 看来 看来 看来 看来 看来 看来 看来 看来 看来 看来 看来 看来 看来 看来 看来 看来 看来There are also other memory card interface standards. As an alternative to the card format, a memory system of the type not shown in Fig. 1 can be permanently embedded in the host device 123977.doc -13 - 200820428. The decoding and driving circuits 130 and 190 generate appropriate voltages in their respective lines of the array 11 to perform programmatic and read operations in accordance with the respective control and status lines 135 and 195 when addressing via the bus bar 16? And erase function. Array 110 provides any status signals including voltage levels and other array parameters to controller 经由8 via the same control and status lines 135 and 195. A plurality of sense amplifiers in circuit 130 receive current or voltage levels indicative of the state of the addressed memory cells in array ,, and provide information regarding their states to control via line 145 during a read operation 18 〇. A large number of sense amplifiers are typically used so that the state of a large number of memory cells can be read in parallel. During a read and program operation, a plurality of cells in the addressed column selected by circuit 130 are typically accessed by circuit 190 at the same time as one of the addressed cells. During an erase operation, all of the cells in each of the many columns are typically addressed together as a block for simultaneous erasure. FIG. 2(A) shows a NAND memory cell array C formed on a substrate; a plan view of an example of a column uo, wherein for the sake of clarity, there are few dielectric layers present between 70 pieces. The details illustrate the small portion of the repeating structure of the conductive element. Extending through the surface of the substrate to form shallow trench isolation (STI), O-structure 210a-d. To provide an agreement for this description, the STI structures are shown spaced apart in the -X direction, the length extending in the second ¥ direction, and the first and second directions are substantially orthogonal to one another. - Between the STI structures 210a-d, there are memory strings 220a-c that are extended in the ¥ direction. Therefore, the direction of the string is parallel to the direction of the STI structure. Each of the strings 22A-c includes a plurality of memory devices connected in series. Figure 123977.doc -14- 200820428 2(A) shows one of three strings 22〇a_c, where each string shows three memory cells. However, string 220a-c may contain additional elements not shown in Figure 2(A). Similarly, array 110 contains additional strings not shown in Figure 2(A). This type of array can have (four) thousand strings 'each-string with 16, 32 or more units.

An exemplary memory cell includes a floating gate 23A and a source/drain region 240a-b in the substrate adjacent to the floating gate 23A on either side of the meandering direction. The strings are separated by the STI structure 21〇a_d. The sti structure 21 Oa-d forms an isolation element that electrically isolates the source/drain regions from the source/drain regions of the cells in adjacent strings. In the gamma direction, adjacent cells share a source/drain region. The source/drain regions electrically connect one cell to the next cell, thus forming a cell string. The source/drain regions 240a_c in this example are formed by implanting impurities into the substrate in the desired region. The floating gate shown in the embodiment of Fig. 2(A) includes two portions which are better seen in the three-dimensional view of the floating gate 230a shown in Fig. 2(B). The lower oceanic gate portion 231 extends over the surface of the substrate on a thin layer of tantalum dioxide (oxide). The upper floating gate portion 232 protrudes upward from the upper surface 233 of the lower floating gate portion 231 to form an inverted z-shaped cross section in the meandering direction. The upper floating gate portion 232 extends in the meandering direction to the edge of the lower floating gate portion 231, but is narrower in the meandering direction. Therefore, the floating gate is wider than the intermediate level below the intermediate level, thereby partially exposing one of the upper surfaces 233 of the lower floating gate portion 231. The lower and upper floating gate portions 231, 232 of this embodiment are all made of doped polysilicon. The polycrystalline germanium may be deposited in an undoped form and later implanted in a doped form, or may be deposited in a doped form. In the embodiment - the inter-electrode pole portion 231 is deposited as an undoped gate portion 232 deposited as a doping _ on the upper side of the upper floating gate portion after the "temperature" of the "H 4 @ period 樜 = X The change of 232 is diffused to the lower floating gate Qiu Ba ', and the strip B 231 ' makes it also doped and 1. Other suitable conductive materials can also be used instead of doped polycrystalline stone. The pole portion 231 and the upper floating gate portion 232 may also be deposited in a single layer rather than in two separate layers. The word lines 250a-c are shown in Figure 2(A) as extending the three word lines on the array in the other direction. The portions 250a-c cover the floating gate 23A, and also partially ring the floating gate 230a. In the illustrated embodiment, the word line 2 鸠 covers the exposure of the upper surface 233 of the lower floating gate portion 231. Partially, the upper surface and the side surface of the upper floating gate portion 232 are closed. The ± _ floating gate portion 232 increases the surface area of the floating gate coupling the floating gate 230a with the control gate 25 〇 b. In contrast, this increased area provides an improved coupling ratio. Metal is not shown in Figure 2(A). Body layer. Since a polysilicon element such as a word line has a conductivity that is significantly less than the conductivity of the metal, the metal conductor is included in a separate layer that is connected at any periodic intervals along the length of the polysilicon element via any intermediate layer. Similarly, the word line may include a metal or metal germanide portion to increase the conductivity of the word line. For example, a refractory metal such as cobalt or tungsten may be used to form a germanide layer on top of the polysilicon layer. The telluride material has a higher conductivity than polysilicon' and thus improves the electrical conduction along the word line. 123977.doc -16- 200820428 Process for forming an inverted τ floating gate Figure 3 shows Figure 2(A) A cross-sectional view of the NAND memory array 11 at the early stage of manufacture along the X direction (word line direction) indicated by I-Ι in Fig. 2(A). Layer of tantalum nitride (SiN) or other mask material 3〇1 extends over the upper surface 310 of the substrate 3〇5. The mask layer 301 can be deposited to cover the entire upper surface 3〇3 and thus is considered to be a blanket layer. The photoresist portion 3〇7a<forms On the mask layer 3〇1. Usually The photoresist is spin coated at a high speed to form a blanket layer that is subsequently patterned by exposing the photoresist to light (or, in some cases, to an electron beam) according to a predetermined pattern in a lithography process. This pattern determines which portions are removed and which portions are retained when the photoresist is developed. The photoresist portions 307a-c extend in the Y direction (perpendicular to the cross section of Figure 3) and cover the mask layer 301. Given the lithography used The limitation of the process can form a very small and closely spaced photoresist portion 3〇7a_c. In an example, when the photoresist/knife is deposited, the width of the photoresist portion is equal to the minimum feature size f, 1 when the photoresist is deposited In part, the distance between adjacent photoresist portions is F. 'However, in the present embodiment, the green portion 307a_c is subjected to a refinement process that removes some of the photoresist' such that the photoresist portion a_e has a width less than the minimum feature size J, U.S. Patent No. 6,888,755 and An example of the refining agent refining treatment is described in U.S. Patent Application Serial No. 11/316,654. Subsequently, the resist layer 3G7a_e is used to pattern the mask layer 301 into a mask connector in the same pattern as the Newports a_e. The mask portion is used as a residual mask to form a trench for isolation. . Fig. 4 shows a mask portion 409a-c patterned using the photoresist portion and a trench formed by using the mask portion 409a-c as a mask. Once the mask layer 3 (H is patterned to form a separate mask portion), the photoresist portions 307a-c can be removed. Next, an anisotropic etch is performed at the appropriate location using the mask portion. A groove is formed in the substrate 3〇5 between the regions of the substrate 3〇5 covered by the mask portions 4〇9a-c.

Cerium oxide (Si 〇 2 or "oxide,") 411 fills the trenches. Subsequently, the mask portion and the over 1 cerium oxide 411 can be removed (for example, by CMP or using an etch back treatment) to remain The next flat surface is shown in Figure 5. The ruthenium dioxide filled trench forms a shallow trench isolation (STI) structure 21〇a_d. The sti structure 21〇ad provides isolation between adjacent memory cells. STI structure 2i〇a_d extends in the Y direction. Between adjacent STI structures 21〇a_d is the remaining substrate portion 5 1 5 ac (after which 5 丨 丨 单元 unit is formed here). Unlike some previous structures, The STI structure 21〇ad of 5 is wider than the remaining substrate portions 515a-c therebetween, and the remaining substrate portions 515a-c are narrower than the minimum feature size of the lithography process used. After the planarization step, as shown in FIG. Forming a gate dielectric layer 617 (in this example, cerium oxide) on the substrate 3〇5 (eg, by thermal oxidation or deposition), and first of the conductive material (in this example, polysilicon) A conductive layer 519 is deposited on the gate dielectric layer 617. The mask layer is deposited on the first conductive layer 5 19 and patterned The mask portions 521a-c are formed on the remaining substrate portions 515a-c. In this example, the mask portions 521a-c are tantalum nitride and patterned using photoresist, but in this case no resist refinement is used. The mask portions 521a-c are positioned on the remaining substrate portions 515a-c such that the pattern of the mask portions 521a-c is aligned with the existing pattern of the STI structures 21a-c and the remaining portions 515a-c. After forming the mask portions 521a-c, Side 123977.doc -18-200820428 wall spacers 523a-f are formed along the sides thereof. This sidewall spacer is well known and can be achieved by depositing a dielectric layer and then performing an anisotropic engraving. Prior to the sidewall spacers 523a-f, the gap between the mask portions 521a-c is the minimum feature size (F). The sidewall spacers 523a-f reduce this gap such that it is smaller than the minimum feature size. It will then have sidewall spacers 523a-f The mask portion 52la_c acts as an etch mask to etch through the first conductive layer 519.

A portion of the first conductive layer 519 of C is then replaced by a suitable dielectric (in this example ''oxidation^). 7 shows that the first conductive layer 519 is divided into the first conductive portion 5 in the γ direction (perpendicular to the cross section of FIG. 7), and the mask portion 52U-C and the sidewall spacer 523 are removed to thereby remove the mask portion 52U-C and the sidewall spacer 523. The structure of Figure 6 after the flat surface is provided. Removal of the mask portions 52la-c and sidewall spacers 523a-f may also remove any excess dielectric such that only the electrical points 725a-b between the first floating gate portions I remain. The first conductive portions 519a-c are electrically isolated from each other by the dielectric portion ab and are isolated from the lower remaining substrate portions 515a-e by the gate dielectric layer 617. Subsequently, another mask layer is formed and patterned. FIG. 8 shows that the shape & % Chu is raised above the first conductive portions 519a-c and the dielectric portions 725a-c (Nitride, first) The structure of FIG. 7 of the mask portion 827 ad and the (secondary oxide cut) side soil spacer 829a_f. The mask portion β ~ wall spacer 829a_f ' may be formed as described above such that the gap between the sidewall spacers (4) is smaller than the minimum feature size J J and the gaps are formed to extend upward from the first conductive portion 519 ac 6:51a'e. Forming the mask portions 827a-d involves aligning the pattern used to form the mask portion knives 827a-d with the pre-existing structure. 123977.doc -19_ 200820428 In this case, the mask portions 827a-d are located above the STI structure 2i〇a_d such that the trenches 831a-c between the sidewall spacers are centered on the first conductive portions 519a-c. After iw, the second floating gate layer is deposited to fill the trenches 83a-c. FIG. 9 shows the result of depositing the second conductive layer 933 to fill the trenches 831a-c. In this example, the material of the second conductive layer 933 is doped polycrystalline. The second conductive layer 933 is at the bottom of the trench 83^ and the first conductive portion. Contact and form electrical contacts at these points. After depositing the second conductive layer 933, executable

: etching (or a series of different etches) to remove excess material of the second conductive layer 933 and removing the mask portions 827a-d and sidewall spacers 829a-f. The figure shows the result of removing excess material of the second conductive layer 933, the mask portions 827a-d, and the sidewall spacers 829a-f. As shown in Fig. 1A, the second conductive portions 933a-c are still extended upward from the first conductive portion 519a-c to form an inverted Tau-shaped cross section. The second conductive portion 933a_c remains at the location where the slot 831&<> is formed and its size is determined by the slot 831a-c and may be less than the minimum feature size. Subsequently, a second tantalum layer is deposited on the first and second conductive portions, and a control gate layer is deposited on the second dielectric layer. FIG. 11 shows the structure of FIG. 10 having a second dielectric layer 1135 covering the first conductive portions 519a-c and the second conductive portions 933a_C and having a control gate layer 1137 covering the second dielectric layer 1135. In this example, the material of the gate layer 1137 is doped polysilicon. An additional layer of tungsten, cobalt telluride or other conductive material may also be added to the polysilicon to provide a control gate layer having a lower sheet resistance. The second dielectric layer i can be

Under Poly, non-polycrystalline materials can be used for conductive parts or for control of idler materials, or for use in conductive part materials and control gate materials in 123977.doc -20- 200820428. In the example of the figure, the second dielectric layer !135 is composed of a layer of cerium oxide (oxide), followed by a layer of tantalum nitride (nitride), followed by another layer of cerium oxide (oxide). Composite layer. This oxide-nitride-oxide (0N0) stack provides a pattern that can be performed more than a single dielectric material and is more awkward in phase synchronization. After forming the control gate layer 113 7 , the step of dividing the control gate layer 1137 into word lines 25 〇 a_c

In the step, the first and second conductive portions are divided into independent floating electrodes. In this way, the floating gate and word line are self-aligned. Figure 12 shows a flow chart summarizing the process of Figures 3 through 。. First, a mask layer is formed on a substrate and a photoresist layer (i24i) is formed on the mask layer. The photoresist layer (1243) is patterned and then subjected to retouching (1245). The mask layer is then patterned into a mask trowel (1247) using a refined photoresist portion. The mask portion forms a mask layer for establishing the location of the trenches, filling the trenches with a hafnium oxide and performing planarization to form an STI structure (1249). Next, a deposition-gate dielectric layer and a first floating-level layer (1251) H are formed on the floating gate layer to form a mask portion (1253) and a sidewall spacer (1255) is formed on the side of the mask portion. Next, the mask portion U-sl separator is used as a mask to etch the first floating gate layer (1Μ7) and become a separate first floating gate portion. A dielectric is deposited to fill the gap between the gate portions and then planarization (10) 9) is performed to f: excess dielectric, mask portions, and sidewall spacers. A further set of mask portions and sidewall spacers (1261) are formed on the first floating gate portion. The positioning mask portion is and the side wall spacer # such that the groove formed between the side wall spacers covers the first 'heart' and the file. The slots (1263) are filled with a second floating gate layer, and 123977.doc -21 · 200820428 then the excess second floating gate material is removed (1265) along with the mask portion and the sidewall spacers, leaving the first Two floating gate sections. This exposes the surfaces of the first and second floating gate portions. Subsequently, a dielectric layer is deposited over the first and second floating gate portions, and a control gate layer (1267) is deposited over the dielectric layer. An etch step etches the stack formed by the previous process such that the control gate layer is divided into individual word lines and the first and second floating gate portions are divided into independent floating gates (1269). Therefore, the floating gate is self-aligned with the word line.

Figure 13 shows the structure of Figure 2A in three dimensions. The word lines 25〇a_d extend in the X direction and are spaced apart in the Y direction. Word lines 250a-d form control gates that overlie them and are coupled to individual oceanic gates. The STI structures extend in the Y direction and are spaced apart in the X direction. The word line 25A_c can be used as an implant mask to implant the source/drain region between the memory sheets S in the Y direction. This implant connects the memory cells into a string extending between the STI structures 210a-e in the ¥ direction. The individual floating gates consist of a lower portion and an upper portion as shown in the figure. The advantage of the structure is that there is less capacitance dissipation in the gamma direction between adjacent floating gates. Some prior structures use a floating gate of lateral dimensions determined by the minimum feature size of the lithography process used in the X direction. The embodiment of Figure 13 has a 'preferred gate that is narrower than the upper portion of the minimum feature size. This means that the area of the exposed facet of the floating gate of Figure i3 is reduced by j, which in turn reduces the capacitive coupling between adjacent floating gates. This can be done in such a way as to reduce the facet area without coupling the idle control and the floating gate. The _-view coverage between the control and the floating gate depends on the total area of the control gate of the surface of the gate. 123977.doc -22 - 200820428. This is not affected by ^; γ 士 in the χ direction makes the upper part of the floating gate narrower. In addition, in the only example of the 0f knife mouth u in Fig. 13, between the floating gate and the control gate coupled to it, relative to the floating power between the neighbors in the gamma direction and the neighboring one in the gamma direction The side of the old Qiongyuan ~ can be reduced. This is because the distance between the facet of the floating gate and the facet of the eclipse of the eclipse in the Y direction is compared to the control of the closed disc obscenity jL^r. The distance between the centers of the facets of the sub-gates is reduced. The coupling between the floating gate and the control gate is improved with the floating gate and the ,, , and the ratio between the adjacent ones in the Y direction. The structure of Figure 13 - the advantage is that it can be scaled down to a smaller size than some other structures. In detail, because the upper part of the floating gate is relatively narrow, so at this level, this leaves more space between the floating gates' to allow more space for controlling the gate and dielectric layers. . Given some limitations on how much control gates and dielectric layers can be fabricated, this allows the memory to be fabricated earlier than if the upper portion were larger. Figure 14 illustrates this concept. The cross-section along the word line 25 〇〇 (i.e., along the χ direction) does not have some of the dimensions indicated. The distance between one point on the floating gate 230 and one of the points on the center of the adjacent floating gate 23 in the ~X direction is twice the size of the minimum characteristic (2F). In Fig. 14, the distance is shown to extend from the side of the upper portion of the floating gate 230x to the side of the upper portion of the adjacent floating gate 23 Oy in the x direction. At a distance 2F, there is a floating gate portion 1471 having a thickness h above and a dielectric layer ι 35 having a thickness "the portion 1473 of the word line 250c and having a thickness therebetween". Therefore, in this example, 2F = tl + t2 + 2t3. Size tl,. And “There may be certain minimums for any given material to avoid high failure rates. Typically, 123977.doc -23- 200820428 when the upper floating gate is partially multiphase/, ‧$ k is not less than 1 〇〇 Similarly, the 'right word line is made up of polycrystalline stone eves < 7 into '1:2 will be no less than 1 〇〇. When the dielectric is ΟΝΟ layer, t3 will be 丨 、, 田" The 3-way hoist will be no less than angstroms, so use these minimums, 2F = 440 angstroms and !7 = 22 angstroms (2, 璆 (22 not). Therefore, for some materials 'can be shown as small黾太2 does not have enough minimum feature size structure to maintain sufficient performance. In contrast, if ^ right "-F (the upper part has a size equal to the minimum feature size), then ρ, and substitute 畀|姑^ five generations Minimum value; p = 3 4 0 angstrom

(34 nm). Although these examples are specific to τ only π /, 疋 枓 and their limitations, other restrictions may apply if other materials are used. Another advantage of the embodiment of Figure 13 is that it is relatively insensitive to misalignment that may occur between components. For example, if the first floating gate 23 is misaligned with respect to the STI structures 210a-d, this may not seriously affect device performance. Figure 15 shows the first conductive portions 519a-c and the core c formed by the remaining substrate portion 515. The misalignment between the channel regions is δι. Since the first conductive portion 519a_c is made wider than the minimum feature size, and the remaining portion 5丨5a < is made smaller than the minimum feature size, the first conductive portion 51% < still covers the channel The entire width of the region, and the coupling between the first conductive portion and the channel region does not vary greatly under such conditions. In other embodiments, where the first floating gate portion is not made larger, The channel area is made smaller, and this provides sufficient margin for alignment errors. Similarly, providing a wide first floating gate portion without adequately making the channel small can be sufficient Figure 16 shows the misalignment § 2 between a lower floating gate portion 1675 and an upper floating interpole portion 1677. In this case, the floating gate ι 679 (from the lower 123977.doc -24-200820428 portion 1675 and Upper The portion 1677 trowel 1677 is formed) and the surface contact between the overlying control gate remains unchanged. 'Because the light and the smear of the gate 1679 and the control gate are not moved in the X direction, The effect is that the structure of Figure 13 is relatively resistant to misalignment. θ Self-alignment process The process described above - the alternative process uses self-alignment to generate no need - Independent alignment steps to establish features of their relative position. The entire process flow can be simplified by eliminating the need for a separate alignment step, and thus the cost can be reduced. Additionally, faults due to misalignment can be reduced or eliminated. Figure 17 shows NAND memory. The body array has a cross section in the X direction at the beginning of fabrication. The STI structure 1701 extends in the x direction and is shown in the cross section in Figure 17. Between the STI structures 1701a-d, the gate dielectric portion 17〇3^4 The first conductive portion HOSa-c extends in the gamma direction. The structure shown in Fig. 17 is usually formed by depositing a blanket layer of a gate dielectric (in this case, cerium oxide) followed by a conductive material. Formed by a blanket layer. In this In the example, the conductive material is a polysilicon deposited to a thickness of 10 nm. Next, a mask portion extending in the Y square white is formed on the floating gate layer. The trench is formed according to the pattern of the mask portion. Extending through the conductive layer, the gate dielectric layer and extending into the underlying substrate. The trenches divide the conductive layer and the gate dielectric layer into the first conductive portion 17〇5a_c and the gate dielectric portion 1703a_c, respectively. An electrical material (cerium oxide in this case) is used to fill the trenches to form STI structures I 701a-d. Subsequently, the mask portions are removed from the first conductive portions 1705a-c to expose the sidewalls of the STI structures 1701a-d. . Subsequently, sidewall spacers are formed on the sidewalls of the STI. 123977.doc -25- 200820428 Figure 18 shows the structure of Figure 17 after the sidewall spacers 1807a-f are formed along the exposed sidewalls of the STI structure 17〇la-d. The sidewall spacers 18〇7a-f are formed by depositing a hafnium oxide layer using a process based on tetraethyl orthophthalate (Tetraethyl 0rth〇siHcate, tE〇s) and then performing an anisotropic etching. The side spacers l807a_f cover the first conductive portions POTa-c. Slots 1809a-c are formed between sidewall spacers 18A, 7a-f on first conductive portions 1705a-c such that portions of first conductive portions 1705a-c are exposed. Figure 18 shows the movement down of the grooves 18〇9a-c (except for some of the first conductive portions 1705a <RTIgt; to form holes 1811a-C at such locations. The holes 1811a-c are in the sidewall spacers 18〇7a-f and the first The conductive portions 1705a-c extend between. After the dielectric layer is etched to form the trenches i8〇9a_e, the holes 丨8丨丨a_c can be formed by performing an additional wet etch. In some cases, there is no space. The hole is formed in the first conductive portion, so no wet etching is required. Subsequently, a second floating gate layer is deposited. Figure 19 shows a (doped polysilicon) second conductive layer 1913 deposited on the structure of Figure 18. In other words, the second conductive layer 1913 is deposited to fill the first conductive C; the holes 1811a_c in the adjacent knives n〇5a-c, and the trenches 1809a-c covering the first conductive portion ac are filled. The second conductive layer 1913 is also covered. STI structure 1701 &- (1 and sidewall spacers 18〇7 & 彳. The formation of holes 1811 & ^ allows good between the first conductive portion 17 〇 5a-C and the second conductive layer 1913. In detail, when When the second conductive layer 1913 is deposited, it fills the holes i8iiw, and this provides a stable substrate for the structure formed after the formation. The increased interface area between the first conductive portions 5a c 舁 the first electrical layer 1913 improves the physical strength of the bond between the portions. This can be important to avoid damage during later processing. If the second floating idle portion is not sufficiently fixed by 123977.doc -26-200820428, the CMP or other process may break the second floating gate portion. In some other examples, such holes may not be used. Because sufficient contact can be achieved without such holes. Figure 20 shows the structure of Figure 19 after planarization to remove excess material from the second conductive layer 1913. This causes the second conductive portion 1913a- c is attached to the first conductive portions 1705a-c. This can be achieved by chemical mechanical polishing (CMp) or etch back or other methods. This planarization can also be moved from the STI structure 17〇u_d and the side spacers l8〇7a_f Except for some materials. Subsequently, additional material was removed from the STI structure i7〇la-d and the sidewall spacers 18〇7a-f. Figure 21 shows that the sidewall spacers 18〇7a_f are not removed and the ST] is removed [structure i7〇ia_d The file is up to a level close to the gate dielectric portion 17〇3a_c The structure of the latter figure. In some cases, the portion of the STI structure is removed until it is below the level. For example, the STI structure can be etched under the level of the top of the gate dielectric portion. In other cases, the STI material is removed until a level as indicated, such as the level of the first conductive portion 1 / page f. Subsequently, a dielectric layer and a control gate layer are formed over the conductive portion. Figure 22 shows the structure of Figure 21 after depositing a dielectric layer 2215 and a control gate layer 2217. The layers can be deposited as previously described, and then the word lines and the individual floating spaces are formed in a self-aligned manner by patterning the layers according to a pattern to form a memory array similar to that shown in FIG. The memory array in which the floating gate has a inverted shape as shown in FIG. 2β. In the example, one portion 2219 of the control gate layer 2217 extends downward between adjacent first conductive files 1705a, 1705b, and thus is provided adjacent to the lower end of the word line side 123977.doc -27-200820428 Shielding between floating gate sections. Figure 23 shows a flow chart summarizing the processes of Figures 17-22. First, the first oceanic gate layer and the gate dielectric layer are formed as a blanket layer (2321). Next, an STI structure (2323) is formed, thus dividing the first floating gate layer into separate portions that later form individual floating gates. A sidewall spacer (2325) is formed on the exposed side of the sti structure covering the first floating gate portion such that the trench remains on the floating gate portion. The wet residual removes some of the exposed first floating gate material and some of the floating gate material (2327) under the sidewall spacers. / A second floating gate layer is accumulated to fill the trenches and holes (2329). Next, the overlying second floating gate material is removed (2331) along with the sidewall spacers and portions of the 8-but 1 structure. Next, a dielectric layer and a control gate layer (2333) are deposited on the floating gate portion ST]. A patterned etch is then performed to form a self-aligned independent word line and floating gate (2335). Sidewall Oxidation Process In an alternate embodiment, an inverted T-shaped floating gate is formed by: forming a conductive layer by removing a conductive material, and then dividing the conductive layer into individual conductive portions and forming an STI trench to Make it self-aligned with the conductive portion. Figure 24 shows a cross-section of the NAND memory array along the x-direction in the early stages of fabrication. A gate dielectric layer 2402 (in this example, a cerium oxide gate dielectric layer) is present on the substrate 2400, and a conductive layer 2404 (in this example, a doped polysilicon conductive layer) covers the gate dielectric layer 2402 . Conductive layer 2404 can be deposited in a single step to form a uniform layer, or conductive layer 2404 can be deposited in more than one step such that conductive layer 2404 includes, for example, no. 123977.doc -28-200820428 in different layers. The degree of polycrystalline dreams. The mask portion 24?6a-c (in this example, the nitride-shield portion) extends in the gamma direction (perpendicular to the cross-section shown) on the conductive layer 2404. The conductive layer 2404 is formed by making a ruling in the pattern of the mask portions 24G6a-e. In this case, the conductive layer 4 is not illustrated until the lower-gate " electrical layer 2402. The portion of the conductive layer 24〇4 can be etched away by reactive ion characterization (8) or by some other anisotropic etching method. The mask portion 24 of Figure S (the width of the ^ can be equal to the size of the last lithography process used or can be smaller under certain conditions. Anti-pseudo-refinement or other methods can be used to reduce the mask The width of the portion 24〇6a_c". Because &, the spacing between adjacent mask portions 2406a-c may be the minimum feature size (F) or may be larger. When etching has removed the portion of the conductive layer 24〇4 The vertical protrusions 2408a-c are formed by the remaining portions of the conductive layer 24A4 covered by the mask portions 2406a-c. The vertical protrusions 24A8a-c later form the upper portion of the floating gate. 25 shows the polycrystalline stone of the electric layer 2404 after the oxidation is performed to grow the ceria layer 251 on the exposed surface of the conductive layer 24〇4 and the exposed surface of the mask portions 2406a-c. The oxidation of the eve consumes some polycrystalline stone to form the ruthenium oxide layer 25 1 0. Therefore, when the ruthenium dioxide layer 25 形成 is formed, the floating gate layer 24 〇 4 is partially consumed and the size is reduced. The size of the vertical protrusions 2408a-c decreases in the X direction. Similarly, the size of the mask portions 2406a-c is reduced by oxidation. The thickness of the ruthenium dioxide layer 25 and the polysilicon and nitrite consumed can be controlled by controlling the total oxidation time and controlling the processing conditions. Suitable processes for oxidizing polysilicon and nitriding. Lower temperature (less than 5 degrees Celsius) using an oxy group to perform oxidation of 123977.doc -29- 200820428. For example, decoupling plasma nitriding (clear) or slotted planar antenna (SPA) A plasma processing system can be used to oxidize polysilicon and tantalum nitride. In an alternative embodiment, 'anti-reagent refinement or other methods can be used to form narrow mask portions and vertical protrusions. Next, a dielectric layer can be deposited on The narrowed portion I and the vertical protrusions are formed to form a structure similar to that of Fig. 25. The structure shown in Fig. 25 after the anisotropic residue is formed to form the sTI junction trench 2612. Etching to the opposite sex leaving a dioxent along the vertical protrusion center f ° and the sidewall of the mask portion _a_C such that sidewall spacers 251 〇 af are formed. The cerium oxide is etched through the sidewall spacers 2510a-f, And then etched through the underlying conductive layer 24〇4 After partially forming the individual conductive P-knife 2404a c, the substrate 2400 is etched to form a trench 2612 having sidewall spacers 251 defining the locations of the sides of the trenches 2612a-b. The dioxide dioxide layer 25U) and the lower layer The substrate (4) can be performed as a separate process using different chemical treatments. The trenches 2612a-b are then filled with the dioxide. The ruthenium dioxide fills the trenches 2612a-b beyond the surface C of the substrate 24, such that The dioxide is filled in a groove between the side spacers 2510a-f (also formed by the formation of the dioxide). Then, flattening can be performed to remove the mask portion and the dioxo until a certain level. Then perform - (iv) to remove additional cerium oxide. Figure 27 shows the results of planarization and additional characterization, such that the dioxide is removed until the bit _ of the lower portion of the conductive enthalpy 2404a_c, leaving the ST] structure in some instances 'can remove the dioxin To different levels. At this stage, no mask is partially retained. Flattening can be achieved using a process that stops only after removing all of the material of the mask portions 2406a-c. In other examples of 123977.doc -30-200820428, some of the material of the mask portion 24 can be left after planarization.

Subsequently, a dielectric layer 2818 is deposited over the conductive portions 24〇4 &< and a control gate layer 2820 is deposited over the dielectric layer 28 18 as shown in FIG. As previously described, the dielectric layer 2818 and the control gate layer 282 are then patterned to form individual word lines and independent floating gate beta structures 27 16a-b in a self-aligned manner than the conductive portions 24 in this example. The floating gate formed by 4a_c is extremely narrow, but a certain range of sizes can be achieved by using different oxidation times and conditions to determine the amount of oxide formed and the amount of underlying polycrystalline germanium consumed. Thus, a memory array similar to that shown in ® 2A (although having a narrower STI structure) is formed with individual floating gates having an inverted τ shape similar to that shown in Fig. 2B. Figure 29 shows a flow chart summarizing the process described in Figures 24-28. First, a gate dielectric layer and a floating gate (four) layer (2922) are formed on the surface of the substrate. Next, a mask layer is formed on the floating gate layer and patterned: 匕 The mask layer (4) is a mask portion (2924) extending in the Y direction. The floating gate layer (2926) is engraved in a pattern created by the mask portion such that some of the floating gate material is removed, but at this stage it does not appear to pass through the floating gate layer. Next, the Bosch _, ^ Ding process (2928) was used to grow the dioxotomy on the exposed surface of the floating interrogation layer and the mask portion. Then perform an anisotropic "silver phase from the grown - oxidation 11 to form a sidewall spacer (Μ sidewall spacer provides a mask for the floating gate (4) (four) alone = money "base f TI trench (29 outside Shi Xi Fill the trench (2934) and fill the trench between the sidewall spacers. Then 123977.doc 200820428 The planarization step removes the mask portion and "some: Oxide State 936." By dividing the money with more dioxo, The upper portion of the floating gate is exposed. The cerium oxide remains in the trench to form an STI structure. Subsequently, a dielectric layer is deposited and deposited on the 4 dielectric layer - the control gate layer (8). Separate word lines and independent floating gates (2940) are formed in a self-aligned manner. Although various aspects of the invention have been described with reference to the exemplary embodiments of the invention, it will be understood that the invention RIGHTS OF THE ENTIRE OBJECT PROTECTION OF THE TENDENCY OF THE INVENTION [BRIEF DESCRIPTION OF THE DRAWINGS] Figure 1 shows a non-volatile memory system in which various embodiments of the present invention may be used, including an array of control and memory cells. A shows an embodiment in accordance with the present invention A top view of the nand flash memory array. Figure 2B shows the individual floating gates of the NAND flash memory array of Figure 2A having an inverted τ-shaped cross section. Figure 3 shows a mask covering a substrate covering at the beginning of fabrication. The cross-section of the NAND flash memory array of Figure 2A of the thinned photoresist portion of the layer. Figure 4 shows that after the mask layer is patterned for subsequent use in locating the mask portion of the STI trench filled with cerium oxide Figure 3 shows the structure of Figure 4 after planarization to remove the mask portion and excess ceria. Figure 6 shows the formation of a gate dielectric layer, a first floating gate layer, Figure 5 shows the mask portion and the sidewall spacer on the exposed sidewall of the mask portion. Figure 7 shows the division of the first floating gate layer with a dielectric-first float. The gate portion and the structure of the mask portion and the side spacer are removed. Fig. 8 shows the structure of Fig. 7 after forming the shield portion and the sidewall spacer to form a groove on the floating gate portion. Deposit a fill: flute 00 ^ with the brother in the slot of the first gate The structure of Figure 8 after the second floating gate layer. Figure 1A shows the structure of Figure 9 after removing the excess second floating gate material and the spacer wall spacer. Figure 11 is not a floating question pole. Fig. 10 shows the structure of the process of Fig. 3 to Fig. 11. Fig. 13 shows the structure of the structure of Fig. 11. The diagram 'includes a separate word line and a self-aligned floating gate that extend over a dirty gate that controls the closed pole.

C Figure 14 shows certain dimensions of the structure of Figure 13. Figure 15 shows the misalignment between the floating idle and channel regions in the memory array. Figure 16 shows the misalignment between the lower floating gate portion and the lower gate portion of one of the floating gates. ^ i Figure 17 shows a cross section of a flash memory array in a structure and a self-material formed first floating gate portion in accordance with another embodiment of the present invention. Figure 18 shows the formation of a sidewall spacer on the exposure (4) of the STI structure such that 123977.doc -33 - 200820428 forms a groove on the first floating gate portion, and the structure of Figure 17 is also formed at the bottom of the sample. After the force is made into a twenty-eighth, FIG. 19 shows the structure of FIG. 18 after depositing a trench filled between the sidewalls of the first and fourth sides and filling the cavity with the oceanic gate layer. Figure 20 shows the structure in which planarization is performed to remove excess second 19 . Figure 〖After the moving pole material Figure 21 shows the removal of the sidewall spacer and 2. The structure. Figure 1 is a diagram showing the structure of Figure 21 after depositing a dielectric layer and depositing a control layer on the floating gate. Figure 23 shows a flow chart of the process described in Figures 17-22. Figure 24 shows a cross section of a NAND flash memory array in an early stage of fabrication and having a pattern-formed portion for the mask portion of the floating interrogation layer in accordance with another embodiment of the present invention. Figure 25 shows the structure of Figure 24 after oxidation of the exposed floating gate layer and the mask portion. Figure 26 shows the structure of Figure 25 after the sidewall spacers are formed from the oxide layer and the sidewall spacers are used to form the STI trenches. Figure 27 shows the structure of Figure 26 after removal of the sidewall spacers and mask portions and filling the trenches. Figure 28 shows the structure of the diagram after depositing the dielectric layer and the control gate layer. [Main component symbol description] Figure 29 shows a flow chart of the process described in Figures 24 to 27. 3 Recall system 123977.doc -34- 100 200820428 110 Cell array 130 bit line decoding and driving circuit 135, 195 control and status signal line 140 line 145 line 150 line 160 bus bar 170 line 180 controller 190 word line decoding and driving circuit 210a, 210b, 210c 210d ST1 structure 220a, 220b, 220c memory cell string 230a, 230b, 230n, 230x, 230y floating gate 231 lower floating gate portion 232 upper floating gate portion 233 surface 240a, 240b, 240c source/drain Area 250a, 250b, 250c word line 301 mask layer 303 upper surface 305 substrate 307a, 307b, 307c photoresist portion 409a ' 409b, 409c mask portion 123977.doc -35 - 200820428 411 515a , 515b , 515c 519 519a , 519b , 519c 521a, 521b, 521c 523a, 523b, 523c, 523d, 523e, 523f 617 I 725a, 725b 827a, 827b, 827c, 827d 829a, 829b, 829c, 829d, 829e > 829f 831a, 831b, 831c 933 933a, 933b, 933c 1135 1 ^ 1137 1471 1473 1675 1677 1679 1701a, 1701b, 1701c, 1701d ruthenium dioxide remaining substrate portion first conductive layer first conductive portion mask portion sidewall spacer Chip gate dielectric layer dielectric portion mask portion sidewall spacer trench second conductive layer second conductive portion dielectric layer control gate layer upper floating gate portion word line one lower portion floating gate portion upper floating gate portion Floating gate ST1 structure 123977.doc -36- 200820428 1703a, 1703b, 1703c Gate dielectric portion 1705a, 1705b, 1705c First conductive portion 1807a, 1807b, 1807c, sidewall spacers 1807d, 1807e, 1807f 1809a, 1809b, 1809c Slot 1811a, 1811b, 1811c cavity 1913 second conductive layer 1913a, 1913b, 1913c second conductive portion 2215 dielectric layer 2217 control gate layer 2219 control gate layer portion 2400 substrate 2402 gate dielectric layer 2404 conductive layer 2404a , 2404b, 2404c conductive portion 2406a, 2406b, 2406c mask portion 2408a, 2408b, 2408c vertical protrusion 2510 dioxo矽 layer 2510a, 2510b, 2510c, sidewall spacers 2510d, 2510e, 2510f 2612a, 2612b trench 2716a, 2716b STI structure 2818 dielectric layer 2820 control gate layer 123977.doc -37-

Claims (1)

200820428 X. Patent Application Range: 1. A method for forming an array of non-volatile memory cells on a surface of a semiconductor substrate, comprising: forming a plurality of shallow trench isolation structures extending in a first direction Forming a plurality of first conductive portions extending in the first direction; forming a groove on one of the first conductive portions, the groove being in a second direction perpendicular to the first direction No. - the conductive portion is narrow; ... forming a second conductive portion in the groove, the second conductive portion is in electrical contact with the first conductive portion; and by etching the first conductive portion and the second conductive portion A plurality of floating gates are formed. The method of claim 1, wherein the width of the slot in the second direction is less than a minimum feature size for defining a lithography process of the memory array component. The method of claim 1, further comprising forming a dielectric layer and a control gate layer on the first conductive portion and the first conductive portion. The method of claim 3, wherein the self-aligned word lines of the individual floating gates are formed by the control gate layer by the etching. 5. The method of claim 1, wherein the plurality of first conductive portions are self-aligned to the plurality of shallow trench isolation structures. The method of claim 5, wherein the trench is formed by sidewall spacers on sidewalls of the plurality of shallow trench isolation structures. A method of forming an array of non-volatile memory 123977.doc 200820428 body elements on a semiconductor substrate having a surface, the method comprising: forming an extension in a first direction and a second direction perpendicular to the first direction Separating a plurality of shallow trench isolation structures separated by a plurality of first conductive portions; forming an exposed sidewall along the plurality of shallow trench isolation structures a plurality of sidewall spacers extending in the first direction, the plurality of sidewall spacers covering the first conductive portion; Forming a plurality of second conductive portions defined by the plurality of sidewall spacers and contacting the first conductive portions; and subsequently removing the plurality of sidewall spacers, thereby exposing the plurality of first conductive portions and the The surface of the plurality of second conductive portions. 8. The method of claim 7, wherein the first conductive portions are formed by a first conductive layer, and the first conductive layer is divided into the plurality of first conductive portions by forming the plurality of shallow trench isolation structures. The plurality of first conductive portions are self-aligned to the shallow trench isolation structure. 9. The method of claim 7, wherein the individual portions of the plurality of second conductive portions have a dimension in the second direction that is less than a size of a minimum feature size for patterning a lithography process of the array. 10. The method of claim 7, further comprising the exposed surfaces of the plurality of first conductive portions and the plurality of second conductive portions: a dielectric layer and a control gate layer. ^11. The method of claim 1, wherein the word line and the forming of the individual floating gates by the plurality of segments further comprise forming a conductive portion and the plurality of second conductive portions from the _ gate layer, such that the word line Align the floating gate. 123977.doc 200820428 12. 13. The method of claim 11 is extended in the middle and spaced apart on the first side of the substrate in the direction of the second direction. A method of forming a memory array, comprising: forming a conductive floating gate layer; forming a plurality of mask portions on the movable idle layer, the: extending in a first direction and in a second direction Separate the two-parts to remove the portion of the floating gate layer exposed by the plurality of mask portions, 哕箄 " ^ 1 knife. The removed portion extends to a depth of a thickness of the oceanic gate layer; subsequently forming a plurality of sidewall spacers extending in the first direction on the exposed surface of the floating closed layer; And performing a second etching to form a plurality of trenches in the substrate, wherein the individual trenches of the plurality of trenches extend in the first direction, and have a The width of the plurality of sidewall spacers. 14. The method of claim 3, wherein the second (four) divides the floating gate layer into a plurality of individual conductive materials, and the plurality of conductive portions and the plurality of trenches extend in a first direction. A: The method of claim 14, further comprising forming a plurality of word lines extending in a second direction perpendicular to the first direction. 16. The method of claim 5 wherein the plurality of word lines are formed by a -to-step process, and the (four) step of dividing the plurality of conductive portions into a plurality of independent floating gates. The method of claim 13, wherein the plurality of sidewall spacers are formed by oxidizing the floating gate layer of 123977.doc 200820428. 18. The method of claim 17, wherein the plurality of mask portions are also subjected to the oxidization. The method of claim 13, wherein the plurality of sidewall spacers are formed by depositing a dielectric. 20. A non-volatile memory array on a substrate, comprising: a plurality of memory cell strings extending in a first direction and separated in a second direction perpendicular to the first direction; the plurality of strings - individual strings comprising series connected in the first direction a plurality of memory cells together, one of the plurality of memory cells having a floating gate; and the floating gate having an inverted zigzag cross section along the second direction. 2 1 · The non-volatile memory array of claim 20, which has a 々----, Τ 浮动 浮 浮 浮动 浮动 浮动 浮动 浮动 浮动 浮动 浮动 + + + + + + + + + + + + + + + + + + The 〇丨 portion and one have a portion smaller than the first width in the direction of the Θ. The upper portion of the second width 22. The non-volatile memory array of claim 21, where 兮> ^ is less than the minimum feature size of the lithography process used. The non-volatile memory array of claim 22, wherein the minimum feature size of the lithography process used is. a first upper portion and a non-volatile memory array not having the upper portion and the second portion, wherein the lower portion meets along a plane, and the upper portion of the lower portion is covered along the plane surface. 25. The non-volatile memory array of claim 24, wherein 123977.doc 200820428 the lower portion is formed separately. The upper portion is aligned with the lower portion from the non-volatile memory array of claim 25. 27. The non-volatile memory array of claim 20, further comprising a shallow trench isolation structure extending in a first direction. /匕3 in the non-volatile memory array on a substrate, comprising: a plurality of memory cell strings, one string comprising a plurality of memory cells connected along a first-square port, Each of the plurality of cells includes a floating gate covering a channel; the individual shallow trenches separate a plurality of shallow trench isolation structures of adjacent strings, and the isolation structure extends into the substrate; a plurality of word lines extending in a second direction perpendicular to the first direction, a different word line covering the plurality of, a pre-active gate; and W a floating gate having a parallel to the substrate A lower portion of the surface extending forward and an L portion projecting from an intermediate portion of the lower portion, the upper portion being narrower than the lower portion in the second direction. ^ Q. 29. The non-volatile memory array of claim 28, wherein the upper portion eight is aligned with the lower portion. 77 Stomach 30. The non-volatile memory array of claim 28, wherein the lower portion 八 is aligned with a neighbor of the plurality of shallow trench isolation structures. 31. The non-volatile memory array of claim 28, further comprising a dielectric layer between the individual floating gate and a word line, the layer 123977.doc 200820428 directly covering the upper portion And the lower part. 32. The non-volatile memory array of claim 28, wherein the shallow trench isolation structure has a width in the second direction that is less than a minimum feature size of the lithography process used. 123977.doc