JP2000049243A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a flash memory with a small cell array area, in which an offset region can be formed with good controllability and writing can be executed uniformly and speedily and data access is not delayed and to provide the manufacture method. SOLUTION: FG and a resist pattern 4 are set to be masks and ions are obliquely implanted. Thus, n+ regions 5 having offset regions 5a are formed. A CVD oxide film whose etching rate is fast with respect to HF fluid is used, and a sidewall film 9 is formed around FG. Then, dry oxidation is executed, and a thermal oxidation film 10 is formed. The sidewall film 9 is removed by HF fluid and the sidewall 11 of a poly-poly insulating film is formed on the sidewall of FG.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a structure of a flash memory such as an EEPROM and a method of manufacturing the same.

[0002]

2. Description of the Related Art In general, a batch erasing type EEPROM memory called a flash memory applies an insulating film by applying a voltage to a control gate (hereinafter referred to as CG) and applying a desired voltage to each of a drain, a source and a well. Data is stored by accumulating or discharging electrons in a floating gate (hereinafter, referred to as FG) made of a polysilicon film surrounded by.

For example, in a NOR type flash memory, electrons are injected and extracted, and the presence or absence of electrons is checked under application conditions as shown in Table 1 below. These operations are generally called data writing, erasing, and reading. Writing is performed by injection of channel hot electrons (hereinafter referred to as CHE) from the drain, and erasing is performed by FN (Fowler-Nordheim) tunneling at the source edge.

[0004]

[Table 1]

In Table 1, V _CG is a CG voltage, V _D
The drain voltage, V _S is the source voltage, V _well is well voltage.

In recent years, with the miniaturization of memory cells, when the length of the stack gate composed of CG and FG is reduced, the short channel effect is increased, and it has become difficult to increase the efficiency of CHE. To solve this, CH
In order to increase the efficiency of E, increase the amount of electrons injected per unit time and increase the writing speed even in the same voltage arrangement as in Table 1 above, for example, Japanese Patent Application Laid-Open No. 7-297299 discloses an offset structure. Is disclosed.

A flash memory having a virtual ground line structure in which both writing and erasing are performed by FN tunneling has been proposed. In this case, one diffusion layer can serve as either a drain or a source depending on how the potential is applied, and the area of the memory cell can be reduced.

FIGS. 4 to 7 are process diagrams showing a conventional flash memory manufacturing method. In each figure, (a) is a plan view, (b) is a cross-sectional view in the word line direction along bb ′ in the plan view (a), and (c) is cc in the plan view (a). FIG. 3 is a cross-sectional view in the bit line direction along the line ′.
The description will be made sequentially according to the drawings.

First, as shown in FIG. 4, a thin silicon oxide film called a tunnel oxide film 2 having a thickness of, for example, 110 angstroms and a polysilicon film 3 doped with phosphorus are formed on a silicon substrate 1 in which wells are formed. The resist patterns 4 are sequentially formed and, for example, L / S = 0.
By patterning at 4 / 0.4 μm, FG composed of tunnel oxide film 2 and polysilicon film 3 is formed. Also, L
Is an abbreviation of Line, a portion remaining after patterning, and S is Sp
ace indicates a portion that disappears after patterning.

Thereafter, while the resist pattern 4 is left, for example, arsenic ions or the like are obliquely ion-implanted at an angle of 7 ° with respect to the vertical surface of the silicon substrate 1 so that, for example, on one side of the FG, An n ⁺ region 5 which is a diffusion layer which is offset by about 0.1 μm and overlaps on the other side by about 0.1 μm is formed.

Next, as shown in FIG. 5, after removing the resist pattern 4, a silicon oxide film 6 formed on the entire surface by CVD is deposited, and the entire surface is etched until the polysilicon film 3 is exposed. Each cell is separated by embedding the oxide film 6 between the FGs.

Next, as shown in FIG. 6, a poly-poly insulating film 7 made of a silicon oxide film and a silicon nitride film is formed on the entire surface.
And WSi / polySi = 1000/1000
A film 8 of Angstrom is formed. After that, a resist is applied and photolithography is performed to make the resist pattern 4 to L / S = 0.3 / 0.3 μm.
a is formed.

Thereafter, as shown in FIG. 7, etching is performed using the resist pattern 4a as a mask to complete a memory cell. At this time, the FG of the completed memory cell
Table 2 below shows voltage application conditions when (2) performs writing, erasing, and reading. In Table 2, electrons are injected and extracted by FN tunneling by applying a high voltage to the tunnel oxide film 2. Also, n ⁺ region 5
N ⁺ (1) acts as a source for FG (1) and acts as a drain for FG (2).

[0014]

[Table 2]

[0015]

The conventional method of manufacturing a flash memory is as described above. In a fine memory cell, since the offset region is formed only by ion implantation, the variation in the angle due to the implantation machine, There has been a problem that an offset region cannot be formed uniformly in any memory cell due to variations in the thickness of a resist or FG used as a mask during ion implantation.

Further, if the offset amount is too large, the current flowing at the time of reading data becomes small, and reading becomes slow. That is, there is a problem that data access is slow.

Further, since the poly-poly film is only on the FG, the capacitance between the CG and the FG / the capacitance between the FG and the substrate (= coupling) is reduced, and the voltage applied between the FG-n ⁺ region or the FG and the substrate is reduced. As a result, the FN tunnel current is small, and there is a problem that writing and erasing are slow.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. An offset area can be formed with good control, writing can be performed uniformly and quickly, and data access can be performed without delay. It is an object of the present invention to provide a flash memory having a small area and a manufacturing method thereof.

[0019]

According to a first aspect of the present invention, there is provided a semiconductor device including a thick oxide film on a diffusion layer and a thin oxide film on an offset portion. Is provided with an insulating film, and the other portion on the thin oxide film is provided with a conductive film serving as a control gate. When a potential is applied to the control gate, the lower portion of the conductive film on the thin oxide film becomes a first channel. In the layer, the lower portion of the insulating film on the side wall of the floating gate does not function as the channel layer or the diffusion layer, and the lower portion of the gate electrode serves as the second channel layer.

According to a second aspect of the present invention, in a method of manufacturing a semiconductor device, a channel layer is formed in an offset portion to control a region of the offset portion that does not function as the channel layer or the diffusion layer. It was done.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device, the step of forming the channel layer in the offset portion includes forming the diffusion layer having the overlap portion overlapping the floating gate and the offset portion separated from the floating gate. After the step of forming, H
A step of forming a first sidewall of a film having a high etch rate with respect to the F solution, a step of forming a thermal oxide film for cell isolation by dry oxidation between the floating gates, HF sidewall
Removing with a liquid; and forming a second sidewall of a poly-poly insulating film composed of two layers of a silicon oxide film, silicon and a nitride film on the floating gate side wall. It is.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 1 to 3 are process diagrams showing a method for manufacturing a flash memory according to the present invention. In each figure, (a) is a plan view, (b) is a cross-sectional view in the word line direction along bb ′ in the plan view (a), and (c) is cc in the plan view (a). FIG. 3 is a cross-sectional view in the bit line direction along the line ′. The description will be made sequentially according to the drawings.

First, as shown in FIG. 1, a thin silicon oxide film called a tunnel oxide film 2 having a thickness of, for example, 110 angstroms and a polysilicon doped at a phosphorus concentration of 1E20 cm ^-3 are formed on a silicon substrate 1 having wells formed thereon. A silicon film 3, a silicon oxide film 7a, and a silicon nitride film 7b are sequentially formed. At this time, etching is performed according to the finished film thickness so that the total film thickness of the silicon oxide film 7a and the silicon nitride film 7b becomes the same as the film thickness of the poly-poly insulating film 7 formed on the sidewall of the FG later. It is formed in consideration of the margin for the film reduction due to the above.

Thereafter, using the resist pattern 4, patterning is performed, for example, at L / S = 0.4 / 0.4 μm to form an FG composed of the tunnel oxide film 2 and the polysilicon film 3. Here, L is an abbreviation of Line, a portion remaining after patterning, and S is an abbreviation of Space, a portion that disappears after patterning.

Further, by using the resist pattern 4 as a mask and implanting arsenic ions or the like obliquely at a concentration of about 3E15 cm ⁻² , for example, one side of the FG has an offset region 5 a and the other side has An n ⁺ region 5 having a wrap region 5b is formed. At this time, the offset region 5a may have a variation in angle due to the implantation machine, a resist or FG as a mask at the time of ion implantation.
In consideration of the variation in the film thickness, a large value is formed with a margin for the dimension of the design value.

Next, as shown in FIG. 2, after the resist pattern 4 is removed, a CVD oxide film is deposited by, for example, about 1000 angstroms, and then anisotropically etched so as to have a width of about 0.1 μm around the FG. Is formed. At this time, the CVD oxide film is NSG
A film having a high etching rate with respect to the HF solution, such as a film or a low-pressure CVD oxide film, is used.

Thereafter, dry oxidation containing no moisture is performed at 900 ° C., and the difference in silicon oxidation rate depending on the presence or absence of ion implantation indicates that ¹⁺
The thermal oxide film 10 is formed to be as thick as about 000 to 1200 angstroms and as thin as about 250 angstroms on the offset region 5a. At this time, the side wall of the FG is not oxidized because the side wall film 9 exists.

Next, as shown in FIG. 3, the side wall film 9 is removed with an HF solution. At this time, since the side wall film 9 is a film having a high etching rate with respect to the HF solution, the thin thermal oxide film 1 on the offset region 5a is formed.
0 does not disappear. Thereafter, a poly-poly insulating film composed of a silicon oxide film 7a and a silicon nitride film 7b is formed on the entire surface, for example, to a total thickness of about 200 Å, and then anisotropically etched to form a side of the poly-poly insulating film on the side wall of the FG. The wall 11 is formed.

Then, WSi / polySi = 1000
/ 1000 angstroms, and a film 8 is formed.
The memory cell is completed by patterning to /S=0.3/0.3 μm. This WSi / polySi film 8 is made of CG
Work as

In the flash memory thus manufactured, the WSi / polySi film 8 is formed on the thin thermal oxide film 10 in the portion of the offset region 5a where the side wall 11 of the poly-poly insulating film on the FG side is not formed. And a general gate structure.

Therefore, when a voltage is applied to the CG, the lower part of the side wall 11 of the poly-poly insulating film on the FG side wall in the offset region 5a becomes an offset region 12 which is neither a channel layer nor a diffusion layer, and A channel layer 13 is formed below a portion of the poly insulating film where the sidewalls 11 are not formed. That is, n ⁺
Between the regions 5, the first channel layer 13, the offset region 1
2, a structure in which the second channel layer 14 is arranged in this order.

Thus, even if the length of the offset region 5a formed by ion implantation varies, the FG
Since the thickness of the side wall 11 of the poly-poly insulating film on the side wall can be formed with good control, the actual length of the offset region 12 can be formed with good control, and the offset region 12 is formed uniformly without variation depending on the cell. be able to.

In the flash memory shown in FIG.
When a voltage is applied to (2a) as shown in Table 3 below, it works so that electrons are injected by CHE and electrons are extracted by FN tunneling.

[0034]

[Table 3]

In this case, by forming the offset region 12, the generation efficiency of CHE can be increased, the writing speed can be increased, and the length of the offset region 12 can always be made constant, so that the generation amount of CHE can be reduced. The writing speed can be made constant and the writing speed can be made constant as designed. Furthermore, at the time of reading, n ⁺ (2
a) functions as a drain, and the offset region 5a becomes the offset region 12 and the first channel layer 13. Therefore, the drain resistance does not increase and the read current does not decrease. That is, the data access speed can always be made constant as designed.

Embodiment 2 In the first embodiment, FIG.
In the flash memory shown in FIG.
In the above, a case has been described in which electron extraction is performed by FN tunneling. Here, in the flash memory shown in FIG. 3, electron injection and electron injection are performed by applying a potential to FG (2a) as shown in Table 4 below. A case in which both of the drawing and the drawing are performed by FN tunneling will be described.

[0037]

[Table 4]

In this case, the length of the offset region 12 is uniformly formed by the thickness of the side wall 11 of the poly-poly insulating film on the side wall of the FG in the n ⁺ (2a) serving as a source for the FG (2a) during reading. Therefore, the readout current can be made constant as designed and the access speed can be made constant.

Further, by surrounding the periphery of the FG with a poly-poly insulating film, the capacitance between the CG and the FG can be increased, and the FN tunnel current increases. Therefore, writing,
Erasure can be made faster.

[0040]

As described above, according to the present invention, a thick oxide film is provided on a diffusion layer, and a thin oxide film is provided on an offset portion.
An insulating film is provided on a side wall portion of the floating gate on the thin oxide film, and a conductive film serving as a control gate is provided on other portions on the thin oxide film. By applying a potential to the control gate, the thin oxide film is formed. The lower part of the conductive film on the film becomes the first channel layer, the lower part of the insulating film on the side wall of the floating gate becomes an offset region which does not function as the channel layer or the diffusion layer, and the lower part of the gate electrode becomes the second channel layer. As a result, the offset region can be controlled by the first channel layer, and the resistance between the diffusion layers does not increase. When writing with channel hot electrons,
It is possible to increase the generation efficiency of channel hot electrons and obtain a flash memory capable of keeping the writing speed fast and constant. Furthermore, since the resistance between the source and the drain does not increase, a flash memory in which the read current does not decrease, the access speed is constant, and does not decrease can be obtained.

Further, by forming a channel layer in the offset portion, a region of the offset portion that does not function as the channel layer or the diffusion layer is controlled. Therefore, when writing by channel hot electrons, The writing speed can be made constant. At the time of reading, the data access speed can be made constant.

In the step of forming a channel layer in the offset portion, after the step of forming a diffusion layer having an overlap portion overlapping with the floating gate and the offset portion separated from the floating gate, an HF solution is formed on the side wall of the floating gate. Forming a first sidewall of a film having a high etch rate, forming a thermal oxide film for cell isolation between the floating gates by dry oxidation, and forming the first side wall between the floating gates. A step of removing the wall with an HF solution, and a step of forming, on the side wall of the floating gate, a second sidewall of a poly-poly insulating film composed of two layers of a silicon oxide film, silicon and a nitride film. Therefore, the offset portion formed first by the second sidewall film thickness of the poly-poly insulating film is located. Of can be controlled in the offset region, it is possible to form a non-desired offset region in the channel layer. Further, by surrounding the floating gate with a poly-poly insulating film, the capacitance between CG and FG can be increased, and the FN tunnel current can be increased. Therefore, writing and erasing by FN tunneling can be sped up.

[Brief description of the drawings]

FIG. 1 is a process chart showing a method for manufacturing a flash memory according to the present invention.

FIG. 2 is a process chart showing a method for manufacturing a flash memory according to the present invention.

FIG. 3 is a process chart showing a method for manufacturing a flash memory according to the present invention.

FIG. 4 is a process chart showing a conventional flash memory manufacturing method.

FIG. 5 is a process diagram showing a conventional flash memory manufacturing method.

FIG. 6 is a process chart showing a conventional flash memory manufacturing method.

FIG. 7 is a process chart showing a conventional flash memory manufacturing method.

[Description of Signs] 1 Silicon substrate, 3,8 polysilicon film, 5 n ⁺
Region, 5a, 12 offset region, 5b overlap region, 7a silicon oxide film, 7b silicon nitride film, 9 sidewall of CVD oxide film, 10 thermal oxide film, 11 sidewall of poly-poly insulating film, 13
First channel layer, 14 Second channel layer.

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 5F001 AA25 AA43 AB03 AB09 AC02 AC06 AD12 AD15 AD21 AD41 AD61 AD62 AE02 AE03 AE08 AG02 AG10 AG21 AG32 5F083 EP02 EP24 EP27 EP54 EP65 EP77 ER02 ER05 ER09 ER14 ER16 ER22 GA03 PR12 PR21

Claims (3)

[Claims] A gate electrode comprising a floating gate and a control gate; and a diffusion layer on both sides of the gate electrode. One of the diffusion layers has an overlap portion overlapping the gate electrode, and the other has an overlap portion. In a semiconductor device having an offset portion separated from the gate electrode and forming a channel layer below the gate electrode between the diffusion layers by applying a potential to the gate electrode, a thick oxide film on the diffusion layer, the offset A thin oxide film on the thin oxide film, an insulating film on the floating gate sidewall on the thin oxide film, and a conductive film serving as the control gate on the other portion on the thin oxide film. By applying a potential to the gate, the lower portion of the conductive film on the thin oxide film is connected to the first channel layer by the floating layer. The offset region does not function as the diffusion layer also insulating film under the Gugeto sidewall portions as the channel layer, a semiconductor device, characterized in that the gate electrode lower part was set to the second channel layer. 2. A gate electrode comprising a floating gate and a control gate, and a diffusion layer on both sides of the gate electrode. One of the diffusion layers has an overlap portion overlapping the gate electrode, and the other has an overlap portion. A semiconductor device having an offset portion separated from the gate electrode and forming a channel layer below the gate electrode between the diffusion layers by applying a potential to the gate electrode, wherein a floating gate is formed on a substrate A step of forming a diffusion layer having an overlapping portion overlapping with the floating gate and an offset portion separated from the floating gate; anda step of forming a control gate on the floating gate. By forming a channel layer in the offset portion, the offset The method of manufacturing also semiconductor device is characterized in that so as to control the offset region does not function as the diffusion layer as the channel layer. 3. The step of forming a channel layer in the offset portion includes forming a diffusion layer having an overlap portion overlapping with the floating gate and the offset portion separated from the floating gate.
Forming a first sidewall of a film having a high etch rate with respect to an HF solution, forming a thermal oxide film for cell isolation between the floating gates by performing dry oxidation; HF sidewall
Removing by a liquid; and forming a second sidewall of a poly-poly insulating film composed of two layers of a silicon oxide film, silicon and a nitride film on the side wall of the floating gate. 3. The method for manufacturing a semiconductor device according to claim 2, wherein: