WO2008029956A1 - Semiconductor integrated circuit device, and wire forming method - Google Patents

Semiconductor integrated circuit device, and wire forming method Download PDF

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Publication number
WO2008029956A1
WO2008029956A1 PCT/JP2007/067778 JP2007067778W WO2008029956A1 WO 2008029956 A1 WO2008029956 A1 WO 2008029956A1 JP 2007067778 W JP2007067778 W JP 2007067778W WO 2008029956 A1 WO2008029956 A1 WO 2008029956A1
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WO
WIPO (PCT)
Prior art keywords
wiring
forming
film
copper
insulating film
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PCT/JP2007/067778
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French (fr)
Japanese (ja)
Inventor
Takenobu Yoshino
Nobuhiro Hata
Jun Kawahara
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National Institute Of Advanced Industrial Science And Technology
Nec Corporation
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Priority to JP2008533223A priority Critical patent/JP5299901B2/en
Publication of WO2008029956A1 publication Critical patent/WO2008029956A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844—Bottomless liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor integrated circuit device capable of suppressing a leakage current between wirings, which is a problem when using fine wiring containing copper, and a wiring forming method for realizing wiring of the semiconductor integrated circuit device. . Background art
  • Copper wiring or wiring using a conductor layer containing copper is often used in recent ultra-LS I semiconductor devices because of its low resistivity and excellent resistance to electromigration. This low wiring resistance and high migration resistance are reflected in the realization of high-speed operation.
  • the wiring is filled with an insulating film having a low dielectric constant for higher speed operation, and a combination of a copper wiring and a low dielectric constant film such as porous silica is widely used.
  • tetramethylcyclotetrasiloxane and 6-membered ring vinylsiloxane are known as raw materials for forming such a wiring interlayer insulating film.
  • TMCTS ⁇ tramethylcyclotetrasiloxane
  • BPSG borophosphosilicate glass
  • PSG phosphosilicate gate glass
  • TMCTS is the next generation with Limethyl Phosphite (TMP) and Trimethyl Bora (TMB) Used for BPSG and PSG films.
  • Patent Document 1 Japanese Laid-Open Patent Publication No. 2 00 2-3 3 4 8 7 2 discloses an organic-inorganic hybrid film having a main chain in which a part made of siloxane and a part made of an organic molecule are alternately bonded. Is used to prevent copper, which is a wiring material, from diffusing into the interlayer insulating film.
  • This technology uses the appearance of barrier properties by the mechanism that copper ions are trapped in the siloxane part due to the magnitude of the interaction between copper ions and siloxane or organic molecules.
  • the organic molecules play the role of connecting the siloxanes, which has the effect of being reduced in density by the organic molecules.
  • the siloxane portion and the copper are spatially separated and shielded by increasing the potential required for diffusion to prevent copper ionization. With this, barrier properties are developed. Since cyclic siloxane is used, it is not necessary to connect the siloxanes with organic molecules as described above, and the low density is still maintained.
  • Patent Document 2 Japanese Patent Laid-Open No. 2 0 0 5-4 5 0 5 8) describes S i R 1 x R 2 y R 3 z R 4 4 _ (x + y + Z ) (silane This is an insulating film made of gas, and any one of R 1 ⁇ R 4 has a ⁇ electron (that is, has a double bond or triple bond). Since the silicon compound obtained by decomposing or reacting this gas has a copper ion diffusion barrier property, this barrier property is used.
  • Patent Document 2 is different from the present invention in that it includes a silane derivative having negative electrons.
  • the inventors of the present invention By controlling the molecular weight of the organic side chain of the siloxane moiety, the inventors of the present invention It was discovered that the silica skeleton and copper can be spatially separated to suppress copper ionization, and as a result, a function to suppress copper ion drift can be added to the insulating film itself.
  • the present invention is capable of suppressing the problem of deterioration of insulation characteristics between wirings caused by diffusion of copper atoms (or ions) in an insulating film between wirings, and wiring of the semiconductor integrated circuit device.
  • An object of the present invention is to provide a wiring forming method for realizing the above. Disclosure of the invention
  • the present invention is a semiconductor integrated circuit device formed on a semiconductor substrate, comprising: a wiring formed from a conductive layer containing copper; and an insulating film provided between the wirings, wherein the insulating film is
  • This is an insulating film that contains 3 IP 3 V-cyclosiloxane film that is exposed at the same time as at least a part of the wiring layer in the middle of the manufacturing process, and suppresses the diffusion of copper that occurs between the wirings in the thermal process of the manufacturing process.
  • the above 3 IP 3 V-cyclosiloxane film is provided to improve the reliability of high-density integrated circuits.
  • the reliability can be further improved by contacting the wiring and the 3 I P 3 V-cyclosiloxane film through a barrier metal.
  • the wiring structure of such a semiconductor device includes a step of forming a wiring / turn groove in an insulating layer having a 3 IP 3 V-cyclosiloxane film on a flat semiconductor substrate, and a conductive ⁇ layer containing a copper component.
  • a damascene process or an etch back process removing the conductive layer in a portion other than the groove, and exposing the 3 IP 3 V-cyclosiloxane film, and An insulating film can be formed on the surface, and a wiring process including:
  • the conductive layer containing a copper component includes a conductive layer in which a metal layer containing a copper component is formed on a barrier metal layer.
  • the wiring of the semiconductor integrated circuit device includes a step of forming a conductive layer containing a copper component on an insulating film on a flat semiconductor substrate, a step of patterning the conductive layer to form a wiring, and 3 It can be formed by a forming method including: a step of forming an IP 3 V-cyclosiloxane film at least between wirings; and a step of forming another insulating film on the surface.
  • the wiring of the semiconductor integrated circuit device includes a step of forming a conductive layer containing a copper component on an insulating film on a flat semiconductor substrate, a step of patterning the conductive layer, and forming a wiring. Forming a barrier metal layer on at least the side wall of the wiring, forming a 3 IP 3 V-cyclosiloxane film at least between the wirings, and forming another insulating film on the surface. Can be formed. Brief Description of Drawings
  • Figures 1 (a), (b), (c), (d), and (e) show the manufacturing process of a semiconductor integrated circuit device.
  • FIG. 2 is an example of a cross-sectional view for explaining an integrated circuit to which the present invention is applied.
  • Figures 4 (a) and 4 (b) are diagrams showing the measurement results of the cumulative failure rate of the M IS structure element.
  • FIG. 5 is a schematic diagram showing a cross-sectional structure of a measurement sample for measuring the MTF characteristic of an MIS structure element.
  • Figures 6 (a), (b), and (c) show the measurement results for the flat band shift.
  • FIG. 7 is a diagram showing the measurement results of the MTF characteristics of the MIS structure element.
  • FIG. 8 is a graph showing the measurement results of the film thickness dependence of the MTF characteristics of the MIS structure element.
  • the inventors of the present invention control the molecular weight of the organic side chain of the siloxane part to spatially shield between the silica skeleton and copper, thereby suppressing the ionization of copper.
  • 3 IP 3 V-cyclosiloxane with isopropyl group (IP) and vinyl group (V) from each silicon does not allow copper ions to penetrate into the film.
  • MS Q methylsilsesquioxane having a methyl group as an organic side chain and S i OC (DMDMOS:
  • 3 IP 3 V-cyclosiloxane has a barrier property.
  • 3 IP 3 V-cyclosiloxane has a lifetime that is almost an order of magnitude longer than that of SioC under the same measurement conditions.
  • the electric field drift of copper ions into the 3 IP 3 V-cyclosiloxane film is suppressed. This is because the vinyl group and isopropyl group contained in 3 I P3V-cyclosiloxane are the copper part contained in the electrode and the silica part contained in the film structure. This is thought to be because copper ionization is suppressed by spatially or electrically shielding the copper. Electrical shielding is surplus electrons generated by double and triple bonds
  • Fig. 6 (a) shows the measurement results of the flat band shift of the 3 I P 3 V-cyclosiloxane (OC S) M I S structure with a Cu electrode.
  • the MOS capacitor used for the measurement is CuZOCS (200 nm) i O 2 (30 nm) S i M
  • Fig. 7 shows the applied electric field dependence of the mean time (MTF) required for a measurement sample having the cross-sectional structure shown in Fig. 5 to reach dielectric breakdown.
  • Po-S i 0 2 is porous (polyporous) silicon oxide film (1 38 nm)
  • OCS is 3 IP 3 V—cyclosiloxane (0 to 800)
  • B CB is benzocyclopolymerized in plasma Butene (benzocyclobutene).
  • the thickness of the silicon thermal oxide film is 30 nm.
  • FIG. 8 is a graph showing the dependence of MTF on the film thickness of the measurement sample having the structure of FIG.
  • an in-plane wiring that does not require a barrier metal It can be used to reinforce weak spots due to the formation of pinholes and pinholes generated in ultrathin barrier metals.
  • CMP Chemical Mechanical Polishing
  • It can also be used as a stopper layer for anisotropic etching processes, and can also be used as a diffusion barrier for diffusion channels formed at the interface with an insulating film formed when an insulating film is formed. .
  • a stubber layer there is no necessity to use the insulating film having the steel ion drift function described above, and a layer that exhibits good selectivity in CMP or anisotropic etching process is used. It is obvious that the insulating film having the copper ion drift function may be provided in the lower layer.
  • the insulating film used in the present invention can also be used as a copper ion diffusion barrier on the wiring or at the CMP interface.
  • Si CN having a diffusion barrier property is often used for this part, but in the present invention, by using an insulating film having a diffusion barrier property of a low dielectric constant film, the capacitance between wirings can be reduced. It is possible to reduce the copper ion drift at the interface with the heterogeneous film.
  • FIG. 1 is a cross-sectional view illustrating an integrated circuit to which the present invention is applied.
  • Fig. 1 shows a wiring structure that blocks the diffusion of copper ions in the lateral direction by providing a side wall that has barrier properties in parallel with the side wall of the barrier metal, and shows a part of the manufacturing process.
  • a simple wiring structure is used, but it is apparent that the present invention can be applied to a more complicated wiring structure.
  • a transistor layer 2 is formed on a semiconductor substrate 1, and a silicon nitride film (film thickness 20-30 nm) is formed as an etching stopper layer 3 by a CVD (chemical vapor deposition) process.
  • An interlayer insulating film 4 film thickness: 100 to 150 nm
  • a low dielectric constant cap layer 5 film thickness of about 20 nm
  • the film is formed by a process, and a film 20 (film thickness of 30 nm or less) such as a 3 I P3V-cyclosiloxane film or BCB film having a copper ion barrier property is laminated, and anisotropic etching is performed to form a sidewall.
  • a film 20 film thickness of 30 nm or less
  • a film 20 film thickness of 30 nm or less
  • anisotropic etching is performed to form a sidewall.
  • a barrier metal layer 6 (thickness of 10 nm or less) is further laminated, and anisotropic etching is performed to form sidewalls. As a result, a side wall is formed in which the barrier film and the copper ion barrier film are parallel to each other.
  • a wiring layer 7 containing copper is laminated, and a buried copper wiring as shown in FIG. 1 (d) is formed by a CMP process or an etching process.
  • a film 20 such as a 3 IP 3 V-cyclosiloxane film or a BCB film having a barrier property of copper ions is used for detecting the end point of the CMP process or used as a stutter layer for anisotropic etching.
  • a dielectric barrier layer 8 is provided.
  • the interlayer insulating film 21 and the plug are further shown on the assumption that the semiconductor device has a multilayer wiring having a wiring layer as an upper layer.
  • an interlayer insulating film 21 is attached, a via hole is formed by etching, and a film 11 having a barrier property is formed on the sidewall of the via hole. This can be formed in the same manner as the sidewall of the barrier metal layer 6 described above, and then the plug layer 12 is formed and embedded.
  • FIG. 2 is a cross-sectional view for explaining an integrated circuit to which the present invention is applied.
  • a simple wiring structure is used.
  • the cross-sectional structure of FIG. 2 will be described by dividing it into a semiconductor substrate 1, a transistor layer 2, and a multilayer wiring layer.
  • the transistor layer in FIG. 2 includes a diffusion layer that forms a transistor, a gate electrode, a source electrode, and a drain electrode of the transistor, electrodes that supply voltage and current to them, and an interlayer insulating film that insulates each electrode. Is arranged.
  • FIG. 3 is a diagram illustrating an example of a manufacturing process for forming a wiring layer. Copper wiring is formed by a method known as the damascene process. FIG. 3 shows an example of a single damascene, but the present invention can be similarly applied to a dual damascene. In general, a part of the semiconductor manufacturing process can be easily substituted with another manufacturing process, and in the present invention, there is no reason to limit to the following processes.
  • a transistor layer 2 is formed on a semiconductor substrate 1, and a silicon nitride film (thickness 20 to 30 nm) is formed as an etching stopper layer 3 by a CVD process.
  • a silicon nitride film thinness 20 to 30 nm
  • an etching stopper layer 3 is formed on the etching stopper layer 3, and a low dielectric constant cap layer 5 (film thickness of about 20 nm) are laminated, and a trench pattern for wiring
  • the barrier metal layer 6 (thickness of 10 nm or less) is laminated.
  • the copper wiring layer 7 is formed.
  • a CMP (Chemical Mechanical Polishing) process is used to embed the copper wiring layer in the wiring trench pattern, similar to the usual damascene process.
  • the low dielectric constant cap layer 5 is used for end point detection.
  • the copper wiring layer is a conductive layer containing copper as a main component. In this wiring process, after forming the rear metal layer 6, the copper wiring layer 7 can be formed without performing anisotropic etching, and then buried by a CMP process.
  • FIG. 3 (b) A CMP (Chemical Mechanical Polishing) process is used to embed the copper wiring layer in the wiring trench pattern, similar to the usual damascene process.
  • the low dielectric constant cap layer 5 is used for end point detection.
  • the copper wiring layer is a conductive layer containing copper as a main component.
  • the copper wiring layer 7 can be formed without performing anisotropic etching, and then buried by a CMP process.
  • the dielectric barrier layer 8, the via interlayer insulating film layer 9 (film thickness 150 to 300 nm) and the etching stopper layer 10 (film thickness 20 to 30 nm) are formed.
  • a via hole is formed by a photolithography process, and a sidewall is formed with a film 11 having a barrier property such as a 3 I P3V-cyclosiloxane film or a BCB film (film thickness of 3 O nm or less), and a plug layer 1 2 is formed. Laminated and anisotropically etched to form plugs.
  • an interlayer insulating film 13 and an etching stopper layer 14 are stacked, and a trench pattern for wiring is formed by a photolithography process, and the barrier metal layer 1 After stacking 5 (thickness 1 O nm or less), anisotropic etching is performed to form a barrier metal layer 15 (thickness 1 O nm or less) side wall.
  • FIG. 3 (e) a copper wiring layer 16 is formed next, and the copper wiring layer is buried in the wiring groove pattern by the damascene process in the same manner as described above.
  • FIG. 3 shows an example of a single damascene, but the present invention can be similarly applied to a dual damascene.
  • the thickness of the copper wiring layer varies depending on the current to be applied. In order to obtain a wiring of about 500 to 1 GOO nm after embedding, a copper wiring layer of about 1 to 3 m before the CMP process 1 6 Form.
  • FIG. 3 (f) shows a semiconductor integrated circuit device in which a low dielectric constant insulating film 17 and a protective film 18 are provided on the formed copper wiring layer 16.
  • a film in which copper ion diffusion occurs can be used as an interlayer insulating film, and the choice of a low dielectric constant film can be expanded. It can also be used as a pore seal (side wall) for ultra-low dielectric constant interlayer insulating films such as porous silica. For example, in the case where the distance between wirings is 0.6 microns, if the 30 nm film in the above example is used, 90% of the insulating film between the wirings and this ultra low dielectric constant interlayer insulating film other than the pore seal And parasitic capacitance between wires can be suppressed.
  • the insulating film that blocks the copper ions in any case is caused by a pinhole generated when a barrier metal-free wiring structure or an extremely thin / rear metal wiring structure is used. It has the effect of reinforcing the wakespot and can improve the reliability of semiconductor devices.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

Provided is a semiconductor integrated circuit device, in which a 3IP(isopropyl-radical)-3V(vinyl-radical)-cyclohexane (OCS) film (20) to appear simultaneously with a copper wiring layer (7) is used, as a film to be formed between copper wires, when the wiring layer is formed. The semiconductor integrated circuit device is characterized by using a barrier property of the OCS film against a copper ion drift. The wire is formed by forming a conductive layer containing copper over an insulating film (4), by patterning the conductive layer to form wires, by forming the OCS film at least between the wires, and by laminating another insulating film on the surface. Alternatively, the wire is formed by forming wiring pattern grooves in an insulating layer having the OCS film on the surface, by forming a conductive layer containing copper, by burying by the Damascene or etch-back method using the OCS film for a terminal detection, and by forming another insulating film on the surface.

Description

明 細 書 半導体集積回路装置と配線形成方法 技術分野  Description Semiconductor integrated circuit device and wiring formation method Technical Field
この発明は、 銅を含む微細配線を用いるときに問題となる配線間のリーク電流 を抑制することのできる半導体集積回路装置と、 その半導体集積回路装置の配線 を実現するための配線形成方法に関している。 背景技術  The present invention relates to a semiconductor integrated circuit device capable of suppressing a leakage current between wirings, which is a problem when using fine wiring containing copper, and a wiring forming method for realizing wiring of the semiconductor integrated circuit device. . Background art
銅配線あるいは銅を含む導体層を用いた配線は、 抵抗率が低く、 また、 エレク トロマイグレーション耐性に優れていることから、 最近の超 LS I半導体装置に よく用いられている。 このように配線抵抗が低く高マイグレーション耐性をもつ ていることは、 高速動作の実現に反映されている。 また、 さらに高速動作のため に配線間を低比誘電率の絶縁膜で埋めることが行なわれておリ、 銅配線とポーラ スシリカなどの低比誘電率膜との組み合わせが広く用いられている。  Copper wiring or wiring using a conductor layer containing copper is often used in recent ultra-LS I semiconductor devices because of its low resistivity and excellent resistance to electromigration. This low wiring resistance and high migration resistance are reflected in the realization of high-speed operation. In addition, the wiring is filled with an insulating film having a low dielectric constant for higher speed operation, and a combination of a copper wiring and a low dielectric constant film such as porous silica is widely used.
このような銅原子 （あるいはイオン） の拡散を防止するために、 次世代の高密 度集積回路の配線層間絶縁膜として比誘電率の低い分子細孔構造のポーラス S i OCH膜 （比誘電率 k = 2. 4) が既に提案されている。 この膜は、 上記のよう に配線抵抗の低い銅配線と組み合わせ、 また、 多層配線構造で用いることが想定 されている。 このような配線層間絶縁膜を形成するための原料としては、 この他 に、 テトラメチルシクロテトラシロキサンや 6員環ビニルシロキサンが知られて いる。  In order to prevent such diffusion of copper atoms (or ions), a porous Si Si OCH film (relative permittivity k) having a low relative dielectric constant as a wiring interlayer insulating film of the next generation high-density integrated circuit. = 2. 4) has already been proposed. It is assumed that this film is used in combination with a copper wiring having a low wiring resistance as described above and used in a multilayer wiring structure. In addition, tetramethylcyclotetrasiloxane and 6-membered ring vinylsiloxane are known as raw materials for forming such a wiring interlayer insulating film.
半導体装置 ω製造においては、 配線部分で寄生容量を小さくするために、 上記 のポーラス SiOGHの他に、 メソサイズの空孔を導入したポーラスシリカや、 ポー ラス SiLK (登録商標)、 などが使われる。 また、 上記の亍トラメチルシクロテト ラシロキサン （TMCTS) はボロフォスフオシリゲートガラス （BPSG) や フォスフオシリゲートガラス （PSG) の原料にも使用される。 TMCTSは卜 リメチルフォスファイト （TMP) やトリメチルボラ一卜 （TMB) と共に次世 代の B P S Gと P S Gフイルムに使われている。 In manufacturing the semiconductor device ω, in order to reduce the parasitic capacitance in the wiring portion, in addition to the porous SiOGH described above, porous silica into which meso-sized holes are introduced, porous SiLK (registered trademark), and the like are used. The above-mentioned 亍 tramethylcyclotetrasiloxane (TMCTS) is also used as a raw material for borophosphosilicate glass (BPSG) and phosphosilicate gate glass (PSG). TMCTS is the next generation with Limethyl Phosphite (TMP) and Trimethyl Bora (TMB) Used for BPSG and PSG films.
し力、し、 欠点として、 このような銅配線と低比誘電率膜との組み合わせで微細 化を進めた場合には、 配線間の絶縁膜に銅原子 （あるいはイオン） が拡散して、 配線間の絶縁特性が低下するという問題あることが知られている。 このような拡 散は、 製造プロセスにおいて熱工程を経るごとに受けるが、 製品になつてからも 電界が印加される部分では、 電界拡散が起こることはよく知られている。  As a disadvantage, when miniaturization is advanced by combining such copper wiring and a low dielectric constant film, copper atoms (or ions) diffuse into the insulating film between the wiring, and the wiring It is known that there is a problem that the insulation characteristics between them deteriorate. Such diffusion is received every time a thermal process is performed in the manufacturing process, but it is well known that electric field diffusion occurs in the part where an electric field is applied even after the product is manufactured.
特許文献 1 (日本特開 2 0 0 2— 3 3 4 8 7 2号公報） には、 シロキサンから なる部位と、 有機分子からなる部位を交互に結合させた主鎖を有する有機無機ハ イブリツド膜を用いて、 配線材料である銅が層間絶縁膜中に拡散することを防ぐ ことが記載されている。  Patent Document 1 (Japanese Laid-Open Patent Publication No. 2 00 2-3 3 4 8 7 2) discloses an organic-inorganic hybrid film having a main chain in which a part made of siloxane and a part made of an organic molecule are alternately bonded. Is used to prevent copper, which is a wiring material, from diffusing into the interlayer insulating film.
この技術は、 銅イオンとシロキサンあるいは有機分子との相互作用の大小によ つて銅イオンがシロキサン部にトラップされる、 と言うメカニズムでバリア性が 出現することを用いている。 加えて上記の有機分子が各シロキサンを繋ぐ役割を 果たしておリ、 有機分子によって低密度化されるという効果がある。  This technology uses the appearance of barrier properties by the mechanism that copper ions are trapped in the siloxane part due to the magnitude of the interaction between copper ions and siloxane or organic molecules. In addition, the organic molecules play the role of connecting the siloxanes, which has the effect of being reduced in density by the organic molecules.
上記特許文献 1に対して、 本発明では、 後述するように、 シロキサン部と銅を 空間的に離間させ、 拡散に必要なポテンシャルを高くすることによる遮蔽を行つ て銅のイオン化を阻止することでバリア性を発現させる。 環状シロキサンを用い るために、 上記の様に有機分子で各シロキサンを繋ぐ必要はなく、 やはり低密度 が保たれる。  In contrast to the above-mentioned Patent Document 1, in the present invention, as described later, the siloxane portion and the copper are spatially separated and shielded by increasing the potential required for diffusion to prevent copper ionization. With this, barrier properties are developed. Since cyclic siloxane is used, it is not necessary to connect the siloxanes with organic molecules as described above, and the low density is still maintained.
また、 特許文献 2 (日本特開 2 0 0 5 - 4 5 0 5 8号公報） の記載は、 S i R 1 x R2 y R3 z R4 4_(x+y+Z) (シランの誘導体） ガスを用いて作製した絶縁膜で、 R 1—R 4のいずれか一つは π電子を持つ （つまり、 2重結合または 3重結合を持つ） ことが特徴である。 このガスを分解または反応させた珪素化合物が銅ィォン拡散 バリア性を持つことから、 このバリア性を用いるものである。 Patent Document 2 (Japanese Patent Laid-Open No. 2 0 0 5-4 5 0 5 8) describes S i R 1 x R 2 y R 3 z R 4 4 _ (x + y + Z ) (silane This is an insulating film made of gas, and any one of R 1−R 4 has a π electron (that is, has a double bond or triple bond). Since the silicon compound obtained by decomposing or reacting this gas has a copper ion diffusion barrier property, this barrier property is used.
この特許文献 2の開示は、 兀電子を有するシラン誘導体を含むことを特徴と する点で、 本発明と異なっている。  The disclosure of Patent Document 2 is different from the present invention in that it includes a silane derivative having negative electrons.
上記のような銅配線と低比誘電率膜との組み合わせで微細化を進めた場合には、 配線間の絶縁特性が低下するという問題がある。  When miniaturization is promoted by a combination of the copper wiring and the low relative dielectric constant film as described above, there is a problem that the insulating characteristics between the wirings are deteriorated.
本発明の発明者らは、 シロキサン部の有機側鎖の分子量を制御することにより、 シリカ骨格と銅の間を空間的に離間して銅のイオン化を抑制し、 結果として絶縁 膜自身に銅イオンドリフトを抑制する機能を付加することが可能であることを発 見した。 By controlling the molecular weight of the organic side chain of the siloxane moiety, the inventors of the present invention It was discovered that the silica skeleton and copper can be spatially separated to suppress copper ionization, and as a result, a function to suppress copper ion drift can be added to the insulating film itself.
この発明は、 配線間の絶縁膜に銅原子 （あるいはイオン） が拡散しておこる配 線間の絶縁特性の低下という問題を抑制することのできる、 半導体集積回路装置 とその半導体集積回路装置の配線を実現するための配線形成方法を提供すること を目的とする。 発明の開示  The present invention is capable of suppressing the problem of deterioration of insulation characteristics between wirings caused by diffusion of copper atoms (or ions) in an insulating film between wirings, and wiring of the semiconductor integrated circuit device. An object of the present invention is to provide a wiring forming method for realizing the above. Disclosure of the invention
本発明は、 半導体基板上に形成した半導体集積回路装置であって、 銅を含む導 電層から形成した配線と、 前記配線の配線間に設けた絶縁膜とを備え、 上記の絶 縁膜は、 製造プロセスの途中で上記の配線層の少なくとも一部と同時に露出する 3 I P 3 V—シクロシロキサン膜を含み、 製造プロセスの熱工程で配線間に起こ る銅の拡散を抑制する絶縁膜であることを特徴としておリ、 上記の 3 I P 3 V - シクロシロキサン膜を設けて、 高密度集積回路の信頼度を改善する。  The present invention is a semiconductor integrated circuit device formed on a semiconductor substrate, comprising: a wiring formed from a conductive layer containing copper; and an insulating film provided between the wirings, wherein the insulating film is This is an insulating film that contains 3 IP 3 V-cyclosiloxane film that is exposed at the same time as at least a part of the wiring layer in the middle of the manufacturing process, and suppresses the diffusion of copper that occurs between the wirings in the thermal process of the manufacturing process. The above 3 IP 3 V-cyclosiloxane film is provided to improve the reliability of high-density integrated circuits.
また、 上記の配線と 3 I P 3 V—シクロシロキサン膜とは、 バリアメタルを介 して接するようにすることで、 さらに信頼性を高めることができる。  Further, the reliability can be further improved by contacting the wiring and the 3 I P 3 V-cyclosiloxane film through a barrier metal.
このような半導体装置の配線構造は、 平坦な半導体基板上で、 表面に 3 I P 3 V—シクロシロキサン膜を持つた絶縁層に配線/ ターン溝を形成する工程と、 銅 成分を含む導 Λ層を形成する工程と、 ダマシンプロセスあるいはエッチバックプ 口セスを用いて、 溝以外の部分で上記の導電層を除去すると同時に、 上記の 3 I P 3 V—シクロシロキサン膜を露出せしめる工程と、 さらに他の絶縁膜を表面に 形成する工程と、 を含む配線工程で形成することができる。  The wiring structure of such a semiconductor device includes a step of forming a wiring / turn groove in an insulating layer having a 3 IP 3 V-cyclosiloxane film on a flat semiconductor substrate, and a conductive Λ layer containing a copper component. Using the damascene process or an etch back process, removing the conductive layer in a portion other than the groove, and exposing the 3 IP 3 V-cyclosiloxane film, and An insulating film can be formed on the surface, and a wiring process including:
また、 上記の銅成分を含む導電層は、 バリアメタル層上に銅成分を含む金属層 を形成した導電層であることを含む。  The conductive layer containing a copper component includes a conductive layer in which a metal layer containing a copper component is formed on a barrier metal layer.
上記の半導体集積回路装置の配線は、 平坦な半導体基板上で、 絶縁膜上に銅成 分を含む導電層を形成する工程と、 上記の導電層をパターニングして配線を形成 する工程と、 3 I P 3 V—シクロシロキサン膜を少なくとも配線間に形成するェ 程と、 さらに他の絶縁膜を表面に形成する工程と、 を含む形成方法で形成できる。 また、 上記の半導体集積回路装置の配線は、 平坦な半導体基板上で、 絶縁膜上 に銅成分を含む導電層を形成する工程と、 上記の導電層をパターニングして配線 を形成する工程と、 配線のすくなくとも側壁にバリアメタル層を形成する工程と、 3 I P 3 V—シクロシロキサン膜を少なくとも配線間に形成する工程と、 さらに 他の絶縁膜を表面に形成する工程と、 を含む形成方法で形成できる。 図面の簡単な説明 The wiring of the semiconductor integrated circuit device includes a step of forming a conductive layer containing a copper component on an insulating film on a flat semiconductor substrate, a step of patterning the conductive layer to form a wiring, and 3 It can be formed by a forming method including: a step of forming an IP 3 V-cyclosiloxane film at least between wirings; and a step of forming another insulating film on the surface. The wiring of the semiconductor integrated circuit device includes a step of forming a conductive layer containing a copper component on an insulating film on a flat semiconductor substrate, a step of patterning the conductive layer, and forming a wiring. Forming a barrier metal layer on at least the side wall of the wiring, forming a 3 IP 3 V-cyclosiloxane film at least between the wirings, and forming another insulating film on the surface. Can be formed. Brief Description of Drawings
図 1 (a) 、 (b) 、 (c) 、 (d) 、 (e) は、 半導体集積回路装置の製造 プロセスを示す。  Figures 1 (a), (b), (c), (d), and (e) show the manufacturing process of a semiconductor integrated circuit device.
図 2は、 本発明を適用する集積回路を説明するための断面図の例である。  FIG. 2 is an example of a cross-sectional view for explaining an integrated circuit to which the present invention is applied.
図 3 (a) 、 （b) 、 （c) 、 （d) 、 （e) 、 （ f ) は、 本発明の製造プロ セスを示す断面図である。  3 (a), (b), (c), (d), (e), and (f) are cross-sectional views showing the manufacturing process of the present invention.
図 4 (a) 、 （b) は、 M I S構造素子の累積故障率の測定結果を示す図であ る。  Figures 4 (a) and 4 (b) are diagrams showing the measurement results of the cumulative failure rate of the M IS structure element.
図 5は、 M I S構造素子の MT F特性を測定するための測定試料の断面構造を 示す模式図である。  FIG. 5 is a schematic diagram showing a cross-sectional structure of a measurement sample for measuring the MTF characteristic of an MIS structure element.
図 6 (a) 、 (b) 、 (c) は、 フラットバンドシフトに関する測定結果を示 す図である。  Figures 6 (a), (b), and (c) show the measurement results for the flat band shift.
図 7は、 M I S構造素子の MT F特性の測定結果を示す図である。  FIG. 7 is a diagram showing the measurement results of the MTF characteristics of the MIS structure element.
図 8は、 M I S構造素子の M T F特性の膜厚依存性の測定結果を示す図である。 発明を実施するための最良の形態  FIG. 8 is a graph showing the measurement results of the film thickness dependence of the MTF characteristics of the MIS structure element. BEST MODE FOR CARRYING OUT THE INVENTION
この発明の実施の形態を図面に基づいて詳細に説明する。 以下の説明において は、 同じ機能あるいは類似の機能をもった装置に、 特別な理由がない場合には、 同じ符号を用いるものとする。  Embodiments of the present invention will be described in detail with reference to the drawings. In the following description, devices having the same function or similar functions are denoted by the same reference numerals unless there is a special reason.
上記の様に、 本発明の発明者らは、 シロキサン部の有機側鎖の分子量を制御す ることにより、 シリカ骨格と銅の間を空間的に遮蔽して銅のイオン化を抑制し、 結果として絶縁膜自身に銅イオンドリフ卜を抑制する機能を付加することが可能 であることを見出した。 つまり、 プラズマ重合で絶縁膜を形成すると環状シロキ サン骨格を持つので、 各珪素からイソプロピル基 （I P) とビニル基 （V) を有 する 3 I P 3 V—シクロシロキサンでは膜内に銅イオンが侵入することができな しヽ。 一方、 有機側鎖としてメチル基を有する MS Q (methylsilsesquioxane) や、 S i一 0ネッ卜ワーク中にメチル基を有する S i OC (DMDMOS： As described above, the inventors of the present invention control the molecular weight of the organic side chain of the siloxane part to spatially shield between the silica skeleton and copper, thereby suppressing the ionization of copper. We have found that it is possible to add a function of suppressing copper ion drift to the insulating film itself. In other words, when an insulating film is formed by plasma polymerization, Since it has a sun skeleton, 3 IP 3 V-cyclosiloxane with isopropyl group (IP) and vinyl group (V) from each silicon does not allow copper ions to penetrate into the film. On the other hand, MS Q (methylsilsesquioxane) having a methyl group as an organic side chain and S i OC (DMDMOS:
Dimethyldimet oxysilane を出発原料として用いたプラズマ CV Dで成膜した S i OC) では、 原料の分子構造が部分的に保持されることが少なく、 バリア性 は見られないか、 あるいは極めて小さい。 すなわち有機側鎖として、 炭素原子 2 個以上を有する場合にバリア性が発現する。 これら炭素原子の化学結合は、 単結 合、 2重結合、 あるいは 3重結合のいずれでもよい。 単結合の場合は空間的な遮 蔽が、 また多重結合の場合は、 それに加えて電気的な遮蔽が期待できる。 また、 ここでは環状シロキサンを例に挙げているが、 開環していても有機側鎖による遮 蔽効果が存在する場合は同様の効果が期待できるため、 必ずしも環状であること に縛られない。 In S i OC) formed by plasma CV D using dimethyldimetoxysilane as a starting material, the molecular structure of the raw material is rarely partially retained, and the barrier property is not seen or extremely small. That is, barrier properties are exhibited when the organic side chain has 2 or more carbon atoms. The chemical bond of these carbon atoms may be a single bond, a double bond, or a triple bond. In the case of a single bond, spatial shielding can be expected, and in the case of multiple bonds, in addition to that, electrical shielding can be expected. In addition, although a cyclic siloxane is taken as an example here, even if the ring is opened, the same effect can be expected when the shielding effect by the organic side chain is present, so that it is not necessarily limited to being cyclic.
また、 有機側鎖を有する環状シロキサン （3 I P3V—シクロシロキサン、 以 下では、 OCS ： Organo-Cyclo-Si loxaneとも表示） を用いて作製した Cu— M I S (金属電極に銅を用いた金属一絶縁膜一半導体） 構造での実験結果を図 4 (a) 、 図 4 (b) に示す。  In addition, Cu-MIS (metal alloy using copper as the metal electrode) prepared using cyclic siloxane with organic side chains (3 I P3V—cyclosiloxane; hereinafter also referred to as OCS: Organo-Cyclo-Siloxane). The experimental results for the (insulator-semiconductor) structure are shown in Figs. 4 (a) and 4 (b).
図 4 (a) の結果から、 3 I P 3 V—シクロシロキサンで、 E>0と E<0に 電界を印加した場合の絶縁破壊時間が等しいことがわかる。 一方、 図 4 (b) に 示す様に、 S i 02 (モノシランと笑気ガスを用いた CVD (化学的気層成長 法） 膜） や、 S i OC (DMDMOSを用いた CVD膜） では、 E>0に印加し た場合の絶縁破壊時間が短い。 これは S i 02や S i OCでは E>0の電界で膜 中に銅イオンが電界ドリフトすることによる。 これ力、ら、 3 I P3V—シクロシ ロキサン内部に銅イオンがドリフ卜できない、 すなわち 3 I P 3 V—シクロシロ キサン自身がバリア性を有することを意味する。 また、 3 I P 3 V—シクロシロ キサンの場合は、 同じ測定条件の S i OCの場合に比べて、 ほぼ 1桁寿命が長い。 以上のように、 3 I P 3 V—シクロシロキサン膜内への銅イオンの電界ドリフ 卜が抑制される事が分かる。 これは、 3 I P3V—シクロシロキサンに含まれる ビニル基とイソプロピル基が、 電極に含まれる銅と膜構造に含まれるシリカ部分 を空間的、 あるいは電気的に遮蔽することにより、 銅のイオン化が抑制されるた めである、 と考えられる。 電気的遮蔽は二重結合、 三重結合で生じる余剰電子From the results in Fig. 4 (a), it can be seen that the breakdown time is the same for 3 IP 3 V-cyclosiloxane when E> 0 and E <0 are applied. On the other hand, as shown in Fig. 4 (b), S i 0 2 (CVD (chemical vapor deposition) film using monosilane and laughing gas) and S i OC (CVD film using DMDMOS) The dielectric breakdown time when E> 0 is applied is short. This is due to the electric field drift of copper ions in the film with an electric field of E> 0 in S i 0 2 and S i OC. This means that copper ions cannot drift inside the 3 I P3V-cyclosiloxane, that is, 3 IP 3 V-cyclosiloxane itself has a barrier property. In addition, 3 IP 3 V-cyclosiloxane has a lifetime that is almost an order of magnitude longer than that of SioC under the same measurement conditions. As described above, it can be seen that the electric field drift of copper ions into the 3 IP 3 V-cyclosiloxane film is suppressed. This is because the vinyl group and isopropyl group contained in 3 I P3V-cyclosiloxane are the copper part contained in the electrode and the silica part contained in the film structure. This is thought to be because copper ionization is suppressed by spatially or electrically shielding the copper. Electrical shielding is surplus electrons generated by double and triple bonds
(π電子) がイオン化した銅に供与されて中性化される、 という意味であり、 空間的な遮蔽で銅のィオン化を阻止し、 また格子欠陥などの何らかの理由でィォ ン化した場合でも、 電気的な遮蔽で元に戻す、 という効果が予測できる。 これは、 換言すれば、 有機側鎖にてシリカ骨格 （特に酸素原子） を遮蔽することで銅ィォ ンドリフトへのバリア特性を有する絶縁膜を実現できることを示している。 また、 上記の意味で、 空間的にあるいは電気的に遮蔽することは、 有機側鎖の長さ （分 子量と言い換えこともできる） に依存することから、 その長さを最適化すること によリバリア性を最適化すること力可能であると予測できる。 つまり、 有機側鎖 の分子量を制御することにより、 シリカ骨格と銅の間を空間的に遮蔽して銅ィォ ンとなるイオン化を抑制し、 その結果、 銅イオンドリフ卜数を抑制することが予 測できる。 This means that (π electrons) are donated to ionized copper and become neutralized. Spatial shielding prevents copper ionization and ionization for some reason such as lattice defects However, it can be predicted that it can be restored by electrical shielding. In other words, this indicates that an insulating film having a barrier property against copper ion drift can be realized by shielding the silica skeleton (especially oxygen atoms) with an organic side chain. In addition, in the above sense, spatial or electrical shielding depends on the length of the organic side chain (which can be paraphrased as the molecular weight), so it is necessary to optimize the length. It can be predicted that it is possible to optimize the rebarrier property. In other words, by controlling the molecular weight of the organic side chain, it is possible to spatially shield between the silica skeleton and copper and suppress ionization to become copper ions, and as a result, to suppress the copper ion drift number. Can be predicted.
上記の解釈が正しいことは、 環状 S i一 o骨格と有機側鎖 （メチル基） を有す る MSQや、 S i — Oネットワーク中にメチル基を有する S ί OC (DMDMO S) ではバリア性は見られない （あるいは極めて小さい） 力 イソプロピル基と ビニル基を有する 3 I Ρ 3 V—シクロシロキサンでは膜内に銅イオンが侵入する ことができない、 ということから分かる。  The above interpretation is correct because MSQ with a cyclic S i 1 o skeleton and organic side chain (methyl group) and S OC (DMDMO S) with a methyl group in the S i — O network have barrier properties. Is seen (or very small) force It can be seen from the fact that 3 I Ρ 3 V-cyclosiloxane with isopropyl and vinyl groups cannot penetrate copper ions into the film.
まず、 図 6 (a) に、 Cu電極をつけた 3 I P 3 V—シクロシロキサン （OC S) M I S構造のフラットバンドシフ卜の測定結果を示す。 測定に用いた MOS キャパシタは、 CuZOCS (200 nm) i O 2 (30 nm) S iの M First, Fig. 6 (a) shows the measurement results of the flat band shift of the 3 I P 3 V-cyclosiloxane (OC S) M I S structure with a Cu electrode. The MOS capacitor used for the measurement is CuZOCS (200 nm) i O 2 (30 nm) S i M
I S構造である。 この測定結果は、 図 6 (b) の MSQの場合と比べて十分に小 さい。 更に、 図 6 (c) に示す様に電界強度を 1 MVZcmと高くして測定した 場合でも， フラットバンドシフトは極僅かであることから， 銅イオンの 3 1 P3 V—シクロシロキサンへの侵入抑制効果があることが分かる。 It is an IS structure. This measurement result is sufficiently small compared to the case of MSQ in Fig. 6 (b). Furthermore, as shown in Fig. 6 (c), even when the electric field strength is measured as high as 1 MVZcm, the flat band shift is negligible, which prevents the copper ions from entering the 3 1 P3 V-cyclosiloxane. It turns out that there is an effect.
次に、 図 5の断面構造を持った測定試料が絶縁破壊に至るまでの平均時間 （M T F) の印加電界依存性を、 図 7に示す。 図中、 Po-S i 02はポーラス （多 孔性） シリコン酸化膜 （1 38 nm) 、 O C Sは 3 I P 3 V—シクロシロキサン (0から800 ） 、 B CBはプラズマ中で重合したベンゾシクロブテン (benzocyclobutene) である。 シリコン熱酸化膜の膜厚は 30 n mである。 OC S、 BCBについては、 銅電極が正電圧となる電界を印加している。 図 7力、ら、 3 I P 3 V— クロシロキサンの膜厚が 30 n mと薄い場合でも、 この膜による 絶縁破壊を抑制する効果が大きいことが分かる。 Next, Fig. 7 shows the applied electric field dependence of the mean time (MTF) required for a measurement sample having the cross-sectional structure shown in Fig. 5 to reach dielectric breakdown. In the figure, Po-S i 0 2 is porous (polyporous) silicon oxide film (1 38 nm), OCS is 3 IP 3 V—cyclosiloxane (0 to 800), B CB is benzocyclopolymerized in plasma Butene (benzocyclobutene). The thickness of the silicon thermal oxide film is 30 nm. For OC S and BCB, an electric field is applied in which the copper electrode has a positive voltage. Figure 7 Force, et al. 3 IP 3 V— Even when the film thickness of chlorosiloxane is as thin as 30 nm, it can be seen that this film has a great effect of suppressing dielectric breakdown.
図 8は、 図 5の構造の測定試料についての M T Fの膜厚依存性を示す図である。  FIG. 8 is a graph showing the dependence of MTF on the film thickness of the measurement sample having the structure of FIG.
OCSの場合には、 なし、 30、 80 nmについて測定したものであるが、 OC S膜厚が 30 nmの場合でも、 なしの場合に比べて寿命が 2桁長いことが分かる。 また、 OCSの膜厚が 30 の場合の電界依存性のデータを、 低電界側に外揷 すると、 約 0. 41\1 <= 付近の電界で1\1丁ドが1 0年 （3 X 1 08秒） に達 する。 換言すれば、 ポーラスシリカに 30 nmの OCS膜を形成すると、 20 0°Cの高温において銅イオンのドリフ卜する E>0の電界を印加した場合でも、 0. 41\1 (； 以下の電界強度で1 0年間絶縁性を保持することが可能である。 加えて、 実際のデバイス動作温度は高々 1 50°C程度であることから、 この条件 下では、 さらに高い電界強度での 1 0年信頼性が実現することは明らかである。 これは、 たとえば 45 nmピッチの配線 （配線幅 25 n m、 間隔 20 n m) で、In the case of OCS, measurements were made for none, 30 and 80 nm, but it can be seen that even when the OCS film thickness is 30 nm, the lifetime is two orders of magnitude longer than that without. In addition, when the electric field dependence data when the film thickness of OCS is 30 are applied to the low electric field side, 1 \ 1 cosine is about 10 years (3 X 1 0 8 seconds). In other words, when an OCS film of 30 nm is formed on porous silica, even when an E> 0 electric field drifting copper ions at a high temperature of 200 ° C is applied, 0.41 \ 1 (; It is possible to maintain insulation for 10 years in strength.In addition, since the actual device operating temperature is about 150 ° C at most, under these conditions, 10 years at higher electric field strength. It is clear that reliability is achieved, for example, with a 45 nm pitch wiring (wiring width 25 nm, spacing 20 nm)
1 Vの電源電圧を想定した場合の電界強度 0. 2MVZcmを大きく超えるため、 実際の配線寿命は更に長いことがわかる。 Assuming a 1 V power supply voltage, the field strength greatly exceeds 0.2 MVZcm, indicating that the actual wiring life is even longer.
銅イオンドリフト機能を有する絶縁膜を、 半導体集積回路装置の層間絶縁膜と してあるいはポーラスシリカなど通常の層間絶縁膜に対してサイドウオールとし て、 用いることにより、 バリアメタルの不要な面内配線の形成や極薄バリアメタ ルに生じたピンホールなどに起因するウィークスポッ卜の補強に、 用いることが 可能である。 また配線上面と同水準の界面のリーク電流対策として、 およびダマ シンプロセスあるいはェッチノ <ックプロセスで配線を溝バタ一ンに埋め込んで/ ターニングする場合に、 埋め込みプロセスに用いる CMP (化学的機械研磨） あ るいは異方性エッチングプロセスのストッパ層として用いることができ、 なお且 つ、 さらに絶縁膜を形成した場合にできるもので形成した絶縁膜との界面にでき る拡散チャネルの拡散バリアとしても使用できる。 また、 前記のストツバ層とし ては、 上記の鋼ィオンドリフト機能を有する絶縁膜を用いる必然性は無く、 CM Pあるいは異方性エッチングプロセスで良好な選択性を発揮する層をストツバ層 として設けて、 その下層に前記の銅ィオンドリフト機能を有する絶縁膜を設ける 構造であってもよいことは明らかである。 By using an insulating film having a copper ion drift function as an interlayer insulating film of a semiconductor integrated circuit device or as a side wall with respect to an ordinary interlayer insulating film such as porous silica, an in-plane wiring that does not require a barrier metal It can be used to reinforce weak spots due to the formation of pinholes and pinholes generated in ultrathin barrier metals. In addition, as a countermeasure against leakage current at the same level as the upper surface of the wiring, and CMP (Chemical Mechanical Polishing) used for the embedding process when the wiring is embedded / turned in the groove pattern by the damascene process or the etch knock process. It can also be used as a stopper layer for anisotropic etching processes, and can also be used as a diffusion barrier for diffusion channels formed at the interface with an insulating film formed when an insulating film is formed. . In addition, as the above-mentioned stubber layer, there is no necessity to use the insulating film having the steel ion drift function described above, and a layer that exhibits good selectivity in CMP or anisotropic etching process is used. It is obvious that the insulating film having the copper ion drift function may be provided in the lower layer.
更に本発明で用いる絶縁膜は、 配線上あるいは CM P界面の銅イオンの拡散バ リアとしても使用できる。 従来この部分には、 拡散バリア性を有する S i CNが 使用されることが多いが、 本発明では、 低誘電率膜の拡散バリア性を持った絶縁 膜を使用する とにより、 配線間容量の低減を図ることが可能で、 なおかつ、 異 種膜界面への銅イオンドリフ卜抑制効果が可能である。  Furthermore, the insulating film used in the present invention can also be used as a copper ion diffusion barrier on the wiring or at the CMP interface. Conventionally, Si CN having a diffusion barrier property is often used for this part, but in the present invention, by using an insulating film having a diffusion barrier property of a low dielectric constant film, the capacitance between wirings can be reduced. It is possible to reduce the copper ion drift at the interface with the heterogeneous film.
図 1は、 本発明を適用する集積回路を説明するための断面例を示す図である。 図 1は、 バリアメタルのサイドウオールと並行しバリア性を有するサイドウォー ルを設けて、 横方向の銅イオンの拡散をブロックする配線構造と、 その製造プロ セスの一部を示すものである。 ここでは、 込み入った説明を避けるために、 簡単 な配線構造にしているが、 さらに複雑な配線構造に本発明を適用できることは明 らカ、である。  FIG. 1 is a cross-sectional view illustrating an integrated circuit to which the present invention is applied. Fig. 1 shows a wiring structure that blocks the diffusion of copper ions in the lateral direction by providing a side wall that has barrier properties in parallel with the side wall of the barrier metal, and shows a part of the manufacturing process. Here, in order to avoid complicated explanation, a simple wiring structure is used, but it is apparent that the present invention can be applied to a more complicated wiring structure.
図 1 (a) では、 半導体基板 1上にトランジスタ層 2を形成し、 エッチングス トツパ層 3としてシリコン窒化膜 （膜厚 20〜30 nm) を CVD (化学的気相 成長） プロセスで形成する。 エッチングストツバ層 3上には、 層間絶縁膜 4 (膜 厚 1 00〜1 50 nm) 、 低誘電率キャップ層 5 (膜厚 20 nm程度） を積層し、 配線用の溝パターンをフォ卜リソグラフィプロセスで形成し、 銅イオンのパリア 性を有する 3 I P3V—シクロシロキサン膜あるいは BCB膜などの膜 20 (膜 厚 30 nm以下） を積層し、 異方性エッチングを行なってサイドウォールを形成 する。  In FIG. 1 (a), a transistor layer 2 is formed on a semiconductor substrate 1, and a silicon nitride film (film thickness 20-30 nm) is formed as an etching stopper layer 3 by a CVD (chemical vapor deposition) process. An interlayer insulating film 4 (film thickness: 100 to 150 nm) and a low dielectric constant cap layer 5 (film thickness of about 20 nm) are stacked on the etching stubber layer 3 to form a trench pattern for wiring. The film is formed by a process, and a film 20 (film thickness of 30 nm or less) such as a 3 I P3V-cyclosiloxane film or BCB film having a copper ion barrier property is laminated, and anisotropic etching is performed to form a sidewall.
図 1 (b) では、 さらにバリアメタル層 6 (膜厚 1 0 nm以下） を積層し、 異 方性エッチングを行なってサイドウォールを形成する。 これで、 銅イオンのバリ ァ性を有する膜とバリアメタル層とが並行するサイドウオールが形成される。 図 1 (c) では、 銅を含む配線層 7を積層し、 CM Pプロセスあるいはエッチ ングプロセスで、 図 1 (d) に示すような埋め込まれた銅配線を形成する。 この 際、 銅イオンのバリア性を有する 3 I P 3 V—シクロシロキサン膜あるいは BC B膜などの膜 20を、 CM Pプロセスの終点検出に用いるか異方性エッチングの ストツバ層として用いる。 その後に、 誘電体バリア層 8を設ける。 図 1 ( e ) では、 さらに上層に配線層をもった多層配線の半導体装置の場合を 想定して、 さらに層間絶縁膜 2 1とプラグを示した。 この製造プロセスは、 例え ば、 層間絶縁膜 2 1をつけ、 ビアホールをエッチングで形成し、 バリア性を備え た膜 1 1をビアホールの側壁に形成する。 これは、 上記のバリアメタル層 6のサ イドウォールと同様に形成することができ、 その後、 プラグ層 1 2を形成して埋 め込みを行う、 と言うものである。 In FIG. 1 (b), a barrier metal layer 6 (thickness of 10 nm or less) is further laminated, and anisotropic etching is performed to form sidewalls. As a result, a side wall is formed in which the barrier film and the copper ion barrier film are parallel to each other. In FIG. 1 (c), a wiring layer 7 containing copper is laminated, and a buried copper wiring as shown in FIG. 1 (d) is formed by a CMP process or an etching process. At this time, a film 20 such as a 3 IP 3 V-cyclosiloxane film or a BCB film having a barrier property of copper ions is used for detecting the end point of the CMP process or used as a stutter layer for anisotropic etching. Thereafter, a dielectric barrier layer 8 is provided. In FIG. 1 (e), the interlayer insulating film 21 and the plug are further shown on the assumption that the semiconductor device has a multilayer wiring having a wiring layer as an upper layer. In this manufacturing process, for example, an interlayer insulating film 21 is attached, a via hole is formed by etching, and a film 11 having a barrier property is formed on the sidewall of the via hole. This can be formed in the same manner as the sidewall of the barrier metal layer 6 described above, and then the plug layer 12 is formed and embedded.
図 2は、 本発明を適用する集積回路を説明するための断面例を示す図である。 ここでは、 込み入った説明を避けるために、 簡単な配線構造にしているが、 さら に複雑な配線構造に本発明を適用できることは明らかである。 図 2の断面構造を、 半導体基板 1、 トランジスタ層 2および多層配線層に分けて説明する。 図 2のト ランジスタ層には、 トランジスタを形成する拡散層やトランジスタのゲート電極、 ソース電極、 ドレイン電極などと、 それらに電圧 .電流を供給する電極、 および、 各電極を絶縁する層間絶縁膜などを配置している。 また、 本発明は主に配線層に 関しているが、 配線層は、 アルミニウム配線層と 2層の銅配線層とをプラグで接 続した層配線構造をもっている。 銅配線は、 バリアメタルを介して層間絶縁膜【こ 接している。 また、 銅配線層の表面と同じ高さで銅イオンの拡散をブロックする 絶縁層を配置している。 この構造については、 図 3を参照して以下に説明する。 図 3は、 配線層を形成するための製造工程の一例を示す図である。 銅配線は、 ダマシンプロセスとして知られる方法で形成する。 図 3は、 シングルダマシンの 例であるが、 デュアルダマシンの場合でも同様に本発明を適用することができる。 また、 一般に、 半導体製造工程では、 その一部を容易に他の製造工程で代用する ことが可能であり、 本発明では、 以下に示す工程に限定すべき理由はない。  FIG. 2 is a cross-sectional view for explaining an integrated circuit to which the present invention is applied. Here, in order to avoid complicated explanation, a simple wiring structure is used. However, it is obvious that the present invention can be applied to a more complicated wiring structure. The cross-sectional structure of FIG. 2 will be described by dividing it into a semiconductor substrate 1, a transistor layer 2, and a multilayer wiring layer. The transistor layer in FIG. 2 includes a diffusion layer that forms a transistor, a gate electrode, a source electrode, and a drain electrode of the transistor, electrodes that supply voltage and current to them, and an interlayer insulating film that insulates each electrode. Is arranged. Although the present invention mainly relates to a wiring layer, the wiring layer has a layer wiring structure in which an aluminum wiring layer and two copper wiring layers are connected by a plug. The copper wiring is in contact with the interlayer insulation film through the barrier metal. In addition, an insulating layer that blocks the diffusion of copper ions is arranged at the same height as the surface of the copper wiring layer. This structure is described below with reference to FIG. FIG. 3 is a diagram illustrating an example of a manufacturing process for forming a wiring layer. Copper wiring is formed by a method known as the damascene process. FIG. 3 shows an example of a single damascene, but the present invention can be similarly applied to a dual damascene. In general, a part of the semiconductor manufacturing process can be easily substituted with another manufacturing process, and in the present invention, there is no reason to limit to the following processes.
図 3 ( a ) では、 半導体基板 1上にトランジスタ層 2を形成し、 エッチングス トツパ層 3としてシリコン窒化膜 （膜厚 2 0〜3 0 n m) を C V Dプロセスで形 成する。 エッチングストッパ層 3上には、 層間絶縁膜 4 (fl莫厚 1 0 0〜 1 5 0 η m) 、 低誘電率キャップ層 5 (膜厚 2 0 n m程度） を積層し、 配線用の溝パター ンをフォトリソグラフィプロセスで形成し、 バリアメタル層 6 (膜厚 1 0 n m以 下） を積層する。  In FIG. 3A, a transistor layer 2 is formed on a semiconductor substrate 1, and a silicon nitride film (thickness 20 to 30 nm) is formed as an etching stopper layer 3 by a CVD process. On the etching stopper layer 3, an interlayer insulating film 4 (fl thick 10 0 to 15 0 η m) and a low dielectric constant cap layer 5 (film thickness of about 20 nm) are laminated, and a trench pattern for wiring The barrier metal layer 6 (thickness of 10 nm or less) is laminated.
図 3 ( b ) では、 次に、 異方性エッチングを行なってバリアメタル層 6のサイ ドウオールを形成した後、 銅配線層 7を形成する。 配線用の溝パターンに銅配線 層を埋め込むために、 通常のダマシンプロセスと同様に、 CMP (化学的機械研 磨） プロセスを用いる。 この際、 低誘電率キャップ層 5を終点検出に用いる。 こ こで、 銅配線層とは、 銅を主成分として含む導電層である。 また、 この配線工程 では、 ノくリアメタル層 6を形成した後、 異方性エッチングを行なわずに銅配線層 7を形成して、 CMPプロセスで埋め込む、 という方法をとることもできる。 図 3 (c) では、 次に、 誘電体バリア層 8、 ビア （V i a) 層間絶縁膜層 9 (膜厚 1 50〜300 nm) とエッチングストッパ層 1 0 (膜厚 20〜30 n m) を形成し、 ビアホールをフォトリソグラフィプロセスで形成し、 3 I P3V ーシクロシロ サン膜あるいは BCB膜などのバリア性を備えた膜 1 1 (膜厚 3 O nm以下) でサイドウオール形成し、 プラグ層 1 2を積層し、 異方性エツチン グを行なつてプラグを形成する。 In FIG. 3 (b), next, anisotropic etching is performed to form the barrier metal layer 6. After forming the wall, the copper wiring layer 7 is formed. A CMP (Chemical Mechanical Polishing) process is used to embed the copper wiring layer in the wiring trench pattern, similar to the usual damascene process. At this time, the low dielectric constant cap layer 5 is used for end point detection. Here, the copper wiring layer is a conductive layer containing copper as a main component. In this wiring process, after forming the rear metal layer 6, the copper wiring layer 7 can be formed without performing anisotropic etching, and then buried by a CMP process. Next, in FIG. 3 (c), the dielectric barrier layer 8, the via interlayer insulating film layer 9 (film thickness 150 to 300 nm) and the etching stopper layer 10 (film thickness 20 to 30 nm) are formed. Then, a via hole is formed by a photolithography process, and a sidewall is formed with a film 11 having a barrier property such as a 3 I P3V-cyclosiloxane film or a BCB film (film thickness of 3 O nm or less), and a plug layer 1 2 is formed. Laminated and anisotropically etched to form plugs.
図 3 (d) では、 次に、 層間絶縁膜 1 3とエッチングストッパ層 14 (膜厚 2 0〜30 nm) を積層し、 配線用の溝パターンをフォトリソグラフィプロセスで 形成し、 バリアメタル層 1 5 (膜厚 1 O nm以下） を積層した後、 異方性エッチ ングを行なってバリアメタル層 1 5 (膜厚 1 O nm以下） のサイ ドウオールを形 成する。  Next, in FIG. 3 (d), an interlayer insulating film 13 and an etching stopper layer 14 (thickness 20-30 nm) are stacked, and a trench pattern for wiring is formed by a photolithography process, and the barrier metal layer 1 After stacking 5 (thickness 1 O nm or less), anisotropic etching is performed to form a barrier metal layer 15 (thickness 1 O nm or less) side wall.
図 3 (e) では、 次に銅配線層 1 6を形成し、 上記と同様にダマシンプロセス によって配線用の溝パターンに銅配線層を埋め込む。 上記の様に、 図 3はシング ルダマシンの例であるが、 デュアルダマシンの場合でも同様に本発明を適用する ことができる。 銅配線層の厚さは、 流したい電流によって異なる力 埋め込み後 で 500〜1 G OO nm程度の配線になるようにするために、 CM Pプロセス前 で 1〜 3 m程度の銅配線層 1 6を形成する。  In FIG. 3 (e), a copper wiring layer 16 is formed next, and the copper wiring layer is buried in the wiring groove pattern by the damascene process in the same manner as described above. As described above, FIG. 3 shows an example of a single damascene, but the present invention can be similarly applied to a dual damascene. The thickness of the copper wiring layer varies depending on the current to be applied. In order to obtain a wiring of about 500 to 1 GOO nm after embedding, a copper wiring layer of about 1 to 3 m before the CMP process 1 6 Form.
図 3 (d) 、 図 3 (e) にかかる配線工程では、 上記と同様に、 バリアメタル 層 1 5を形成した後、 異方性エッチングを行なわずに銅配線層 1 6を形成して、 CMPプロセスで埋め込む、 という方法をとることもできる。  In the wiring process shown in FIGS. 3 (d) and 3 (e), after forming the barrier metal layer 15 and forming the copper wiring layer 16 without performing anisotropic etching, as described above, You can also embed by CMP process.
図 3 (f ) は、 形成した銅配線層 1 6上に低誘電率絶縁膜 17、 保護膜 1 8を つけた半導体集積回路装置を示す。 産業上の利用可能性 FIG. 3 (f) shows a semiconductor integrated circuit device in which a low dielectric constant insulating film 17 and a protective film 18 are provided on the formed copper wiring layer 16. Industrial applicability
上述のような絶縁膜を使用して銅イオンをブロックすると、 例えば銅ィオンド リフ卜が起こる膜でも層間絶縁膜として使用することができ、 低比誘電率膜の選 択肢を広げることができる。 またポーラス （多孔性） シリカなど超低誘電率層間 絶縁膜に対してポアシール （サイドウォール） として用いることも可能である。 配線間が例えば 0 . 6ミクロンの場合には、 上記の例にある 3 0 n mの膜を用い るとすると、 配線間の絶縁膜の 9割をポアシール以外のこの超低誘電率層間絶縁 膜とすることができ、 配線間の寄生容量を抑制できる。 この際、 上記の銅イオン をブロックする絶縁膜は、 いずれの場合でも、 バリアメタルフリーの配線構造も しくは極薄/くリアメタルを用いた配線構造を用いた場合に生じるピンホールなど に起因するウ ークスポッ卜を補強する効果があり、 半導体デバイスの信頼性を 向上できる。  When copper ions are blocked using the insulating film as described above, for example, a film in which copper ion diffusion occurs can be used as an interlayer insulating film, and the choice of a low dielectric constant film can be expanded. It can also be used as a pore seal (side wall) for ultra-low dielectric constant interlayer insulating films such as porous silica. For example, in the case where the distance between wirings is 0.6 microns, if the 30 nm film in the above example is used, 90% of the insulating film between the wirings and this ultra low dielectric constant interlayer insulating film other than the pore seal And parasitic capacitance between wires can be suppressed. At this time, the insulating film that blocks the copper ions in any case is caused by a pinhole generated when a barrier metal-free wiring structure or an extremely thin / rear metal wiring structure is used. It has the effect of reinforcing the wakespot and can improve the reliability of semiconductor devices.

Claims

請 求 の 範 囲 半導体基板上に形成した半導体集積回路装置であって、 Scope of request A semiconductor integrated circuit device formed on a semiconductor substrate, comprising:
銅を含む導電層から形成した配線と、 Wiring formed from a conductive layer containing copper;
前記配線の配線間に設けた絶縁膜と、 を備え、 An insulating film provided between the wirings of the wiring, and
上記の絶縁膜は、 製造プロセスの途中で上記の配線層の少なくとも一部と同 時に露出する 3 I P 3 V—シクロシロキサン膜を含み、 配線間に起こる銅の 拡散を抑制する絶縁膜であることを特徴とする半導体集積回路装置。 The insulating film includes a 3 IP 3 V-cyclosiloxane film that is exposed at the same time as at least a part of the wiring layer during the manufacturing process, and is an insulating film that suppresses copper diffusion that occurs between the wirings. A semiconductor integrated circuit device.
上記の配線と 3 I P 3 V—シクロシロキサン膜とは、 バリアメタルを介して 接していることを特徴とする請求の範囲第 1項記載の半導体集積回路装置。 請求の範囲第 1項又は第 2項記載の半導体集積回路装置の製造における配線 形成方法であって、 2. The semiconductor integrated circuit device according to claim 1, wherein the wiring and the 3 I P 3 V-cyclosiloxane film are in contact with each other through a barrier metal. A method of forming a wiring in manufacturing a semiconductor integrated circuit device according to claim 1 or 2,
半導体集積回路装置の配線を形成する際に、  When forming the wiring of the semiconductor integrated circuit device,
平坦な半導体基板上で、 On a flat semiconductor substrate,
表面に 3 I P 3 V—シクロシロキサン膜を持った絶縁層に配線パターン溝を 形成する工程と、 Forming a wiring pattern groove in an insulating layer having a 3 I P 3 V-cyclosiloxane film on the surface;
銅成分を含む導電層を形成する工程と、 Forming a conductive layer containing a copper component;
ダマシンプロセスを用いて、 溝以外の部分で上記の導電層を除去すると同時 に、 上記の 3 I P 3 V—シクロシロキサン膜を露出せしめる工程と、 さらに他の絶縁膜を表面に形成する工程と、 Using the damascene process to remove the conductive layer in a portion other than the groove, and simultaneously exposing the 3 IP 3 V-cyclosiloxane film, and forming another insulating film on the surface;
を含むことを特徴とする配線形成方法。 A wiring forming method comprising:
上記の銅成分を含む導電層は、 バリアメタル層上に銅成分を含む金属層を形 成した導電層であることを特徴とする請求の範囲第 3項記載の配線形成方法。 請求の範囲第 1項又は第 2項記載の半導体集積回路装置の製造における配線 形成方法であって、 4. The wiring forming method according to claim 3, wherein the conductive layer containing a copper component is a conductive layer in which a metal layer containing a copper component is formed on a barrier metal layer. A method of forming a wiring in manufacturing a semiconductor integrated circuit device according to claim 1 or 2,
半導体集積回路装置の配線を形成する際に、  When forming the wiring of the semiconductor integrated circuit device,
平坦な半導体基板上で、 On a flat semiconductor substrate,
絶縁膜上 銅成分を含む導電層を形成する工程と、 Forming a conductive layer containing a copper component on the insulating film;
上記の導電層をパターニングして配線を形成する工程と、 3 I P 3 V—シクロシロキサン膜を少なくとも配線間に形成する工程と、 さらに他の絶縁膜を表面に形成する工程と、 Patterning the conductive layer to form a wiring; 3 a step of forming an IP 3 V-cyclosiloxane film at least between the wirings, a step of forming another insulating film on the surface,
を含むことを特徴とする配線形成方法。 A wiring forming method comprising:
請求の範囲第 1項又は第 2項記載の半導体集積回路装置の製造における配線 形成方法であって、 A method of forming a wiring in manufacturing a semiconductor integrated circuit device according to claim 1 or 2,
半導体集積回路装置の配線を形成する際に、  When forming the wiring of the semiconductor integrated circuit device,
平坦な半導体基板上で、 On a flat semiconductor substrate,
絶縁膜上に銅成分を含む導電層を形成する工程と、 Forming a conductive layer containing a copper component on the insulating film;
上記の導電層をパターニングして配線を形成する工程と、 Patterning the conductive layer to form a wiring;
配線のすくなくとも側壁にバリァメタル層を形成する工程と、 Forming a barrier metal layer on at least the sidewall of the wiring;
3 I P 3 V—シクロシロキサン膜を少なくとも配線間に形成する工程と、 さらに他の絶縁膜を表面に形成する工程と、  A step of forming a 3 I P 3 V-cyclosiloxane film at least between the wirings, a step of forming another insulating film on the surface,
を含むことを特徴とする配線形成方法。 A wiring forming method comprising:
PCT/JP2007/067778 2006-09-08 2007-09-06 Semiconductor integrated circuit device, and wire forming method WO2008029956A1 (en)

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JP2005175060A (en) * 2003-12-09 2005-06-30 Jsr Corp Insulating film and method for forming the same, and composition for forming the same

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JP2011171736A (en) * 2010-02-17 2011-09-01 Renesas Electronics Corp Semiconductor device and method of manufacturing the same
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